Você está na página 1de 18

# CS M51A Summer13 Section 1 Logic Design of Digital Systems Lecture 11

August 1, 2013

3 Su 1

## Yutao He yutao@cs.ucla.edu 4532B Boelter Hall

https://courseweb.seas.ucla.edu/classView.php?term=131&srs=187154910
CSM51A-Sec.1 Su 13 L11.1 Y. He @ 8/1/13

Outline
Spec of Sequential Systems

Summary

CSM51A-Sec.1 Su 13

L11.2

Y. He @ 8/1/13

There is no quiz on Friday August 2nd HW #6
Be posted on-line tonight

CSM51A-Sec.1 Su 13

L11.3

Y. He @ 8/1/13

## Motivation: Lecture 2 Ex. 2 Revisit

Description:
A single light can be controlled by any one of three switches. Design a digital system that controls the light as follows:
One switch is the master on/off switch. If it is down, the light is off. When the master switch is up, a change in the position of one of other switches causes the light to change.
Switches

## Lights Off Off Off Off Off On On Off

On Off Off On

System

Light

CSM51A-Sec.1 Su 13

L11.4

Y. He @ 8/1/13

## Sequential Systems: Overview

(Hardware) Systems Analog Digital Seq. Comb.

Basic Concepts
Synchronous sequential systems Clocks States Finite state machines Mealy and Moore machines

Specification
Time behavior (I/O sequence) State transition table State diagram

Sync. Async.

Minimization Implementation
L11.5 Y. He @ 8/1/13

CSM51A-Sec.1 Su 13

## Definition of Sequential Systems

CSM51A-Sec.1 Su 13

L11.6

Y. He @ 8/1/13

## Sync. Vs. Async. Sequential Systems

Synchronous

Asynchronous

CSM51A-Sec.1 Su 13

L11.7

Y. He @ 8/1/13

Clock
An independent periodic reference signal Provided by
An internal crystal An external 60 Hz alternating current

## Make sure you know

When is the present (t) When is the next (t+1)
* back to the future

## When is the previous (t-1)

* forth to the past

CSM51A-Sec.1 Su 13

L11.8

Y. He @ 8/1/13

Time-Behavior Specification
Behavior of a sequential system can be specified by a sequence of input(s)/output(s) pairs with respect to the clock signal
Time t Input xi(t) Output zi(t) 0 1 2 ...

CSM51A-Sec.1 Su 13

L11.9

Y. He @ 8/1/13

## Example 7.1: Serial Decimal Adder

Addition is performed one digit at a time, starting from the LSB Output is generated at each time instant As a result, a 8-digit serial decimal adder needs 8 clock cycles to finish the calculation
s = x + y = 21638753+73652425 t 01234567 x(t) 3 5 7 8 3 6 1 2 y(t) 5 2 4 2 5 6 3 7 s(t) 8 7 1 1 9 2 5 9 c(t) 0 0 1 1 0 1 0 0

CSM51A-Sec.1 Su 13

L11.10

Y. He @ 8/1/13

State
Introduced to help memorize the complete input/output sequences Usually number of states are finite Itself is also a time function Two types of states are defined:
present state (PS): s(t) next state (NS): s(t+1)

CSM51A-Sec.1 Su 13

L11.11

Y. He @ 8/1/13

## State Description of Sequential Systems

A sequential system can be specified as a finite state machine (FSM) by specifying
output function: z(t) = H(s(t), x(t)) state transition function: s(t+1) = G (s(t), x(t))
Inputs x(t) Outputs z(t) Present State s(t)

## Next State s(t+1)

CSM51A-Sec.1 Su 13

L11.12

Y. He @ 8/1/13

## Example 7.3 - Serial Decimal Adder

Inputs: x(t), y(t) {0,1, , 9} Outputs: z(t) {0, 1, , 9} State: c(t) {0, 1} Initial State: c(0) = 0 Functions:
State transition function: c(t+1) =
1 if x(t)+y(t)+c(t) 10 0 otherwise

## Output function z(t) = (x(t)+y(t)+c(t)) mod 10

CSM51A-Sec.1 Su 13

L11.13

Y. He @ 8/1/13

## State Transition Table

An extended truth table for specifying output function and state transition function in a tabular form

PS

Inputs x(t)

## NS, Outputs z(t)

CSM51A-Sec.1 Su 13

L11.14

Y. He @ 8/1/13

## Example 7.4: Odd/Even Detector

Given a system whose input has two values a and b, and whose output also has two values, 0 and 1. The output at time t is 1 if the number of b s in the input x(0,t) is even, and 0 otherwise.
PS Inputs x(t) Inputs: x(t) {a,b} a b Outputs: z(t) {0, 1} Even Even, 1 Odd, 0 State: s(t) {Even, Odd} Odd Odd, 0 Even, 1 Initial State: s(0) = Even NS, Outputs z(t) t 01234567 x(t) a b b a b a b a z(t) 1 0 1 1 0 0 1 1
CSM51A-Sec.1 Su 13 L11.15 Y. He @ 8/1/13

State Diagram
A graphical specification of a sequential system

CSM51A-Sec.1 Su 13

L11.16

Y. He @ 8/1/13

## Example: State Diagram

Inputs x(t) a b Even Even, 1 Odd, 0 Odd a/1 b/0 Even Odd Odd, 0 Even, 1 a/0 PS

## NS, Outputs z(t)

b/1
CSM51A-Sec.1 Su 13 L11.17 Y. He @ 8/1/13

## Mealy and Moore Machines

Mealy Machine:
Its output depends upon both input and state

Moore Machine:
Its output depends only upon present state

inputs

logic for
outputs combinational logic for next state

outputs inputs

reg

reg

## logic for outputs

outputs

state feedback

state feedback

Mealy Machine

Moore Machine

CSM51A-Sec.1 Su 13

L11.18

Y. He @ 8/1/13

## Example 7.5 - A Moore Machine

CSM51A-Sec.1 Su 13

L11.19

Y. He @ 8/1/13

## How to Select State Names

Use integers as state names Example: A modulo-64 counter
Input: x(t) {0,1} Output: z(t) {0,1,,63} State: s(t) {0,1,,63} Initial State: s(0) = 0 Function:
* Transition function: s(t+1) = [s(t)+x(t)] mod 64 * Output function: z(t) = s(t)

CSM51A-Sec.1 Su 13

L11.20

Y. He @ 8/1/13

## How to Select State Names (Cont d)

Use state-vector approach:
state is represented by a vector s = (sn-1, , s 0)

Example:
A sequential system that counts the occurrence of 55 different events. When the count of event I is a multiple of 100, the output is z(t) = i, otherwise, z(t) = 0 Input: x(t) {1, 2, , 55} Output: z(t) {0, 1, 2, , 55} State: s(t) = (s55,,s1), si {0,1,,99} State: s(0) = (0,0,,0) Functions:
* Transition function: si(t+1) = * Output function:
CSM51A-Sec.1 Su 13

z(t) =

Y. He @ 8/1/13

L11.21

## Case Study 1: Finite Memory Systems

A sequential system has finite memory of length m is z(t) depends only on the last m input values:
z(t) = F(x(t-m+1), t))

Example 7.12:
z(t) =
p q if x(t-3,t) = aaba otherwise

## Finite memory of length four

All finite-memory machines are FSMs Not all FSMs are finite-memory
z(t) =
1 0 if number of 1 s in x(0, t) is even otherwise

CSM51A-Sec.1 Su 13

L11.22

Y. He @ 8/1/13

## Case Study 2: Pattern Detector

Detect sub-patterns in the input sequence Two types:
overlapped and non-overlapped

Example:
Input: x(t) {0,1} Output: z(t) {0,1} 1 Function: z(t) =
0 if x(t-3,t) = 1101 otherwise

CSM51A-Sec.1 Su 13

L11.23

Y. He @ 8/1/13

## Case Study 2a: Attack CS31 Project 3 in a CSM51A Way

A piano-playing software Buttonbeat
Note, Beat, Tune, A well-formed, note/beat/tune, A playable note/tune

Note:
a note letter a note letter followed by an accidental sign a note letter followed by a digit a note letter followed by an accidental sign followed by a digit

CSM51A-Sec.1 Su 13

L11.24

Y. He @ 8/1/13

## Case Study 3: Controller

A FSM that produces control signals as the states are traversed. Control signals determine actions performed by other parts of the system. Two types
Autonomous
* State transitions follow a fixed sequence of states, independent of any inputs except the clock.

Non-autonomous
* The transition is decided by external inputs

CSM51A-Sec.1 Su 13

L11.25

Y. He @ 8/1/13

## Vending Machine Controller

CSM51A-Sec.1 Su 13

L11.26

Y. He @ 8/1/13

## Vending Machine Controller (Cont d)

CSM51A-Sec.1 Su 13

L11.27

Y. He @ 8/1/13

State Minimization
Motivation:
High-level design may generate many redundant states Fewer states may mean fewer state variables To reduce the complexity and cost

Basic concept:
Two states are equivalent if they are impossible to distinguish from the outputs of the FSM, i. e., for any input sequence the outputs are the same
* (1) Output must be the same in both states * (2) Must transition to equivalent states for all input combinations

Basic Methods:
Table matching Implication Chart
CSM51A-Sec.1 Su 13 L11.28 Y. He @ 8/1/13

## Table Matching Procedure - Overview

Starting with the state table Step 1: Row matching with respect to outputs Step 2: Rename the newly partitioned classes Step 3: List their next state transitions by using new names Step 4: Check if partitions are same by column matching within classes
If no, go back to Step 1 If yes, The states are minimal

## Write the state table for the minimal states

CSM51A-Sec.1 Su 13 L11.29 Y. He @ 8/1/13

## State Minimization - Example 7.14

CSM51A-Sec.1 Su 13

L11.30

Y. He @ 8/1/13

## Example 7.14 (Cont d)

Row Matching:
P1 = (A, C, E) (B, D, F)

Column Matching:

CSM51A-Sec.1 Su 13

L11.31

Y. He @ 8/1/13

## Example 7.14 (Cont d)

Row Matching:
P2 = (A, C, E) (B, D) (F)

Column Matching:

Row Matching:
P3 = (A, C) (E) (B, D) (F)

Column Matching:

## P3 (A, C) (E) (B, D) (F) a 1 1 2 4 4 b 3 3 4 3 3 c 3 3 4 1 1

CSM51A-Sec.1 Su 13

L11.32

Y. He @ 8/1/13

## Example 7.14 (Cont d)

Column Matching:
P4 = (A, C) (E) (B, D) (F) = P3

## Stop: The states are minimal

CSM51A-Sec.1 Su 13

L11.33

Y. He @ 8/1/13

Summary
Specification of sequential systems
time-behavior state-transition table equation state diagram

## Several common types of sequential systems

pattern detectors Controller

## State equivalence and minimization

CSM51A-Sec.1 Su 13

L11.34

Y. He @ 8/1/13

Next Lecture
Chapter 8: Sections 8.1-8.7

CSM51A-Sec.1 Su 13

L11.35

Y. He @ 8/1/13