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BEE-402 ADVANCED INTEGRATED CIRCUIT DESIGN

Name: Matric No: Scoring Rubric

Marking scheme for Assignment Category Remarks Week Moderate Good Very good Clarity of basic concepts 1 2 4 5 and design The concepts and design should be explained properly Efficiency of using proper 1 2 4 5 software and design Software accuracy in input/output waveforms Software simulation 1 2 4 5 Presentation and Result The selection of suitable software 1 2 4 5 The report presentation and the clarity of the solution TOTAL MARKS:

ASSIGNMENT 1 Subject code & Name: BEE 402-Advanced integrated circuit design Submission date: 19.05.13 Title of Assignment Design ganged CMOS circuit and simulate the performance using mentor graphics software. Learning Outcomes and assessment criteria covered
CLO2: Construct moderate scale projects using EDA tools (C4, P5, A2)

Assessment criteria:
Design of AND, XOR and Half adder circuit using Ganged CMOS technique. Front end and backend analysis of IC using mentor graphics software. Performance analysis of delay, power, rise and fall time.

Introduction: Ganged CMOS also called as symmetric circuits. They are constructed with pair of inverters ganged together to perform a function. The construction proposed by Johnson a novel structure for a 2-input NOR. The gate consists of two inverters with shorted outputs, ratioed such that an inverter pulling down can overpower an inverter pulling up. This ratio is exactly the same as is used for Pseudo-nMOS gates. The difference is that when the output should rise, both inverters pull in parallel, providing more current than is available from a regular pseudo-nMOS pull up. The input capacitance of each input is 2. The worst-case pull down current is equal to that of a unit inverter, as it is found in the analysis of pseudo-nMOS NOR gates. The pullup current comes from two pMOS transistors in parallel and is thus 2/3 that is a unit inverter. Therefore the logical effort is 2/3 for a falling output and 1(4/3-1/3=1) for a rising output. The average effort is 5/3, which is better that that of a pseudo nMOS NOR and far superior to that of a static CMOS NOR gate. Questions: Front end
a) Design the half adder circuit using ganged CMOS technique. b) Design the schematic using mentor graphics software and check the simulated output. c) Anlayse the rise, fall delay and power.

Back end a) Draw the layout for the half adder circuit and do the DRC/LVS check. b) Layout the design and ensure physical layout is DRC/LVS clean. c) Extract the parasitic values using parasitic extraction.

Your report consists of i. Aim and apparatus required for the design ii. Draw the half adder circuit with truth table and logical expression. iii. Design half adder circuit using ganged CMOS iv. Simulate the design using mentor graphics software v. Draw the DA-IC schematic sheet for half adder suing mentor graphics software vi. simulated result using mentor graphics software. vii. Layout the design viii. Check the schematic and the layout using DRC/LVS check. ix. Conclude the results x. Attach ALL the necessary printout sheets and the errors occurred during the simulation.

Good Luck

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