MM54HC194 MM74HC194 4-Bit Bidirectional Universal Shift Register

November 1995

MM54HC194 MM74HC194 4-Bit Bidirectional Universal Shift Register

General Description
This 4-bit high speed bidirectional shift register utilizes advanced silicon-gate CMOS technology to achieve the low power consumption and high noise immunity of standard CMOS integrated circuits along with the ability to drive 10 LS-TTL loads This device operates at speeds similar to the equivalent low power Schottky part This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register It features parallel inputs parallel outputs right shift and left shift serial inputs operating mode control inputs and a direct overriding clear line The register has four distinct modes of operation PARALLEL (broadside) LOAD SHIFT RIGHT (in the direction QA toward QD) SHIFT LEFT INHIBIT CLOCK (do nothing) Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs S0 and S1 high The data are loaded into their respective flip flops and appear at the outputs after the positive transition of the CLOCK input During loading serial data flow is inhibited Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low Serial data for this mode is entered at the SHIFT RIGHT data input When S0 is low and S1 is high data shifts left synchronously and new data is entered at the SHIFT LEFT serial input Clocking of the flip flops is inhibited when both mode control inputs are low The mode control inputs should be changed only when the CLOCK input is high The 54HC 74HC logic family is functionally as well as pinout compatible with the standard 54LS 74LS logic family All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground

Features
Y Y Y Y Y

Typical operating frequency 45 MHz Typical propagation delay ns (clock to Q) Wide operating supply voltage range 2 6V Low input current 1 mA maximum Low quiescent supply current 160 mA maximum (74HC Series) Fanout of 10 LS-TTL loads

Connection Diagram

Dual-In Line Package

TL F 5323 1

Function Table
Inputs Mode Clear L H H H H H H H S1 S2 X X X X H H L H L H H L H L L L Clock X L Serial X X X X X H L X X X X H L X X X Parallel X X a X X X X X X X b X X X X X X X c X X X X X X X d X X X X X L QA0 a H L QBn QBn QA0 L QB0 b QAn QAn QCn QCn QB0 L QC0 c QBn QBn QDn QDn QC0 L QD0 d QCn QCn H L QD0 Outputs Q QB QC QD Left Right A B C D A

Order Number MM54HC194 or MM74HC194

H e high level (steady state) L e low level (steady state) X e irrelevant (any input including transitions)

u e transition from low to high level

a b c d e the level of steady-state input at inputs A B C or D respectively QA0 QB0 QC0 QD0 e the level of QA QB QC or QD respectively before the indicated steady-state input conditions were established QAn QBn QCn QDn e the level of QA QB QC respectively before transition of the clock the most-recent

u u u u u
X

C1995 National Semiconductor Corporation

TL F 5323

RRD-B30M115 Printed in U S A

Absolute Maximum Ratings (Notes 1

2)

Operating Conditions
Supply Voltage (VCC) DC Input or Output Voltage (VIN VOUT) Operating Temp Range (TA) MM74HC MM54HC Input Rise or Fall Times VCC e 2 0V (tr tf) VCC e 4 5V VCC e 6 0V Min 2 0 Max 6 VCC Units V V

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK IOK) DC Output Current per pin (IOUT) DC VCC or GND Current per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S O Package only Lead Temperature (TL) (Soldering 10 seconds)
b 0 5 to a 7 0V b 1 5 to VCC a 1 5V b 0 5 to VCC a 0 5V
g 20 mA g 25 mA g 50 mA

b 40 b 55

a 85 a 125

C C ns ns ns

b 65 C to a 150 C

1000 500 400

600 mW 500 mW 260 C

DC Electrical Characteristics (Note 4)

Symbol Parameter Conditions VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V VIN e VIH or VIL lIOUTl s20 mA 2 0V 4 5V 6 0V 4 5V 6 0V 2 0V 4 5V 6 0V 4 5V 6 0V 6 0V 6 0V 20 45 60 42 57 0 0 0 02 02 TA e 25 C Typ VIH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 15 3 15 42 05 1 35 18 19 44 59 3 98 5 48 01 01 01 0 26 0 26
g0 1

74HC TA eb40 to 85 C

54HC TA eb55 to 125 C

Units

Guaranteed Limits 15 3 15 42 05 1 35 18 19 44 59 3 84 5 34 01 01 01 0 33 0 33
g1 0

15 3 15 42 05 1 35 18 19 44 59 37 52 01 01 01 04 04
g1 0

V V V V V V V V V V V V V V V V mA mA

VIL

VOH

VIN e VIH or VIL lIOUTl s4 0 mA lIOUTl s5 2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA

VIN e VIH or VIL lIOUTl s4 0 mA lIOUTl s5 2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN e VCC or GND VIN e VCC or GND IOUT e 0 mA

80

80

160

Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power Dissipation temperature derating plastic N package b 12 mW C from 65 C to 85 C ceramic J package b 12 mW C from 100 C to 125 C Note 4 For a power supply of 5V g 10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst case VIH and VIL occur at VCC e 5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN ICC and IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY89

AC Electrical Characteristics VCC e 5V

Symbol fMAX tPHL tPLH tPHL tREM tS tS tW tH Parameter Maximum Operating Frequency Maximum Propagation Delay Clock to Q Maximum Propagation Delay Reset to Q Minimum Removal Time Reset Inactive to Clock Minimum Setup Time (A B C D to Clock) Minimum Setup Time Mode Controls to Clock Minimum Pulse Width Clock or Reset Minimum Hold Time any Input Conditions

TA e 25 C CL e 15 pF tr e tf e 6 ns Typ 50 17 19 Guaranteed Limit 35 24 25 5 20 20 9

b3

Units MHz ns ns ns ns ns ns ns

16 0

AC Electrical Characteristics CL e 50 pF
Symbol fMAX Parameter Maximum Operating Frequency Maximum Propagation Delay Clock to Q Maximum Propagation Delay Reset to Q Maximum Output Rise and Fall Time Minimum Removal Time Reset Inactive to Clock Minimum Set Up Time (A B C or D to Clock) Minimum Set Time Mode Controls to Clock Minimum Hold Time any Input Minimum Pulse Width Clock or Reset Maximum Input Rise and Fall Time Power Dissipation Capacitance (Note 5) Maximum Input Capacitance Conditions VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V

tr e tf e 6 ns (unless otherwise specified) TA e 25 C Typ 10 45 50 70 15 12 80 15 12 30 8 7 6 30 35 145 29 25 150 30 26 75 15 13 5 5 5 100 20 17 100 20 17

b 10 b3 b3

74HC TA eb40 to 85 C 5 24 28 183 37 31 189 37 31 95 19 16 5 5 5 125 25 21 125 25 21 0 0 0 100 20 18 1000 500 400

54HC TA eb55 to 125 C 4 20 24 216 45 37 216 45 37 110 22 19 5 5 5 150 30 25 150 30 25 0 0 0 120 24 20 1000 500 400

Units

Guaranteed Limits MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF 10 10 10 pF

tPHL tPLH

tPHL

tTHL tTLH

tREM

tS

tS

tH

0 0 0 80 16 14 1000 500 400

tW

30 89 8

tr tf

CPD CIN

77 5

Note 5 CPD determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC f a ICC

Logic and Timing Diagrams

TL F 5323 2

TL F 5323 3

MM54HC194 MM74HC194 4-Bit Bidirectional Universal Shift Register

Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J) Order Number MM54HC194J or MM74HC194J NS Package Number J16A

Molded Dual-In-Line Package (N) Order Number MM74HC194N NS Package Number N16E LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user
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