ECE 423 Designation Technical Elective

Digital VLSI Design

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Catalog Data

Principles of the design and layout of Very Large Scale Integrated (VLSI) circuits concentrating on the CMOS technology. MOS transistor theory and the CMOS technology. Characterization and performance estimation of CMOS gates. CMOS gate and circuit design. Layout and simulation using CAD tools. CMOS design of data-path subsystems. Design of finite state machines. Examples of CMOS system designs. Laboratory experience in CMOS VLSI design ECE 327, ECE 345 Three 50-minute sessions per week Four design assignments, each four 2-hour sessions, one project, 15 hours H. Wang, S. Tragoudas, S. Ahmed Credit Hours Textbooks

Prerequisites Lecture Laboratory Committee

Principles of CMOS VLSI Design. A Systems Perspective, 3rd Edition, by Neil H. E. Weste, Karman Eshraghian, Addison-Wesley, 2004 References Digital Integrated Circuits: A Design Perspective, Jan M. Rabaey, Prentice Hall, Inc., 1996 CMOS Digital Integrated Circuits: Analysis and Design, S.-M. Kang and Y. Leblebici, 2nd Edition, McGraw-Hill, Inc., 1999 Basic VLSI Design, D.A. Pucknell and K. Eshraghian, 3rd Edition, Prentice-Hall, Inc., 1994 Course Learning Outcomes / Expected Performance Criteria Upon completion of the course, the students should be able to: Design combinational, sequential, and arithmetic circuits using CMOS transistors. Design both static and dynamic CMOS circuits. Understand the performance metrics of CMOS circuits. Be able to evaluate and optimize the designed circuits. Perform transistor-level (SPICE) simulation to verify and evaluate the designed circuits. Perform layout design for CMOS circuits. Understand modern IC Layout design techniques, including Design Rule Check (DRC), Electrical Rule Check (ERC), Layout Versus Schematic (LVS), and layout parasitic extraction. Understand the challenges in high-speed digital VLSI design. Know the common techniques to improve circuit clock frequency and avoid timing violation problems. Understand the circuit structures of static and dynamic random access memories. Understand the challenges and circuit techniques in high-speed interconnect design. Understand basic I/O buffers and ESD circuits. Prerequisites by Topic Synthesis of digital logic design. Characteristics of MOS or CMOS devices Professional Component {Credit Hours} Mathematics Sciences General Ed. Eng. Science 2 Eng. Design 2

ECE 423

Digital VLSI Design Course Topics

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MOS transistor theory: MOS structure, threshold voltage, MOS I-V characteristics, second-order effects, parasitic capacitors in MOS devices {4 classes} CMOS processing technology and layout rules {2 classes} CMOS combinational circuit design: standard and complex logic gate design, ratioed logic, passtransistor logic, techniques to evaluate and optimize gate threshold voltage, noise margin, delay, and power consumption, optimal transistor and gate sizing, layout techniques for complex logic gates {10 class} CMOS dynamic circuits: basic dynamic circuits, Domino logic, NP Domino logic, signal integrity in dynamic circuits {3 classes} CMOS synchronous circuits: static and dynamic latch and D flip-flop (DFF) circuit design, DFF timing parameters, max-delay constraints, min-delay constraints, time borrowing, clock skew, techniques to improve clock frequency and avoid timing violations, synchronizers {10 classes} Arithmetic circuits: static adder circuit, transmission-gate-based adder, implementation of Manchester carry-chain adder, carry-bypass adder, carry-select-adder, carry-look-ahead adder, array multiplier, carry-save multiplier, shifter {6 classes} Memory circuits: architecture and building blocks of memory, SRAM and DRAM memory cells, operation of memory circuits {4 classes} Interconnect challenges: interconnect delay, cross-talk, buffer insertion, active and passive shielding {2 classes} I/O circuits and ESD protection: {1 class} Laboratory Topics 1. Design inverters and perform transistor resizing to adjust gate threshold, noise margin, and delay {4 lab sessions} 2. Layout design of multiple input NAND/NOR gates. Perform DRC, LVS, and post-layout simulation. Optimize the layout to minimize gate delay {4 lab sessions} 3. Design and layout a dynamic circuit, study the impact of charge-sharing, leakage, and cross-talk on the signal integrity of the design dynamic circuit {4 lab sessions} 4. Design and layout an adder circuit. Optimize the design to meet delay, power, and area budget {4 lab sessions} Projects Design and layout a CMOS functional unit. Optimize the circuit to meet delay, power, and area budget CAD and Computer Tools Used Cadence CAD Tools Assessment of the Contribution to Program Outcomes Outcome Assessed 1 2 3 x 4 x 5 x 6 x 7 x 8 x 9 10 11 x Hours 8 8 8 8 Hours 15

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Last Review Course Coordinator

Spring Semester 2007 Dr. H. Wang

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