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Candidate 1

hi friends...!!! hope these questions would be useful for you. I had three rounds , two rounds of technical and one round of technical +HR . I had only two questions in HR. Technical: 1) Explain about impedance matching. He gave me a circuit consisting of a PMOS with its drain connected to a transmission line of characteristic impedance of 50 ohms and the circuit was open at the end. He gave a rising edge of 0->1 at the gate and told me to find the waveform at the drain end... 2) what is layout mismatch? 3) what are multi-vdd and multi-Vt techniques? 4)what is clock skew? If I connect buffers to both the clocks will the clock skew be affected? 5) explain the operation of currentmirrors 6)explain the inverter characteristics 7)explain level restoration in pass transistors.what will be the contention at the output of pass transistor if you connect an inverter before the pass transistor and give the input to it. 8)what is dynamic power consumption ? how do you reduce it practically? 9) what is short circuit power dissipation? how will you minimize it? 10)explain the flow of DFT in encounter test 11) what are setup and hold time violations? 12)what is clock to Q delay? 13) He gave a circuit and asked me to calculate the clock period for that.. 14) what is the efficient way of clock gating? 15)explain the diff bet blocking and non-blocking statements and what do they sythesize after synthesis? 16)write a code for shifting a block of data from one reg to another.. 17)how will u find the number of occurences of 01101 (sequence detector.I drew sequence detector for this) 18) how will u write FSM for the above question? 19)Differentiate bet arrays and linked-lists in C 20)what is the diff bet C and C++ ? 21)what is call by value and call by reference in C? 22) what is an object and class in C++? 23)what is inheritance? 24) what is a static class? 25)what do u mean by metastability?( in digital design-flip flops) 26)write the code for multiplexer 27) If you use only one always block for FSM , will it be sequential or combinational? HR 1) what are your strengths? 2) Do you set goals in life? If yes what is your goal for next two years? Friends.... always be cool....don't get puzzled If he poses a question for which u don't get the answer immediately.... it may be due to pressure...think for a while with confidence, the interviewer will always help you and try to make you come out with answers. Be sure about what u have written in your resume. They will usually start off with project only , prepare well on your project. First impression is the best impression...! prepare for all the subjects u have put in ur resume...Always be positive and answer all questions with smile. :):) Don't worry friends...you all will be definitely placed in good company of your wish....Wish u all good luck.....!!!

Candidate 2
Dear all, these are the technical questions I have faced during the interview. Please go through your project, skills and Areas of Interest that you have mentioned in your resume. If he asks apart from that, you can honestly mention that you have not that much experienced with that subject and direct him to your interested topic. I felt that those people came here after thoroughly studied everyones resume!! 1. Explain about your best Project? 2. What is the difference between blocking and non-blocking statements? a=b a=>b b=c b=>c c=a c=>a Explain how the above statements going to synthesise? And explain each step of execution? 3. What is the difference between casex and casez? 4. What is clock tree synthesis? Explain prects and postcts optimisation? 5. Explain P&R flow in detail? 6. Explain setup time and hold time in detail? 7. How we can rectify hold time violation in physical synthesis? 8. How can you overcome set up time violation after manufacturing a chip? 9. Explain the entire synthesis flow? 10. What are the inputs given for a synthesis process? 11. What all are the input constrains for synthesis? 12. What is false path? 13. What is the optimisation techniques used for synthesis? 14. Explain about .lib file? 15. What is PVT variation? 16. What is the difference between I/O limited and Core Limited floor planning? 17. Explain about physical verification? 18. What is end of line violation in DRC? 19. What is .lef file contains? 20. What you mean by cross talk? What are the methods used to avoid cross talk?? 21. What all are the timing parameters of an inverter? 22. What you mean by On chip Variation? 23. What challenges u face in ur project? Hope that this information will be helpful to you. WISH YOU ALL THE BEST

Candidate 3
MY INTERVIEW QUESTIONS 1. Write a verilog code for any one complex situation upto now faced in m.tech and with its hardware implementation 2. Write a verilog code for sequence detector and its hardware implementation 3. How many always blocks are used in fsm coding ? explain in them in each always block significance. 4. And he gave a wavefrom asked me to write a verilog code. 5. Write a verilog code Specifications: there are 3 buses connected serially and each bus is having 8 flipflops. At the 3rd stage of output we have get output with a delay 3 units time. We give a 8bit input to the circuit. 6. Blocking and non blocking difference w.r.t verilog coding

7. Write a code for swapping of two numbers in verilog , C, perl 8. Write a C code for 2X 9. Design a 4X16 decoder using two 3X8 decoders. 10. What is theory behind the TCLK in the setup time. 11. What happens when switching activity is reduced. 12. Explain about scan based testing. Explain how it is applicable in testing. 13. Explain about the setup time ,hold time ,skew and wat happens if TCLK increase and decreases w.r.t setup time and hold time 14. While designing a fsm coding weather the diagram is sequential or combinational in nature. My suggestion is plz be perfect in your projects and basic of digital logic design. CANDIDATE 4: Hello Friends! These are the questions that I faced in the Interview. Please go through your projects especially the tools. Have a good idea in verilog, ASIC Synthesis flow and Back end flow. 1. What are the different steps from conceptualizing a chip to manufacturing? Explain in detail? 2. C program: int a; Int &b; Int &&c; a=*b=**c; What is the output of a? 3. Explain the process that happens when I press a key on my keyboard to when it is shown in the display? 4. There is a 640x480 display. The coordinates of the beginning is (0,0) and the end coordinate is (640,480). The starting address of the display is xABCD. What is the address of the coordinate (x,y)? 5. How will you implement (17 * a) in digital design?(Ans: use shift registers.) 6. I have two input variables A and B. Use digital design to shift B by A? 7. Implement a 4:16 Decoder using 3:8 Decoder? 8. Implement 5:32 Decoder using 3:8 Decoder and additional circuitry? 9. What is clock gating? Why do we apply low power technique to clock? 10. What are the different low power techniques? 11. What are the different parameters you consider to design a chip? Explain? 12. What is timing Parameters? 13. Explain Setup and hold time? 14. Why is setup time important? Explain hold violations? 15. STA: Three flip flop given with tcq,ts,th given. Flip Flop connected in cascade with some combinational logic in between with tpd given for all. What is the frequency of the circuit? Explain the flow of the data? I feel they asked questions only after looking through our resume. So be thorough with whatever you write. All the best! CANDIDATE 5 : my intel interview questions 1. explain backend flow (in clock tree synthesis skew is very important learn in detail about the skew) 2.design 17*2^x circuit (2^x circuit is decoder(x input -> 2^x output) and we can design 17 multiplier by four left shift registers in cascade and concatenate 1 at the end that is my answer am nt sure abt it better cross check. 3.given a 16bit register and asked to design a circuit such that it should output high when the no of 1's and 0's are equal in register i.e no. of 1's =no of 0's=8. ans:give the output of register to clk input of 4 bit asynchronous counter (negedge trigger flops) and give toggle input as 1 it counts the no. of 1's ,similarly give the output to another set of 4 flops and put an inverter at the clk input so it counts no. of 0's and at the end of 16th clk pulse compare the count.

4.inerter layout,inverter operation 5.why hold is not considered in clk frequency(why we need to maintain 50% duty cycle for clock) ans:it need not be 50% actually but it should be maintained high enough to support clk-q delay and hold constraint. hr qns: 1.if ur teamlead is not good will u report to the manager. ans:dnt say that ul report becoz they are chckng teamwork there. 2.if i put in domain other than physical design will u work? suggestions: Analyse the question in your mind, and understand what is being asked. If the question is not clear, your answer will be wrong. You may ask the question again politely, if you think it may help you to understand the question. Try to think of a solution, and feel free to say "Please can I have a couple of minutes to think"? Also you may request for hints if you think it may help. Generally speaking, the interviewer will give hints, and will try to push your brain to work, up until the point when your brain clicks. Your direction of thinking and approach is the key, even if you fail to answer. And if you haven't got a clue, do not be ashamed in saying "sorry". But do not attempt to answer if you know that you do not know the answer. An Example: Interviewer Asks: Can you tell me what is the max frequency a digital circuit may work? In case you are unable to answer, he may offer hints like: Do you know what is setup time or propagation delay? etc. Then he may actually draw a circuit, and mark propagation delays, setup times etc.. to again make you think towards the answer. So even if you do not know the answer, try to think on the spot using hints and direction given. Again, your approach and direction is very important. ->Remeber, they are interviewing to select you and not to reject you.