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A High-Voltage DCDC Converter With Vin/3Voltage Stress on the Primary Switches

Ting-Ting Song, Henry Shu-Hung Chung, Senior Member, IEEE, and Adrian Ioinovici, Fellow, IEEE

AbstractA high-voltage dc-dc converter with low voltage stress on the power switches and high output current capacity is presented. This converter exhibits three distinct features. First, the voltage stress on the primary switches is only one-third of the input voltage, so that switches of low voltage rating and thus of low on-resistance can be used. This leads to reduced conduction loss. Second, all the switches are soft-switched, so that the switching loss can be reduced. Third, the rectier is a current tripler, so that the output current capacity, and thus the power handling capacity of the converter are increased. A 5.1-kW, 1000-V/48-V dc-dc converter prototype has been built and tested. Experimental results are favorably compared with theoretical predictions. Index TermsDCDC conversion, high-voltage converter, high load current converter.

I. INTRODUCTION HE energy supplied to the low-voltage equipment in systems powered by a high dc voltage, such as the railway system, typically goes through multiple power conversion stages. For example, the electric power in the railway system is transmitted to the trains through high dc voltage (e.g., 1500 V) overhead lines and is inverted into a 3-phase ac voltage (e.g., 440 V, 60 Hz). The ac voltage is further transformed and rectied into a dc voltage (e.g., 110 V) for charging up the backup batteries and powering various control units on the train. It is energy-inefcient to use a low-frequency ac voltage as the means to perform the dc-dc conversion from the high voltage to low voltage (i.e., from 1500 to 110 V). An efcient approach is to perform the power conversion process through a high-frequency ac voltage. As high-voltage switching devices have high on-resistance, available dc-dc converters operating at high input voltage generally dissipate a substantial amount of energy of high-voltage in these elements. The on-resistance devices increases with their voltage-rating (BV) according to a , where . This nonlinear relationship: leads power electronics designers to explore new converter circuits that could reduce the device voltage requirement, so that switches of low on-resistance could be used.
Manuscript received August 7, 2006; revised February 13, 2007. This work was supported by a grant from the Research Grants Council of the Hong Kong Special Administrative Region, China (Project No.: CityU 112406). This paper was previously presented at the IEEE Power Electronics Specialists Conference 2006 and at the Applied Power Electronics Conference and Exposition 2007. Recommended for publication by Associate Editor F. Z. Peng. T.-T. Song and H. S.-H. Chung are with the Department of Electronic Engineering, City University of Hong Kong, Kowloon Tong, Kowloon, Hong Kong (e-mail: eeshc@cityu.edu.hk). A. Ioinovici is with the Department of Electrical and Electronics Engineering, Holon Institute of Technology (HIT), Holon 58102, Israel. Digital Object Identier 10.1109/TPEL.2007.909227

A typical dc-dc converter consists of two power conversion stages. In the rst stage, the dc input voltage is transformed into a high-frequency (HF) ac voltage which is applied across the primary of a HF transformer. The transformer is used for electrical isolation and providing an HF ac voltage across its secondary as determined by the turns ratio . In the second stage, consisting of a rectier, output lter and snubber, the output (load) voltage is obtained as a regulated dc voltage whose value is determined by the values of and of the duty cycle. In a conventional full-bridge (FB) converter, the four primary-side switches sustain the input voltage when they are off. In high-voltage applications, each switch can be realized by connecting two switches in series. Thus, each switch sustains only one-half of the input voltage in voltage-balanced networks. However, the equipment cost has to include that of the eight switches. This approach does not work well as far as dynamic balancing is concerned, since no switches are identical. In order to improve the efciency in systems with a high input voltage, a three-level topology was proposed. Based on the concept of the neutral-point-clamped inverters [1], a three-level (TL) converter has been introduced [2]. By using two dc-link capacitors to split the input voltage, operating the outer two and inner two switches in anti-phase, and using an additional ying capacitor and two extra diodes to clamp the voltage on the transistors in the off-state, the voltage stress on each switch results in only one-half of the input voltage. As a consequence, switches of low on-resistance can be used, resulting in much lower conduction losses. The dominant stream of research in FB and TL converters has had the purpose of developing soft-switching schemes to reduce the switching losses of the switches for further increasing the conversion efciency. A phase-shift control strategy allows the primary-side switches to turn on/off with zero-voltage-switching (ZVS) [3][6]. Different solutions have been proposed to extend the ZVS condition to light load: [7][16] for FB converters and [17][21] for TL converters. Another possibility of achieving soft-switching is to operate two of the power switches with ZVS and the other two with zero-current-switching (ZCS). To realize ZCS, various solutions have been proposed for keeping the primary current at zero during the freewheeling stage and for clamping the rectier voltage at an acceptable level. One recent solution was to add a few elements on the primary side, when a regenerative passive snubber was inserted in the secondary side [22][25]. Another conguration of the primary-side switches leading to also a voltage stress of a half of the input voltage across the power transistors in off-state was proposed in [26].

0885-8993/$25.00 2007 IEEE

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Fig. 1. Proposed converter with Vi/3 voltage stress on primary switches.

As the load current requirement continuously goes up, diodes of high current rating and high forward voltage drop have to be used in the secondary side. This results in an increase in the conduction losses in the rectier stage. This poses a signicant challenge for the high-voltage high-current dc-dc converters. In order to increase the load current capability, current-doubler rectiers have been used [27]. In [28], a current tripler that can increase three times the output current capability was proposed. However, the primary-side stage in [28] is a three-phase FB structure, in which the voltage stress on the power switches is equal to the input voltage. As a result, even if the converter in [28] is suitable for high-power applications, it cannot be used for high input voltage applications. In order to match the big advantage of the tripler rectier of [28] with the need of using the converter for a dc-dc conversion of a very high input voltage (as 1500 V), this paper presents an innovative structure. The power primary-side switches are arranged in three switch pairs. The mid-points of the switch pairs are connected to the primary side of a 3-phase HF transformer. The proposed converter achieves the following goals. 1) The voltage stress on each primary-side switch is only onethird of the input voltage. 2) All the switches are turned on and off with ZVS. 3) The output rectier is a current tripler [28] that has a high output current capability. The proposed converter is described in Section II, where its steady-state cyclically switching operation is presented. The dc analysis is performed in Section III, where the formula of the effective duty cycle is also derived. The small-signal transfer functions are derived in Section IV. Based on the design procedure presented in Section V, a 5.1-kW, 1000-V/48-V dc-dc converter prototype has been built and tested. The experimental results conrmed the theoretical predictions (Section VI).

II. PRINCIPLES OF OPERATIONS A. Circuit Structure The proposed converter is shown in Fig. 1. Three input dc-link capacitors , and are connected across the input voltage . They have the same capacitances, such that, due to the symmetry of the circuit, they split equally the line voltage. The . Three switch pairs, SP1, SP2, and voltage on each one is , and , respectively. Each SP3, are connected across switch pair is formed by two switches, which are operated in in SP1 is on, the voltage stress on , anti-phase. When . When is on, the voltage stress on , is . is The operation is similar for the switch pairs SP2 and SP3. Thus, the voltage stress on all switches in off-state is only one-third of the input voltage. No clamping diodes, as in TL converters, are needed for this purpose. The switching patterns applied to the switch pairs have a phase difference of 120 . The mid-pints of the switch pairs are connected to the primary of a delta-conand nected transformer through the dc blocking capacitors , which are of equal large capacitance. These capacitors take over the role of the ying capacitor in TL converters. As will be explained in Section III, the steady-state dc voltage of these . The voltages produced at the nodes X, Y, and capacitors is Z have phase differences of 120 . The turns ratio of the transformer is . to in The built-in diode-capacitor pairs, the switch pairs, are used to provide ZVS for all primary-side switches, in order to reduce the switching losses. A dead time is added between the gate signals applied to the switches in each switch pair. The secondary-side circuit is a three-phase rectier, namely a current tripler [28]. As the output current is shared by three

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identical parallel diode-inductor branches: , and , the tripler has several advantages over the mainstream rectiers having one output inductor and two or four diodes. Firstly, each output inductor carries only one third of the load current . Secondly, the current stress in each diode is reduced by one-third. Theoretically, it will be a lower rms current through each device, resulting in lower secondary conduction losses [28]. As the output voltage is determined by the voltages applied to the transformer primary, it can be adjusted by controlling the duty cycle of the switches in the switch pairs. B. Steady-State Switching Modes The converter goes cyclically through 15 modes in one switching cycle. Due to the switching operation symmetry, it is sufcient to analyze the rst ve modes which cover a period . At any time, three out of the six primary switches (i.e., of ) are switched on. The timing diagram of one-third of the switching cycle is given in Fig. 2. Fig. 3 shows the modes of operation. Fig. 4 shows the timing diagram of the whole in the gure shows the voltage switching cycle. The voltage between nodes and . As the durations of and are equal, the average value of is . As the steady-state average voltage across each transformer winding is zero (i.e., ), the average voltage of is . Similarly, by considering the nodes and , the average voltage of is also . Detailed derivations will be given in Section III-A. and are turned During the operation in the rst and are turned off. on, and [Fig. 3(a)]: , and are turned 1) Mode 0 [Before on. The converter is in the freewheeling stage. The voltages across the transformers windings are zero. The currents in the primary and secondary windings keep constant. The three and are on, in order to provide output inductors share . in and , respectively. That is the constant current

(1) The above formulas will be proven when the transition to a freewheeling mode (i.e., the last mode in each ) will be explained. , and By using Kirchhoff s Current Law (KCL) at nodes , respectively
Fig. 2. Timing diagram of one-third of a switching cycle.

On the primary side of the transformer

(2) Thus, the rectier diode currents are (4)

(3)

(5)

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Fig. 3. Modes of operation. (a) Mode 0 [before t ]. (b) Mode 1 [t

;t ]

. (c) Mode 2 [t

;t ]

. (d) Mode 3 [t

;t ]

. (e) Mode 4 [t

;t ]

. (f) Mode 5 [t

;t ]

By applying the Kirchhoff s Voltage Law (KVL)

to a positive value and Thus

goes from zero to a negative value.

(6) (8) (7) As decreases and maintains a constant current of has to turn on in order to provide the difference of . With , by considering the loop on the primary side, one can nd (9)

2) Mode 1 [Fig. 3(b)]: At turns off with ZVS because of the presence of . The current begins and discharge . As typically for a transition to charge from a freewheeling stage towards an energy transfer stage (passive topology to active topology transition), only the energy in the transformer leakage inductances is available for achieving , the winding YZ can such a function. As be considered as a short-circuit, and thus its leakage inductance does not participate in providing energy for the above operation. As and increases from zero

(10) (11)

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giving the duration of this stage (12) (29) (13) The values of the main voltages and currents at (14) result in (30) (31)

. where , and are turned on, the voltages on the secAs ondary windings are all zero (15) The currents owing through the primary windings are (32) (33) (16)

(17)

(34) (35)

(18) (19) (20) (36) (21) The currents owing through the secondary windings are (22) (23) (24) The currents through , and result in (38) (39) (37)

(25) (40) (26)

(27) (41) is completely discharged and Mode 1 ends when . That is charged up to is (28) 3) Mode 2 conducting and the rst one with [Fig. 3(c)]: At , as starts is turned on with ZVS (as the two stages, conducting, and the second one with

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conducting, are the same from the point of view of the equations governing their operation, they are considered here as the same topology). According to Fig. 3(c)

(54) (55) (56)

(42) , and are still turned on because the increasing primary currents are still not sufcient to provide the load current. The voltages across the secondary windings are zero (43) As typically found in FB and TL converters with ZVS, this phenomenon causes a loss of the secondary (effective) duty-cycle. Even if the primary circuit is in the on topology, the secondary one is still in the freewheeling state

[Fig. 3(d)]: This is the rst energy transfer 4) Mode 3 stage in the cycle. As shown in Fig. 3(d)

(57) (58) The currents in the primary and secondary windings are almost constant (59) (60)

(44) (45)

(61) (62)

(46)

(47) The reected currents on the secondary side are

[Fig. 3(e)]: According to the PWM action, 5) Mode 4 . At is turned the on stage is ended at . divides into two off with ZVS due to the presence of from zero and discharging from currents for charging . In this mode, the energy of the output inductor, which is reected to the primary side, is sufcient for assuring ZVS of the switches, even at light load. This is typical for all FB and TL converters at the transition from a transfer energy (active) stage to a freewheeling one (passive stage). By using simple circuit theory applied to Fig. 3(e), one gets

(48) (49) (50) (51) Mode 2 ends when the primary current reaches the reected , and thus and secondary current . A new energy transfer stage begins. results From (49), the loss of the effective duty cycle in (52) Based on (44)(48) (53) (65) (64) so that (63)

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The currents remain almost unchanged

(66) (67) (68) (69) is charged up to [i.e., Mode 4 ends when and is completely discharged [i.e., Thus, at

(70) The converter enters into the freewheeling stage. The currents in the transformers windings are kept constant during the transition due to the leakage inductances of the windings. 6) Mode 5 [Fig. 3(f)]: As at starts conducting and, soon after this instant, turns on with ZVS. As these two topologies are similar from the point of view of the equations governing their operation, they will be consid, and are turned-on, ered here as the same mode. As
Fig. 4. Timing diagram of the whole switching cycle.

(71) (72) That is, the converter operates in the rst freewheeling stage of a switching cycle. The currents in the primary windings remain constant so that

III. STEADY-STATE CHARACTERISTICS A. Steady-State Voltages across Capacitors , and

(73) (74) Thus, on the secondary side (75) (76) (77) are conducting in order to provide the constant curin and , respectively. rent intervals, the converter will operate in For the next two a similar way, the transition taking place in the switch pair SP2, and then in the switch pair SP3, arriving in the last Mode at the diagram described in Mode 0. The main converter waveforms for a full steady-state cycle are given in Fig. 4. and

The converter can be seen as an equivalent structure of three isolated identical buck converter modules with their inputs connected in series and their outputs connected in parallel, operating with the same duty cycle in a switching period. Thus, the symmetry in the component values and in switch pairs operation assures the equal voltage distribution among the three input capacitors. The capacitors have large values, such that their voltages can be considered as constant during a switching cycle. The situation is the same as in three-level converters where the input voltage is halved equally by the two input capacitors. B. Steady-State Voltages across Capacitors and

The steady-state average voltages across the primary windings over are zero (78) where , and are the average windings , and , respectively. and Thus, the capacitor voltages, by averaging the voltages between the nodes , respectively. and the nodes and pressed as voltages across can be obtained and , and can also be ex(79) (80)

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Thus (81) (82)

and (83) becomes

(85) According to the switching diagram (Fig. 4), the switches pointerval are as follows. sitions in each : and are turned on, resulting in 1) Interval I for DT (except for the commutation time), for (except for the commutation time). increases in a in the rst ZVS transition sinusoidal manner from zero to and decreases from to 0 in the second ZVS time . transition time 2) Interval II : and are turned on, resulting in for (except for the commutation time), for (except for the commutation time). decreases from to zero, and increases from zero to (both in a sinusoidal manner) during the rst ZVS transition stage of increases from 0 to , and interval I decreases from to zero for the second ZVS transition time . : and are turned-on, resulting 3) Interval III = 0, for in (except the commutation time), for (except the commutation time), decreases from to zero in a sinusoidal manner for the rst ZVS transition time in ), and increases from 0 to for the Interval III . second ZVS transition time As the parasitic capacitances of all switches - are equal , the transition of each upper switch and, reare governed by spectively, of each lower switch the same equations, so that the transition times for the upper, and respectively lower switches, are equal. That is, . As a result, by solving the integrals in (81) and (82), one gets: . C. DC Input-to-Output Voltage Ratio and Effective Duty Cycle The duty cycle of the converter is dened as the conduction time of the upper switch in each switch pair with respective to one-third of the switching period. Based on the energy balance between the input and output energy in a steady state switching cycle, the dc input-to-output voltage ratio can be shown to be (90) If the short ZVS commutation times are neglected, (85) gives

(86) The secondary (effective) duty-ratio can be expressed as

(87) and thus (86) can be expressed

(88)

D. Elements Design for ZVS The load range is determined by the minimum load current that can ensure the zero-voltage switching of all switches. As the commutation from a freewheeling stage to an active energy energy is available transfer stage is more difcult (only the is made accordingly: the energy in this case), the design of stored in the leakage inductances involved in the commutation process has to be higher than the energy in the equivalent caof the switches involved in the pacitance of the capacitors resonance path (i.e., 2 )

(89) i.e., in order to assure ZVS for a passive to active transition from a minimum load of , the minimum has to be

IV. AC SMALL-SIGNAL CHARACTERISTICS For the sake of simplicity in the analysis, all components are assumed to be ideal and . Since the ZVS commutation durations of the switch pairs are very short, as compared with the switching period, they are neglected in the analysis. Each one of the main switching modes (energy transfer are given in Fig. 5 and or freewheeling) in a switching cycle can be described by an equation of the form (91)

(83) According to (29) and (52) (84)

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A. Control-to-Output Transfer Function By applying the state-space averaging method

(98) (99)

where and respectively

are the averaged state vector and input vector,

Fig. 5. Equivalent circuits of the main switching modes. (a) Energy transfer of the Interval I [t ; t ]. (b) Energy transfer of the Interval II [t ; t ]. (c) Energy transfer of the Interval III [t ; t ]. (d) Freewheeling stage of Intervals I, II, and III.

By introducing small-signal perturbations into (98) and (99), it can be shown that

where

is the mode of operation

(100) (101)

where

By imposing

and using (97)

(102) The small-signal characteristics of the converter are studied , and by introducing ac perturbations into (92) (93) (94) (95) (96) where , and are the steady-state values of , and , respectively. By using (87) and substituting (92)(96) into (91), we have (97) (104) where and . Since

(103) By substituting (102)(103) into (100), it can be shown that

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TABLE I COMPONENT VALUES USED IN THE PROTOTYPE

Thus, by using (101) and (104), it can be shown that the conis equal to trol-to-output transfer function

Fig. 6. XY-plot of the switch voltage (v ) and the gate signal (v ) in SP3 at the full load condition. (a) S . (b) S . [x-axis (v ): 100 V/div, y-axis (v ): 5 V/div].

(105) Thus, the input-to-output transfer function by using (107) and (101) B. Input-to-Output Transfer Function By imposing into (97) (106) By substituting (106) into (100), it can be shown that V. SIMPLIFIED DESIGN PROCEDURES A simplied design procedure is given as follows. 1) The value of is determined by using (88) (109) where is the designed minimum effective duty cycle. is determined by using (90). 2) The value of 3) The selection of the switches is based on the consideraand b) tions: a) the voltage stress on the switches is . the current stress is (108) is determined

(107)

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Fig. 7. XY-plot of the switch voltage (v ) and the gate signal (v ) in SP3 at 62% load condition. (a) S . (b) S . [x-axis (v ): 100 V/div, y-axis (v ): 5 V/div]. Fig. 8. Enlarged waveforms of i , and v , and gate signals to S and S v : ; v : (10 V/div) (Timebase: 1  s/div). (a) (100 V/div), i (20 A/div), v Full load. (b) 62% load.

4) The minimum values of the output inductor and capacare determined by considering the current ripple itor through and the voltage ripple across . It can be shown that (110)

(111) VI. EXPERIMENTAL RESULTS A 1000-V/48-V dc-dc converter prototype has been built. The designed output power is from 3.2 kW (62% load) to 5.1 kW (100% load). Based on the design procedures in Section V, the component values are given in Table I. From (109), for V and V, and considering , it results . A transformer with 6:5 windings turns has been chosen. By choosing A and nF and using step 2) in Section V, the results give H. H is chosen in the prototype. Figs. 6 and 7 show the XY plot of the switch voltage and the gate signal of and in SP3 at the full load and 62% load conditions, respectively. They are all in L-shape. This implies that the switch voltage has become zero before dictating the ON signal to the gate, and remains zero after dictating the OFF signal to the gate. Thus, the ZVS commutation of the switches and can be clearly noticed.

The enlarged waveforms of , and , and gate signals to and at the full load and 62% load are shown in Fig. 8. Comparing Fig. 8(a) and (b), when the load current is reduced (i.e., from full load to 62% load), has moved close to zero before is increased to one-third of the supply voltage, giving the limit of achieving ZVS. As discussed in Section III-C, the . It ZVS range can be adjusted by changing the value of should be noted that parasitic ringing between the leakage inductance and the diodes junction capacitances, which appears at the turn-off of a rectier diode, can be tackled with an appropriate snubber, such as the one proposed in [20]. At the full-load condition, Fig. 9 shows the theoretical and experimental small-signal characteristics of the converter and Fig. 10 shows the voltage and current waveforms (i.e., and ) of the output rectier, and the voltages across the transformer winding XY (i.e., ). The waveforms are similar to the theoretical waveforms shown in Fig. 2. The efciencies of the prototype under different load conditions have been measured and are given in Fig. 11. The losses in the power components are shown in Table II. The major losses are in the passive components, including the capacitors, transformer, and the rectier, while the losses in the switches constitute only about 3.24% of the input power. The experimental results have demonstrated the objectives of the proposed structure that the voltage stress on the switches is only one-third of

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Fig. 9. Experimental and theoretical small-signal characteristics. (a) [Experimental].

(s) [Theoretical]. (b)

(s) [Experimental]. (c)

G (s) [Theoretical]. (d) G (s)

Fig. 11. Efciency of the prototype at different loading conditions.

Fig. 10. Voltage and current of the secondary rectier (i : 50 A/div, v : 200 V/div) and voltage on one of the transformer (v : 250 V/div) windings. (Timebase: 2  s/div).

the input voltage, and the switches are turned on and off with ZVS. A theoretical comparative study between the proposed converter structure and the classical FB converter has been conducted with a SPICE simulator. The two converters are designed for the same nominal input and output voltage, and load current.

It is found that the efciency of the proposed converter has an improvement of 5% to 10%, because the on- resistance of the high-voltage switches needed in the primary of the FB converter (2 series transistors for each switch) is higher than the one used in the proposed converter. VII. CONCLUSION A high-voltage dc/dc converter with low-voltage stress on the primary switches and an output current tripler has been proposed. By using an original structure of the primary side, the

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TABLE II LOSSES IN THE POWER COMPONENTS

voltage stress on the power switches is reduced to only one-third of the input voltage, allowing thus for the use of transistors of low-voltage rating and low on-state resistance. The conduction losses are considerable reduced. This novel primary structure matches the output current tripler, which allows for an increasing in the load and power handling capacity. The output voltage is controlled by adjusting the duty cycle of the switches in each switch pair. All the switches are turned-on/off with softswitching, allowing for minimal switching losses. The operating principles of the converter have been demonstrated and studied on a 5.1-kW, 1000-V/48-V prototype. The measurements of the efciency under different loads proved the expected advantages of the new converter. REFERENCES
[1] A. Nabae, I. Takahashi, and A. Akagi, A new neutral-point clamped PWM inverter, IEEE Trans. Ind. Appl., vol. 19, no. 5, pp. 518523, Sep./Oct. 1981. [2] J. Pinheiro and I. Barbi, The three-level ZVS-PWM DC-to-DC converter, IEEE Trans. Power Electron., vol. 8, no. 4, pp. 486492, Oct. 1993. [3] R. Fisher, K. Ngo, and M. Kuo, A 500 kHz, 250 W dc-dc converter with multiple outputs controlled by phase-shifted PWM and magnetic ampliers, in Proc. High Frequency Power Conv., May 1988, pp. 100110. [4] L. H. Mweene, C. A. Wright, and M. F. Schlecht, A 1 KW, 500 KHz front-end converter for a distributed power supply system, in Proc. IEEE Applied Power Electronics Conf. (APEC), 1989, pp. 423432. [5] J. Sabate, V. Vlatkovic, R. Ridley, F. Lee, and B. Cho, Design considerations for high-voltage high-power full-bridge zero-voltage-switched PWM converter, in Proc. IEEE Applied Power Electron. Conf. (APEC), 1990, pp. 275284. [6] R. Redl, N. Sokal, and L. Balogh, A novel soft-switching full-bridge DC-DC converter: Analysis, design considerations, and experimental results at 1.5 KW, 100 KHz, in Proc. IEEE Power Electron. Specialists Conf. (PESC) Rec., 1990, pp. 162172. [7] J. Sabate, V. Vlatkovic, R. Ridley, and F. Lee, High-voltage high-power ZVS full-bridge PWM converter employing an active snubber, in Proc. IEEE Applied Power Electron. Conf. (APEC), 1991, pp. 158163. [8] G. Hua, F. Lee, and M. Jovanovic, An improved full-bridge zero-voltage-switched PWM converter using a saturable inductor, in Proc. IEEE Power Electronis Specialist Conf. (PESC) Rec., 1991, pp. 189194. [9] R. Redl, L. Balogh, and D. Edwards, Optimum ZVS full-bridge dc/dc converter with PWM phase-shift control: Analysis, design considerations, and experimental results, in Proc. IEEE Applied Power Electronics Conf. (APEC), 1994, pp. 159165. [10] G. Moschopoulos and P. Jain, A PWM full-bridge converter with load independent soft-switching capability, in Proc. IEEE Applied Power Electron. Conf. (APEC), 2000, pp. 7985.

[11] R. Ayyanar and N. Mohan, Novel soft-switching dc-dc converter with full ZVS range and reduced lter requirementPart I: regulated output applications, IEEE Trans. Power Electron., vol. 16, pp. 184200, Mar. 2001. [12] C. Qiao and K. Smedley, An isolated full-bridge boost converter with active soft-switching, in Proc. IEEE Power Electron. Specialists Conf. (PESC), 2001, pp. 896903. [13] P. Jain, W. Kang, H. Soin, and Y. Xi, Analysis and design considerations of a load and line independent zero voltage switching full bridge dc/dc converter topology, IEEE Trans. Power Electron., vol. 17, no. 5, pp. 649657, Sep. 2002. [14] G. Koo, G. Moon, and M. Youn, Analysis and design of phase-shift full bridge converter with series-connected two transformers, IEEE Trans. Power Electron., vol. 19, no. 2, pp. 411419, Mar. 2004. [15] Y. Jang and M. Jovanovic, A new family of full-bridge ZVS converters, IEEE Trans. Power Electron., vol. 19, no. 3, pp. 701708, May 2004. [16] G. Koo, G. Moon, and M. Yoon, New zero-voltage-switching phaseshift full-bridge converter with low conduction losses, IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 228235, Feb. 2005. [17] J. Pinheiro and I. Barbi, Wide load range three-level ZVS PWM DC-to-DC converter, in Proc. IEEE Power Electronics Specialist Conf. (PESC) Rec., 1993, pp. 171177. [18] X. Ruan, D. Xu, L. Zhou, B. Li, and Q. Chen, Zero-voltage switching PWM three-level converter with two clamping diodes, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 790799, Aug. 2002. [19] F. Canales, P. Barbosa, M. Burdio, and F. Lee, A zero-voltageswitching three-level DC/DC converter, in Proc. 22nd Int. Telecommunications Energy Conf. (INTELEC), 2000, pp. 512517. [20] Y. Jang and M. Jovanovic, A new three-level soft-switched converter, IEEE Trans. Power Electron., vol. 20, no. 1, pp. 7581, Jan. 2005. [21] X. Ruan, Z. Chen, and W. Chen, Zero-voltage-switching PWM hybrid full-bridge three-level converter, IEEE Trans. Power Electron., vol. 20, no. 2, pp. 395404, Mar. 2005. [22] T. Song, N. Huang, and A. Ioinovici, A family of zero-voltage and zero-current switching (ZVZCS) three-level DC-DC converters with secondary-assisted regenerative passive snubber, IEEE Trans. Circuits Syst. I, vol. 52, no. 11, pp. 24732481, Nov. 2005. [23] T. Song, N. Huang, and A. Ioinovici, A zero-voltage and zero-current switching three-level DC-DC converter with reduced rectier voltage stress, in Proc. IEEE Applied Power Electronics Conf. (APEC), 2004, vol. 2, pp. 10711077. [24] T. Song, N. Huang, and A. Ioinovici, DC and small-signal analysis, and design of a novel ZVZCS three-level converter with reduced rectier voltage stress, in Proc. Power Electronics Specialist Conf. (PESC), 2004, pp. 40934099. [25] T. Song, N. Huang, and A. Ioinovici, A zero-voltage and zero-current switching three-level DC-DC converter with reduced rectier voltage stress and soft-switching-oriented optimized design, IEEE Trans. Power Electron., vol. 21, no. 5, pp. 12041212, Sep. 2006. [26] I. Barbi, R. Gules, R. Redl, and N. Sokal, DC-DC converter: Four = VB =2, capacitive turn-off snubbing, ZV turnswitches VB on, IEEE Trans. Power Electron., vol. 19, no. 4, pp. 918927, Jul. 2004. [27] X. Ruan, B. Li, J. Wang, and J. Li, Zero-voltageSwitching PWM three-level converter with current-doubler-rectier, IEEE Trans. Power Electron., vol. 19, no. 6, pp. 15231532, Nov. 2004. [28] M. Xu, J. Zhou, and F. Lee, A current-tripler dc/dc converter, IEEE Trans. Power Electron., vol. 19, no. 3, pp. 693700, May 2004.

Ting-Ting Song received the B.S. and M.S. degrees from the Department of Electrical Engineering, Sichuan University, Chengdu, China, in 1999 and 2002, respectively. She is currently pursuing the Ph.D. degree from the Department of Electronic Engineering, City University of Hong Kong. She was a Research Assistant with the Department of Electrical Engineering, Sichuan University, from 2002 to 2004. Her research interests include dc/dc and ac/dc converters.

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Henry Shu-Hung Chung (M95SM03) received the B.Eng. degree in electrical engineering in 1991 and the Ph.D. degree in 1994, both from The Hong Kong Polytechnic University. Since 1995, he has been with the City University of Hong Kong (CityU). He is currently professor of the Department of Electronic Engineering and Chief Technical Ofcer of e.Energy Technology Limitedan associated company of CityU. His research interests include time- and frequency-domain analysis of power electronic circuits, switched-capacitor-based converters, random-switching techniques, control methods, digital audio ampliers, soft-switching converters, and electronic ballast design. He has authored six research book chapter and over 250 technical papers, including 100 refereed journal papers in his research areas, and holds ten patents. Dr. Chung was IEEE Student Branch Counselor and Track Chair of the Technical Committees on Power Electronics Circuits and Power Systems of IEEE Circuits and Systems Society during 19971998. He was Associate Editor and Guest Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSPART I: FUNDAMENTAL THEORY AND APPLICATIONS during 19992003. He is currently an Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS. He was awarded the Grand Applied Research Excellence Award in 2001 from the CityU.

Adrian Ioinovici (M84SM85F04) received the electrical engineering degree in 1974 and the Dr.Eng. degree in 1981, both from Polytechnical Institute of Iasi, Iasi, Romania. In 1982, he joined the Holon Institute of Technology, Holon, Israel, where he is currently a Professor in the Electrical and Electronics Engineering Department. During 19901995, he was a Reader and then a Professor in the Electrical Engineering Department, Hong Kong Polytechnic University. His research interests are in simulation of power electronics circuits, switched-capacitor-based converters and inverters, soft-switching DC power supplies, and three-level converters. He is the author of the book Computer-Aided Analysis of Active Circuits (New York: Marcel Dekker, 1990) and of the chapter Power Electronics in the Encyclopedia of Physical Science and Technology (Academic Press, 2001). He has published more than 100 papers in circuit theory and power electronics. Dr. Ioinovici has been Chairman of the Technical Committee on Power Systems and Power Electronics of the IEEE Circuits and Systems (CAS) Society. He has served as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI and of the Journal of Circuits, Systems, and Computers. He has been an Overseas Advisor of the IEICE Transactions of Japan. He was Chairman of the Israeli chapter of the IEEE CAS Society between 19851990 and served as General Chairman of the Conferences ISCSC86, ISCSC88 (Herzlya, Israel), SPEC94 (Hong Kong), organized and Chaired special sessions in Power Electronics at ISCAS91, ISCAS92, ISCAS95, ISCAS2000, and was a member of the Technical Program Committee at the Conferences ISCAS91- ISCAS95, ISCAS06, PESC92-PESC95, Track Chairman at ISCAS96, ISCAS99-ISCAS2005, Co-Chairman of the Special Sessions Committee at ISCAS97, co-chairman of the Tutorial Committee at ISCAS06, and designed co-chair, Special Session Committee at ISCAS10 Paris. He was a Guest Editor of special issues of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI (August 1997 and August 2003) and of a Special Issue on Power Electronics of the Journal of Circuits, System and Computers (Aug. 2003).