BSC6900 Hardware System Structure

BSC6900 Hardware System Structure
www.huawei.com
Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.
Contents
1 BSC6900 System Overview 2 BSC6900 Hardware Structure 3 BSC6900 Signal Flows
Page2
RNC in WCDMA System

UE
Uu
UTRAN
Iu
CN
Iu-CS
RNC
Iub NodeB
b Iu
CS Iu-PS
Iur
NodeB PS Iu-BC Iub
NodeB
RNC
CBC
Page3
Capacity
HW68 R11 Board
Page4
Capacity
HW69 R11 Board
Page5
Contents
Page6
Contents
2 BSC6900 Hardware Structure
2.1 BSC6900 Cabinets and Subracks 2.2 BSC6900 Boards 2.3 BSC6900 Cables
Page7
BSC6900 Cabinets
MPR: Main processing rack EPR: Extended processing rack MPS: Main processing subrack EPS: Extended processing subrack
EPS EPS EPS EPS
MPS
EPS EPR
MPR
Full Configuration
Page8
BSC6900 Cabinets
Item Outline Specification 2200 H 600 Height of available 46U space Weight 140~350kg dimensioning (mm) W 800 D
Power consumption RSR: 4,650W RBR: 4,660 W
Front View
Rear View
Page9
BSC6900 Subrack

12 U shielding subrack of Huawei 28 slots with backplane is positioned in the middle
Front View
Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved. Page10
Rear View
Contents
Page11
Boards in MPS
14 15 16 17 18 19 20 21 22 23 24 25 26 27
Rear board
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
O M U a
O M U a
R I N T
R I N T
R I N T
R I N T
Backplane C S U a
00
Backplane
C S U a
01
Front board
S P U a
02
S P U a
03
S P U a
04
S S P C U U a a
05 06
S C U a
07
D P U b
08
D P U b
D P U b
D P U b
11
G C U a
12
G C U a
13
09 10
Page12
Boards in EPS
14 15 16 17 18 19 20 21 22 23 24 25 26 27
Rear board
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
Backplane
Backplane S P U a
00
Front board
S P U a
01
S P U a
02
S P U a
03
S P U a
04
S S P C U U a a
05 06
S C U a
07
D P U b
08
D P U b
D P U b
D P U b
11
D P U b
12
D P U b
13
09 10
Page13
RNC Logical Structure
Subsystem
Clock signal
clock synchronization subsystem To NodeB To other RNC To MSC To SGSN BAM BAM LMT/M2000 transport subsyste m switching subsystem
RNC
service service service processing processing processing subsystem subsystem subsystem
Page14
Switching Subsystem
MPS
14 15 16 17 18 19 20 21 22 23 24 25 26 27
Rear board
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
O M U a
O M U a
R I N T
R I N T
R I N T
R I N T
Backplane C S U a
00
Backplane
C S U a
01
Front board
S P U a
02
S P U a
03
S P U a
04
S S P C U U a a
05 06
S C U a
07
D P U b
08
D P U b
D P U b
D P U b
11
G C U a
12
G C U a
13
09 10
Page15
Switching Subsystem
EPS
14 15 16 17 18 19 20 21 22 23 24 25 26 27
Rear board
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
Backplane
Backplane S P U a
00
Front board
S P U a
01
S P U a
02
S P U a
03
S P U a
04
S S P C U U a a
05 06
S C U a
07
D P U b
08
D P U b
D P U b
D P U b
11
D P U b
12
D P U b
13
09 10
Page16
Switching Subsystem
Inter-Subrack Connection
Page17
Switching Subsystem

SCUa: Switching and Control Unit High-speed backplane channel in each subrack
Page18
Switching Subsystem
Functions
Providing internal Medium Access Control (MAC) switching
Enabling convergence of ATM and IP networks Providing a service switching channel for EPS Providing an OM channel for EPS Distributing timing signal and RFN signal to EPS boards
Page19
SCUa Board
SCUa
Functions
Main control board for configuration and maintenance Support GE Switching for local subrack Provide synchronous clock and time synchronous information Locate in 6th and 7th slot in active and standby mode Work in full-interconnection and dual-plane mode among subracks
RUN ALM ACT RESET

LINK ACT
0 1 2 3
Working mode
LINK ACT
6 7
LINK ACT
10/100/1000BASE-T
Port Name
Function
Type
RJ45
8 9 10 11
10/100/1000BASE-T For inter-subrack connection
COM CLKIN
Serial port for commissioning
RJ45
CLKIN
COM
Receiving the 8 kHz and the 1PPS RJ45 timing signals from the GCUa/GCGa
TESTO UT
PARC
TESTOUT
Test the timing signal output
Page20
SMB male
Service Processing Subsystem
MPS
14 15 16 17 18 19 20 21 22 23 24 25 26 27
Rear board
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
O M U a
O M U a
R I N T
R I N T
R I N T
R I N T
Backplane C S U a
00
Backplane
C S U a
01
Front board
S P U a
02
S P U a
03
S P U a
04
S S P C U U a a
05 06
S C U a
07
D P U b
08
D P U b
D P U b
D P U b
11
G C U a
12
G C U a
13
09 10
Page21
EPS
14 15 16 17 18 19 20 21 22 23 24 25 26 27
Rear board
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
Backplane
Backplane S P U a
00
Front board
S P U a
01
S P U a
02
S P U a
03
S P U a
04
S S P C U U a a
05 06
S C U a
07
D P U b
08
D P U b
D P U b
D P U b
11
D P U b
12
D P U b
13
09 10
Page22
Page23
SPM in MPS
14 15 16 17 18 19 20 21 22 23 24 25 26 27
Rear board
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
O M U a
O M U a
R I N T
R I N T
R I N T
R I N T
Backplane C S U a
00
Backplane
C S U a
01
Front board
S P U a
02
S P U a
03
S P U a
04
S S P C U U a a
05 06
S C U a
07
D P U b
08
D P U b
D P U b
D P U b
11
G C U a
12
G C U a
13
09 10
Page24
SPM in EPS
14 15 16 17 18 19 20 21 22 23 24 25 26 27
Rear board
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
Backplane
Backplane S P U a
00
Front board
S P U a
01
S P U a
02
S P U a
03
S P U a
04
S S P C U U a a
05 06
S C U a
07
D P U b
08
D P U b
D P U b
D P U b
11
D P U b
12
D P U b
13
09 10
Page25
SPUa Board
XPUa
Component
RUN ALM ACT
Four independent subsystems Motherboard-subboard structure
Two sub-boards Each has two CPU subsystems
LINK ACT
Function
0 1 2 3
10/100/1000BASE-T
Processing signaling and algorithm Iub/Iur/Iu interface signaling processing Wireless and transport resource
management
PARC
Page26
DPUb Board
DPUa
Component
RUN ALM ACT
22 DSPs in one board
Function
Processing data of wireless frame protocol
PARC
Page27
Clock Synchronization Subsystem
MPS
14 15 16 17 18 19 20 21 22 23 24 25 26 27
Rear board
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
O M U a
O M U a
R I N T
R I N T
R I N T
R I N T
Backplane C S U a
00
Backplane
C S U a
01
Front board
S P U a
02
S P U a
03
S P U a
04
S S P C U U a a
05 06
S C U a
07
D P U b
08
D P U b
D P U b
D P U b
11
G C U a
12
G C U a
13
09 10
Page28
Page29
Optional
CN
BITS RSS
GPS
To NodeB
R I N T
R I N T
GCUa/GCGa Clock module
8kHz
S C U a
19.44MHz, 32.768MHz, 8KHz RBS 8kHz RBS
To NodeB
R I N T
S C U a
S C U a
R I N T
To NodeB
19.44MHz, 32.768MHz, 8KHz High-speed backplane channel
19.44MHz, 32.768MHz, 8KHz Clock cable
Page30
GCUa: General Clock Unit GCGa: General Clock with GPS Card Function
Generating system timing signal Generating RFN signal
Page31
GCUa/GCGa Board
Port name Function Port type ATN-IN Port for the GPS antenna SMA female CLKOUT 0~9 COM0 COM1 TESTOUT Output 8 kHz timing signals and 1PPS timing signals Reserved Port for 422-level 8kHz timing signals Testing timing signal output RJ45 RJ45 SMB male RJ45
TESTIN
Testing timing signal input of 2 MHz signals
SMB male
CLKIN0
Inputting BITS timing and line timing signals
SMB male
Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved. Page32 CLKIN1 Inputting BITS timing and line timing
SMB male
Transport Subsystem
RINT in MPS
14 15 16 17 18 19 20 21 22 23 24 25 26 27
Rear board
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
O M U a
O M U a
R I N T
R I N T
R I N T
R I N T
Backplane C S U a
00
Backplane
C S U a
01
Front board
S P U a
02
S P U a
03
S P U a
04
S S P C U U a a
05 06
S C U a
07
D P U b
08
D P U b
D P U b
D P U b
11
G C U a
12
G C U a
13
09 10
Page33
Transport Subsystem
RINT in EPS
14 15 16 17 18 19 20 21 22 23 24 25 26 27
Rear board
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
Backplane
Backplane S P U a
00
Front board
S P U a
01
S P U a
02
S P U a
03
S P U a
04
S S P C U U a a
05 06
S C U a
07
D P U b
08
D P U b
D P U b
D P U b
11
D P U b
12
D P U b
13
09 10
Page34
Transport Subsystem
RINT: RNC Interface Board

Interface Iub/IuCs/Iur Iub/IuCs/Iur Iub/IuCs/Iur, IuPs
RINT AEUa 32 channels ATM over E1/T1/J1 interface AOUa Two optical ports for ATM over channelized STM-1 UOIa Four unchannelized STM-1 optical ports
PEUa 32 channels of IP over PPP/MLPPP over E1/T1 FG2a Eight FE ports or two GE electrical ports
Iub/IuCs/Iur Iub/IuCs/Iur, IuPs
GOUa Two GE optical ports
Iub/IuCs/Iur, IuPs
Page35
AEUa Board
Function
Providing 32 channels of ATM over E1/T1/J1 for Iub, Iur and Iu-CS
Supporting IMA, UNI, Fractional ATM, fractional IMA Supporting Timeslot cross-connection Supporting AAL2 switching Supporting Intra-board ATM switching
Extracting line clock and outputting synchronization signals to GCUa
Outputting synchronization signals to the NodeB
Page36
AOUa Board
Function
Providing two optical ports for ATM over channlized STM-1
Supporting Iu-CS, Iur, and Iub interface Supporting IMA and UNI Supporting AAL2 switching Supporting Intra-board ATM switching
Page37
UOIa Board
Function
Providing 4 unchannelized STM-1 optical ports
Supporting ATM over SDH Supporting Iu-CS, Iu-PS, Iur, and Iub
Extracting line clock and outputting synchronization signals to GCUa Outputting synchronization signals to the NodeB
Page38
PEUa Board
Function
Providing 32 channels of IP over PPP/MLPPP over E1/T1/J1
Supporting Iu-CS, Iur, and Iub Providing the fractional IP function Supporting timeslot cross-connection
Page39
FG2a Board
Function
Providing 8 FE or 2 GE electrical ports
Providing IP over FE or GE Supporting Iu-CS, Iu-PS, Iur, and Iub
Page40
GOUa Board
Function
Providing two GE optical ports
Providing IP over GE Supporting Iu-CS, Iu-PS, Iur, and Iub
Page41
OM Subsystem
MPS
14 15 16 17 18 19 20 21 22 23 24 25 26 27
Rear board
R I N T
R I N T
R I N T
R I N T
R I N T
R I N T
O M U a
O M U a
R I N T
R I N T
R I N T
R I N T
Backplane C S U a
00
Backplane
C S U a
01
Front board
S P U a
02
S P U a
03
S P U a
04
S S P C U U a a
05 06
S C U a
07
D P U b
08
D P U b
D P U b
D P U b
11
G C U a
12
G C U a
13
09 10
Page42
OM Subsystem
S C U a
Internal network External network To M2000
S C U a S C U a
RBS
O M U a
HUB
O M U a
S C U a
RSS
Ethernet cable Serial cable Alarm box LMT
Page43
OM Subsystem

OMUa: Operation and Maintenance Unit Supporting two CPU, 2G memory Supporting three ETH port (10/100/1000M Base-T self-adaptation) Four USB(USB2.0) ports Installed only in slots 20 and 21, or slots 22 and 23 in RSS
Page44
OMUa Board
1 Captive screw 3 Ejector lever 5 LED (ALM) 7 Button (RESET) 9 USB port 11 Ethernet port (ETH1) 13 COM port 15 LED (HD) 17 Hard disk 2 Shielding finger 4 LED (RUN) 6 LED (ACT) 8 Button (SHUTDOWN) 10 Ethernet port (ETH0) 12 Ethernet port (ETH2) 14 VGA port 16 LED (OFFLINE) 18 Screw for fixing the hard disk
Page45
Contents
Page46
BSC6900 Cable Distribution Figure
Page47
Main Cables
Trunk Cables
75 coaxial cable and Y-shaped 75-ohm coaxial cable 120 twisted pair cable and Y-shaped 120-ohm twisted pair cable
Network Cables
Straight through network cable
used to connect the OMUa board to other devices
Crossover network cable
used to connect the SCU board
Optical Fibers
LC/PC-SC/PC single-mode optical cable LC/PC-FC/PC single-mode optical cable
Page48
Y-Shaped E1/T1 cable
E1/T1 cable is used to connect E1/T1/J1 port The Y-shaped 75-ohm coaxial cable/ 120-ohm coaxial cable
Two DB44 connectors at one end Each connector with a structure of 2 x 8 cores The 16 micro coaxial cables form eight E1 RX/TX links
Page49
Y-shaped RNC Clock Signal Cable

(1) (2) (1) (1)
One RJ45 connector end
Connected to the port CLKIN on SCUa
Two RJ45 connectors end
Connected to ports CLKOUT on 2 GCUa in the RSS subrack
Page50
Optical Cables
LC/PC-SC/PC single-mode optical cable LC/PC-FC/PC single-mode optical cable It is used to connect the other NEs
Page51
Network Cable
Crossover network cable
Connecting the SCU boards Connecting the OMUa board with other devices
Straight-through network cable
Page52
Monitoring Signal Cable of RNC Power Distribution Box
X1: DB9 connector
X2: DB15 connector
SHELL: Metal case
A DB9 connector at one end A DB15 connector at the other end
Page53
RNC Alarm Box Signal Cable
X1: RJ45 connector
X2: DB9 connector
Used to transmit alarm information to the alarm box For display audible and visible warning
Page54
Contents
Page55
BSC6900 Signal Flows
Control plane message flows
Uu interface message flow Iub/Iur/Iu interfaces message flows
User plane data flows
CS data flow PS data flow MBMS Service data flow
Page56
Control Plane Message Flow

Uu Interface Message Flow
Intra-RNC Control Message Flow on Uu Interface
RSS
UE
NODEB
R I N T
D P U b
SPM
S P U a
S P U a
SPM RNC
D P U b
R I N T
UE
NODEB
Page57
Uu Interface Message Flow
Inter-RNC Control Message Flow on Uu Interface
R I N T
UE NODEB
D P U b
S P U a
SPM
R I N T
R I N T
D P U b
SPM SRNC
S P U a
DRNC
Page58
Iub Interface Message Flow

RSS
UE
NODEB
R I N T
D P U b
S P U a
S P U a
D P U b
R I N T
UE
NODEB
SPM RNC
SPM
Page59
Iu/Iur Interface Message Flow

RSS
R I N T
D P U b
S P U a
S P U a
SPM RNC
D P U b
R I N T
MSC/SGSN/other RNC
SPM
Page60
User Plane Data Flow
Data Flow Between Iub and Iu-CS/Iu-PS
Intra-RNC Data Flow

RSS
R I N T
UE NODEB
D P U b
S P U a
R I N T
S P U a
SPM
D P U b
R I N T
NODEB UE
SPM RNC
MSC/SGSN
Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved. Page61
Data Flow Between Iub and Iu-CS/Iu-PS
Inter-RNC Data Flow
R I N T
UE NODEB
D P U a
S P U b
R I N T
R I N T
D P U b
SPM SRNC
S P U a
R I N T
SPM DRNC
MSC/SGSN
Page62
MBMS Service Data Flow

RSS
CSUa
R I N T
UE NODEB
D P U b
SPM
S P U a
R I N T
SGSN RNC
Page63
Thank you
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BSC6900 Hardware System Structure

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

RNC in WCDMA System

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

HW68 R11 Board

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

HW69 R11 Board

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Power consumption RSR: 4,650W RBR: 4,660 W

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

12 U shielding subrack of Huawei 28 slots with backplane is positioned in the middle

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

RNC Logical Structure

service service service processing processing processing subsystem subsystem subsystem

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Providing internal Medium Access Control (MAC) switching

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

RUN ALM ACT RESET

10/100/1000BASE-T For inter-subrack connection

Serial port for commissioning

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Test the timing signal output

Service Processing Subsystem

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Service Processing Subsystem

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Service Processing Subsystem

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Service Processing Subsystem

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Service Processing Subsystem

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

RUN ALM ACT

Four independent subsystems Motherboard-subboard structure

Two sub-boards Each has two CPU subsystems

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

RUN ALM ACT

22 DSPs in one board

Processing data of wireless frame protocol

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Clock Synchronization Subsystem

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Clock Synchronization Subsystem

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Clock Synchronization Subsystem

GCUa/GCGa Clock module

19.44MHz, 32.768MHz, 8KHz RBS 8kHz RBS

19.44MHz, 32.768MHz, 8KHz High-speed backplane channel

19.44MHz, 32.768MHz, 8KHz Clock cable

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Clock Synchronization Subsystem

Generating system timing signal Generating RFN signal

Copyright 2007 Huawei Technologies Co., Ltd. All rights reserved.

Testing timing signal input of 2 MHz signals