Faculty of Electric and Electronic Engineering

Electronic Engineering Laboratory IV BEE31101 Instruction Sheet

Lab 4 CPU Instructions

Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 4 : CPU Instructions

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Table of Content
Table of Content Outcomes Instructions Pre-Lab Lab Activities Overview Assignment1 Assignment2 Observations Questions References ii 1 1 2 3 3 4 6 8 10 11

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 4 : CPU Instructions

Outcomes
After completing this module, student should be able to: 1. Create and apply an appropriate basic CPU instruction on CPU simulator. (C3, PS) 2. Organize time management in group effectively according task given. (P5, TS) 3. Adapt the current technology in microcontroller with morale and etiquette. (A4, ET)

Instructions
1. Grouping: Lab group is not predetermine and consists with at most two team members.

2. Pre-Lab: Must be submitted to the instructor at the beginning of lab sessions. Verified by the instructor and returned to the students at the end of lab session. The verified pre-lab will be attached with the final report for submission. 3. Lab Activities: All lab activities such as sample code, examples and lab assignments must be held in the respective lab location and completed within the given times. 4. Demonstration: Student must demonstrate the successful sample code, examples and lab assignments to the respective instructor. Verification only will be given upon completion of all lab activities and initialized by the instructor on the cover page. 5. Report Organization: Report must be organized according to given report template. 6. Report Submission: Report must be received by respective technical staff (at respective lab) before 4.00pm; not later than three (3) days upon completion of lab session.

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 4 : CPU Instructions

Pre-Lab

1. Explain the functions of special CPU registers such as the PC, SR and SP register. (3 marks)

2. How program stack are working? What kinds of CPU instruction are used to store values on top stack? (2 marks)

(Total 5 marks) Checked by: Date:

Signature & Lab. Stamp

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 4 : CPU Instructions

Lab Activities
Overview
The programming model of computer architecture defines those low-level architectural components, which include the following CPU instruction set CPU registers Different ways of addressing instructions and data in instructions

It also defines interaction between the above components. It is this low-level programming model which makes programmed computations possible.

Next is some basic information on the simulator, which should enable the students to use the simulator. The simulator for this lab is an application running on a PC running MS Windows operating systems.

The main window is composed of several views, which represent different functional parts of the simulated processor. These are shown in Figure 1 and are composed of CPU Instruction Memory Special CPU Registers CPU (General Purpose) Registers Program Stack Program Creation and Running Features

Figure 1: Main Window FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 4 : CPU Instructions

Assignment1
First, we need to place some instructions in the Instruction Memory View, representing the RAM in the real machine, before executing any instructions. 1. In the Program tab, first enter a Program Name, and then enter a Base Address (this can be any number, but for this exercise use 100). 2. Click on the ADD button. A new program name will be entered in the Program List view.

Now, we are ready to enter instructions into CPU simulator. We do this by clicking on the ADD NEW button in the Instructions tab. This will display the Instruction: CPU0 window. We use this window to select and enter the CPU instructions. Appendix lists some of the instructions this simulator uses and also gives examples of their usage.

3. Create an instruction, which moves number 5 to register R00. Execute the above instruction (to do this simply double click on it in the Instruction Memory View). Observe the result in the CPU Registers View. 4. Create an instruction, which moves number 8 to register R01. Execute it (double click on the instruction). Observe the contents of R00 and R01. 5. Create an instruction, which adds the contents of R00 and R01. Execute it, and observe which register the result is put in. 6. Create an instruction, which pushes the above result to the top of the hardware stack, and then execute it. 7. Create an instruction to push number -2 on top of the stack and execute it. Observe the value in Program Stack. 8. Observe the value in the SP register (Special CPU Register view). Whenever we push a value on Program Stack, the SP register is updated. 9. Create an instruction to compare the values in registers R00 and R01. Execute it, and observe the value in SR (Special CPU Registers view). 10. Observe the status of the OV/Z/N parts of the status register. Which boxes are checked and which are not? What do they indicate? 11. Create an instruction to unconditionally jump to the first instruction. Execute it, and observe the value in the PC register. This is the address of the next instruction to be executed. Make a note of which instruction it is pointing to? 12. Observe the values in the PAdd and LAdd columns. What do these values indicate? Are they different (Hint: Check out Base Address value)? 13. Create an instruction to pop the value on top of the Program Stack into register R02. Execute it, and observe the value in the SP register. FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 4 : CPU Instructions

14. Create an instruction to pop the value on top of the Program Stack into register R03. Execute it, and observe the value in the SP register. 15. Execute the last instruction again. What happened? Explain. 16. Create a compare instruction, which compares values in registers R04 and R05. 17. Manually insert two equal values in registers R04 and R05. Execute the compare instruction. Which of the status flags OV/Z/N is set? Why? 18. Manually insert a value in register R05 greater than that in register R04. Execute the compare instruction. Which of the status flags OV/Z/N is set? Why? 19. Manually insert a value in register R04 greater than that in register R05. Execute the compare instruction. Which of the status flags OV/Z/N is set? Why? 20. Create an instruction, which will jump to the first instruction if the values in register R04 and R05 are equal. Test this instruction by manually putting equal values in register R04 and R05, then first executing the compare instruction followed by executing the jump instruction. 21. Save the instructions in the Instruction Memory View in a file by clicking on the SAVE button.

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 4 : CPU Instructions

Assignment2
Investigate and Explore In this assignment, student will be familiar with direct and indirect addressing modes of accessing data in memory. Student also learns about subroutine, call and return from subroutine, to create an iterative loop of instruction. First, you need to place some instruction in the Instruction Memory View, representing the RAM in the real machine, before executing any instructions. 1. In the Appendix at the end of this document, locate the instruction, which is used to store one byte of data in a memory location. Use it to store number 65 in address location 20 using direct addressing mode (all numbers are in decimal). 2. Create an instruction to move decimal number 22 to register. Execute this instruction and verify the result in R01 3. Create an instruction to store decimal number 51 in memory location the address of which currently stored in register R01. This is example of indirect addressing. Note the use of @ prefix next to R01 in this case. 4. Observe on data memory locations 20 and 22. 5. Now, create a loop. First, enter the following code. The # prefix is used to denote a literal value thus distinguishing it from an address value which does not use it. R01 represents an arbitrary register; we can use any of the registers from R00 to R31. MOV L0: ADD CMP JNE HLT #0, R01 #1, R01 #5, R01 $L0

Example Code 1

6. As we can see, the label L0 represents the address of the instruction immediately below it, i.e. the ADD instruction. The JNE instruction can use L0 as the address to jump to. As the label L0 can represent any address this code should work anywhere in memory making it very flexible. The $ sign indicates that L0 is a label. 7. Run Code 1 program. First, click on the RESET PROGRAM button in the CPU Simulator window. Highlight the first instruction of the program. Adjust the speed slider to a value 80. Click on the RUN button. After a short while the program should stop. If it appears to run too long, then click on the STOP button and check your code. Correct it if necessary and repeat instruction once again.

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 4 : CPU Instructions

8. Modify the Example Code 1 so that the program loop is repeated as long as the value of R01 is less than or equal to 3, and test it.

Next, modified Example Code 1 by adding a subroutine code to simply display the text string at data memory location 24 repeatedly in a loop. A subroutine is no use by itself, must call it using MSF followed by CAL. The MSF (Mark Stack Frame) is needed to reserve a place for the return address on the program stack.

9. Modify your code to look like the one below and run it observing the displays on the console. The code will do the loop 5 times and this number is fixed. For flexibility we can pass the number of loops as a parameter to the subroutine.

MSF PSH CAL HLT L2: POP MOV L0: ADD MSF CAL CMP JNE RET L1: OUT RET

#8 $L2

R02 #0, R01 #1, R01 $L1 R02, R01 $L0

24, 0

Example Code 2 10. Click on the INPUT OUTPUT button which will display the simulated console window. 11. Draw a flowchart for Example Code 2.

Total: 40 marks FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 4 : CPU Instructions

Observations
Assignment1 Step 3 4 5 7 8 9 Instruction Register Content [before | after] R00 R00 R01 R00 R01 Program Stack SP R00 R01 SP 10 11 12 13 14 15 16 17 R04 R05 OV/Z/N OV/Z/N PC PAdd Ladd SP SP

18

OV/Z/N

19

OV/Z/N

20

R04 R05

(10 marks) FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 4 : CPU Instructions

Assignment 2 Step 1 2 3 4 Instruction MEM[20] R01 R01 MEM[20] MEM[22] (5 marks) Register Content

Total: 15 Marks

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 4 : CPU Instructions

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Questions
1. Each CPU instruction is associated with two addresses: the PAdd and the LAdd. Briefly explain the different between PAdd and LAdd. (4 marks) 2. What is the different between the LAdd value of the first instruction and the LAdd value of the second instruction? What does this value indicate? (4 marks)

3. Examine the Example Code 2 and briefly explain how the parameter passing works. (7 marks)

Total: 15 marks

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 4 : CPU Instructions

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References
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Nraig Manjikian (2012) Computer Organization and Embedded Systems, 6th Edition. The McGraw-Hill Companies. 2. W. Stallings (2010), Computer Organization & Architecture: Designing for Performance, 8th Edition, Pearson Prentice Hall.

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 4 : CPU Instructions

Appendix Simulator Instruction Sub-set Instruction Description

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Data Transfer Instruction Move data to register; move register to register e.g. MOV MOV #2, R01 moves number 2 into register R01 MOV R01, R03 moves contents of register R01 into register R03 LDB LDW STB STW Load a byte from memory to register Load a word (2 byte) from memory to register Store a byte from register to memory Store a word (2 byte) from register to memory Push data to top of hardware stack (TOS); push register to TOS e.g. PSH PSH #6 pushes number 6 on top of the stack PSH R03 pushes the contents of register R03 on top of the stack Pop data from top of hardware stack to register. e.g. POP POP R05 pops contents of top of stack into register R05 Note: if you try to POP from an empty stack you will get the error message Stack underflow Arithmetic Instruction Add number to register; add register to register e.g. ADD ADD #3, R02 adds number 3 to contents of register R02 and stores the result in register R02 ADD R00, R01 adds contents of register R00 to contents of register R01 and stores the result in register R01 FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 4 : CPU Instructions

SUB MUL Subtract number from register; subtract register from register

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Multiply number with register; multiply register with register

DIV

Divide number with register; divide register with register

Control Transfer Instructions Jump to instruction address unconditionally JMP e.g. JMP 100 unconditionally jumps to address location 100

JLT

Jump to instruction address if less than (after last comparison)

JGT

Jump to instruction address if greater than (after last comparison)

Jump to instruction address if equal (after last comparison instruction) e.g. JEQ JEQ 200 jumps to address location 200 if the previous comparison instruction result indicates that two numbers are equal, i.e. the Z status flag is set(the Z box will be checked in this case)

JNE

Jump to instruction address if not equal (after last comparison)

Mark Stack Frame instruction is used in conjunction with the CAL instruction. MSF e.g. MSF reserve a space for the return address on program stack CAL 1456 save the return address in the reserved space and jump to subroutine in address location 1456

CAL

Jump to subroutine address

RET SWI

Return from subroutine

Software Interrupt (used to request OS help) FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 4 : CPU Instructions

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HLT Comparison Instruction

Halt simulation

Compare number with register; compare register with register e.g. CMP #5, R02 compare number 5 with the contents of register R02

CMP R01, R03 compare the contents of register R01 and R03 CMP Note: If R01 = R03 then the status flag Z will be set, i.e. the Z box is checked If R03 > R01 then none of the status flags will be set, i.e. none of the status flag boxes are checked IF R01 > R03 then the status flag N will be set, i.e. the N status box is checked Input, Output Instruction IN Get input data (if available) from an external IO device

OUT

Output data to an external IO device

FKEE, Sem02 Session 2012/13