Subject: Advanced Computer Architecture

1) Consider the following pipeline reservation table. 1 X X X S2 S3 (a) (b) (c) (d) (e) What are the forbidden latencies? Draw the state transition diagram. List all the simple cycles and greedy cycles. Determine the optimal constant latency cycle and the minimal average latency. Let the pipeline clock period be = 20 ns. Determine the throughput of the pipeline. (10 Marks) Sol: Forbidden latencies: 2, 4, 5 and 7 Permissible latencies: 1, 3, 6 and 8 Collision vector: C7C6C5C4C3C2C1 = 1011010 CASE 1: latency 3 Present state Collision vector PS with 3 shifts Next state Present state Collision vector PS with 3 shifts Next state CASE 2: latency 6 Present state Collision vector 1011010 1011010 + 0001101 1011011 1011011 1011010 + 0001011 1011011 Present state Collision vector PS with 8 shifts Next state 1011011 1011010 + 0000000 1011010 X X X 2 3 4 5 X 6 7 X 8 S1

1011010 1011010

PS with 6 shifts Next state Present state Collision vector PS with 6 shifts Next state

+ 0000001 1011011 1011011 1011010 + 0000001 1011011 Present state Collision vector PS with 8 shifts Next state 1011011 1011010 + 0000000 1011010

CASE 3: latency 1 Present state 1011010 Collision vector 1011010 PS with 1 shifts + 0101101 Next state 1111111 CASE 4: latency 8 Present state 1111111 Collision vector 1011010 PS with 8 shifts + 0000000 Next state 1011010 Present state Collision vector PS with 8 shifts Next state 1011010 1011010 + 0000000 1011010

8+

1011010
3 6 8+ 1* 8+

1011011
3* 6

1111111

Latency cycles: (1, 8) (1, 8, 8) (1, 8, 3, 8) (1, 8, 8, 3, 8) (1, 8, 6, 8) (1, 8, 8, 6, 8) (8) (3) (6) (1, 8, 8, 6, 6, 8) Simple cycles: (3) (6) (8) (1, 8) (3, 8) (6, 8) Greedy cycles: (3) (1, 8) Optimal latency cycle: (3) MAL: Lower bound = 3 Upper bound = 4+1 = 5

Average greedy cycle latency = (1+8) / 2 = 4.5 MAL 4.5 MAL = (3)

2) Consider the five-stage pipelined processor specified by the following reservation table 1 X X X X X S2 S3 S4 S5 (a) (b) (c) (d) Sol: What are the forbidden latencies? Draw the state transition diagram. List all the simple cycles and greedy cycles. Determine the optimal constant latency cycle and the minimal average latency (MAL). (10 Marks) Forbidden latencies: 3, 4 and 5 Permissible latencies: 1, 2 and 6 Collision vector: C5C4C3C2C1 = 11100 CASE 1: latency 1 Present state Collision vector PS with 1 shifts Next state Present state Collision vector PS with 1 shifts Next state 11100 11100 + 01110 11110 11110 11100 + 01111 11111 Present state Collision vector PS with 6 shifts Next state 11110 11100 + 00000 11100 X X 2 3 4 5 X 6 S1

Present state Collision vector PS with 6 shifts Next state

11111 11100 + 00000 11100

CASE 2: latency 2 Present state Collision vector PS with 2 shifts Next state Present state Collision vector PS with 2 shifts Next state CASE 3: latency 6 Present state Collision vector PS with 6 shifts Next state 11100 11100 + 00000 11100 11100 11100 + 00111 11111 11111 11100 + 00111 11111 Present state Collision vector PS with 6 shifts Next state 11111 11100 + 00000 11100

6+

11100
1* 6+ 2* 6+

11110

1111
Latency cycles: (2),(6),(2,6),(1,6),(1,1,6) Simple cycles: (2),(6),(2,6),(1,6),(1,1,6) Greedy cycles: (2) (1, 6) Optimal latency cycle: (2) MAL: Lower bound = 2 Upper bound = 3+1 = 4 Average greedy cycle latency = (1+6) / 2 = 3.5 MAL = 2 3) Consider the following pipelined processor with four stages. This pipeline has a total evaluation time of six clock cycles. All successor stages must be used after each clock cycle. Output Input
S1 S2 S3 S4

(a) (b) (c) (d) (e) Sol:

Specify the reservation table for this pipeline with six columns and four rows. List the set of forbidden latencies between task initiations. Draw the state diagram which shows all possible latency cycles List all greedy cycles from the state diagram What is the value of minimal average latency (MAL)? (10 Marks) Reservation table: 1 X X X X X X 2 3 4 X X 5 6 S1

S2 S3 S4 Forbidden latencies: 2 and 4 Permissible latencies: 1, 3 and 5 Collision vector: C4C3C2C1 = 1010

CASE 1: latency 1 Present state Collision vector PS with 1 shifts Next state Present state Collision vector PS with 1 shifts Next state CASE 2: latency 3 Present state Collision vector PS with 3 shifts Next state Present state Collision vector PS with 3 shifts Next state CASE 3: latency 5 Present state Collision vector PS with 5 shifts Next state 1010 1010 + 0000 1010 1010 1010 + 0001 1011 1011 1010 + 0001 1011 Present state Collision vector PS with 5 shifts Next state 1011 1010 + 0000 1010 1010 1010 + 0101 1111 1111 1010 + 0111 1111 Present state Collision vector PS with 5 shifts Next state 1111 1010 + 0000 1010

5+

1010
1* 5+ 3 5+

1111

1011
3*

Simple cycles: (3),(5),(3,5),(1,5) Greedy cycles: (3) (1,5) Average greedy cycle latency = (1+5) / 2 = 3 MAL: Lower bound = 3 Upper bound = 2+1 = 3 MAL = 3