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# Mentor Graphics Tutorial: from VHDL to Silicon layout design flow

Lab1: Logic Simulation, Synthesis and Timing Simulation - by Basawaraj - Modified Jan 2009 - Originally by: Y.Guo INTRODUCTION: In contemporary ASIC design approach, design for testability (DFT) is usually achieved via synthesis. When your design is presented with VHDL, the DFT structures, such as BIST, Boundary Scan, and internal scan circuitary, can be automatically inserted into it before it is synthesized. However, the inserted DFT circuitary will change the timing performance of the design, so timing simulation results should be the guideline for DFT design. Here, we will first briefly introduce the logic synthesis and timing simulation procedures which will be used in the next two lab exercises. In this tutorial we will design an 8-bit adder described in Figure 1. It is assumed that you know a little of VHDL. We will begin with the VHDL source files of this design (so don't worry about writing VHDL codes, if you don't know VHDL). In this lab exercise, the design will be compiled and simulated on the RTL level, synthesized into gate level circuit with ADK 0.5 standard cell library, and analyzed in timing mode.

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity ADDER is generic (N : in integer := 8); port ( A, B : in std_logic_vector(N-1 downto 0); CI : in std_logic; S : out std_logic_vector(N-1 downto 0); COUT : out std_logic); end ADDER; architecture RTL of ADDER is signal RESULT : std_logic_vector(A'length downto 0); begin RESULT <= ('0' & A) + ('0' & B) + CI; S <= RESULT(A'length-1 downto 0); COUT <= RESULT(A'length); end RTL; Figure 1. VHDL code for an 8-bit adder. The first step is to simulate the design and synthesize the design into RTL level using Leonardo Spectrum synthesizer.

## Simulate VHDL model using ModelSim

The VHDL model should be functionally simulated to ensure correct operation before it is synthesized. Then create a directory (e.g. \$HOME/mgc/class/ee617/lab2/myadder) and copy the VHDL code in figure 1 and save it as adder.vhd in your created directory above. Then enter into your work directory where you saved your vhdl file.

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## Mentor Graphics Tutorial: from VHDL to Silicon layout design flow

First, compile the VHDL file: >>vlib work >>vmap work ./work >>vcom adder.vhd Then, invoke the ModelSim simulator on the design: >>vsim adder You should see a display like the one below:

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## Mentor Graphics Tutorial: from VHDL to Silicon layout design flow

Use the View->Objects... menu item to bring up the Objects (signals) (if not displayed by default) display. Use the View->Wave menu to create a Wave window. Then, select all signals in the objects window and drag them to the wave window. Finally, force values on each of the input signals using the Force... command in the main window or select the input signal, right click and select Force; and run the simulation using the Run->100ns menu item in the main window. For the command reference, for instance, you want to know how to use force, type help force in the main command window. The resulting Wave window should look like this:

Exit the ModelSim simulator using the File->Quit menu item in the main window.

## Synthesizing VHDL using Leonardo Spectrum

Step 1. Create directories and invoke leonardo Navigate to your myadder file where you have put the adder.vhd and make a directory netlist under myadder, like below: \$ cd myadder \$ mkdir netlist (This is the directory where the edif netlist will be saved) Then, start leonardo. \$ leonardo & A pop-up window appears with LeonardoSpectrum Level 3 selected. Hit Ok button and the following window appears (Figure 2). If not like this, click FlowTaps under the tool menu. This allows you to customize the setup of your design, and perform each function separately.

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## Mentor Graphics Tutorial: from VHDL to Silicon layout design flow

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## Mentor Graphics Tutorial: from VHDL to Silicon layout design flow

source setc.tcl Step 4. Read the VHDL file(s) Now click on the "Input" tab. Click the Set Working Directory Button, Set your working directory (to myadder directory). This is the directory where the generated files will be stored. Open the file adder.vhd. Click on "Read". Ensure, resource sharing, run elaborate and run pre-optimization are ticked. Now if you choose Tools, then View RTL Schematic, you can see the RTL level synthesis results. See if the schematic matches the VHDL description. Close the schematic window before you proceed to the next step. Step 5. Optimize design Here leonardo will map the registers to technology cells, implement operators into optimal configurations, and minimize the remaining boolean logic. Click on the "Optimize" tab, make sure "Add I/O Pads" is NOT selected. Now click on "Optimize". Now if you choose Tools, then View Gate Level Schematic, you can see the technology dependent gate level synthesis results. See if the schematic matches the VHDL description. Close the schematic window before you proceed to the next step. Step 6. Generate reports for area and delay You can generate reports regarding the gate count (area) and critical path (delay). Click on "Report" tab, and then click on the "Report Area" button. Save area report in a file (e.g., area-report.txt). Now if you click on the "Report Delay" tab on the bottom left of the screen, and then click on "Report Delay" tab, you can get an estimate of the delay through various critical paths. You can also see the critical path(s) in the schematic if you select Bring Up Schematic Viewer. Step 7. Save the design Now click on the "Output" tab. Choose the output format to "Verilog" first, and then save the output EDIF file (adder.v) in the netlist directory. (Alternatively you can enter the command in the command line: auto_write format Verilog [output_file] You have now created an industry standard netlist file for use in other EDA programs. Exit Leonardo.

Creating Mentor Graphics schematics from netlist file and checking new schematics

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## Mentor Graphics Tutorial: from VHDL to Silicon layout design flow

After source .cshrc , change the working directory to /home/<your name>/mgc/class and run the command % source /home/mgmgr/mg2008/setup Now type da_ic to invoke the Design Architect. Choose File -> Import Verilog. Use the following settings: Set your netlist file to the generated verilog netlist (adder.v); Set the output directory where you want to save your schematic; Set the mapping file to : \$ADK/technology/adk_map.vmp After you click OK, You will have an EDDM schematic which can be used with IC Station or Eldo.

In the Design Architect window, you can open your generated schematic ADDER8. What you see is a schematic consisting of components of the standard gate library (Figure 3).

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