Mos Logic

MOS Logic and Gate Circuits
A B
A
A Y
AB
Wired OR
Contents
` `
` ` ` ` ` ` `
Introduction NMOS Logic

Resistive Load Saturated Enhancement Load Linear Enhancement Load Depletion Load Some Gates Transient in NMOS Circuit Pseudo-NMOS
`
`
CMOS Logic
Static CMOS Logic Gates
NOT NAND NOR Realization of More Complicated Gate Circuits
Transmission Gates Family

NMOS Only Switch CMOS
` `
Differential Cascode Voltage Switch Logic Rules of Thumb
Summary
Introduction
` The MOS inverter is the basic circuit exhibits all of the essential features of MOS Logic. Extension of MOS inverter concepts to NOR and NAND Gate is very simple. In this lecture we will analysis for VTC, NM, PD, . Both NMOS and CMOS circuits are considered. Digital MOS circuits can be classified into two categories:
` Static Circuits: require no clock or other periodic signal for operation. Clocks are required for static circuit in sequential logic ` Dynamic Circuits: require periodic clock signals, synchronized with data signals, for proper operation even in combinational logic
NMOS Logic
` Resistive Load
W L VoL C Speed P RL Area

Vo
Vdd
+ Vdd
RL Vo
Vi
VOL o
Vi
NMOS Logic
` Resistive Load Properties
` ` ` ` ` ` N transistors + Load VOH = Vdd VOL = Vdd ( rN/(rN + RL)) Assymetrical response Static power consumption tPL = 0.69RLCL
NMOS Logic
` Saturated Enhancement Load
Vds2 = Vgs2 Vds2 > Vgs2 VT2 M2 is in saturation

Vo
+ Vdd
+ Vdd
M2
Vo
VOH
Vo = 1 Vi
R
Vi
M1
VOL o
VIL
VIH
Vi
NMOS Logic
` VIL
VIL VT1 M1, M2 are in saturation K1 (Vgs1 VT1 ) 2 = K 2 (Vgs2 VT2 ) 2 , VT 2 Cte Vgs1 = Vi, Vgs2 = Vdd Vo Vo 1 VIL VT1 Vi Vo = R , R > 1 Vi
Vo
VOH
Vo = 1 Vi
R
VOL o
VIL
VIH
Vi
NMOS Logic
` VOL
VOL is difficult to obtain because it is the output voltage when input equal to VOH, the resulting expression is a fourth order polynomial!
Vo
VOH
Vo = 1 Vi
VOL o
VIL
VIH
Vi
NMOS Logic
` VIH
M1 is in triode and M2 in saturation
i Vo = 1 ( rds1 rds2 ) Vi Vi Vo rds1 rds2 rds1 = i1

2 i1 = K1 Vgs1 V Vo Vo 2 ( ) T1 1 i 2 = K 2 (Vgs2 VT2 ) 2 2 i 1 = K1Vo Vi
i1 = K1 ( Vgs1 VT1 Vo ) Vo K1Vo Vo = = 1 Vi K1 (Vgs1 VT1 Vo) Vo = Vi VT1 2 V VT1 Vi = VIH IH = Vo 2
NMOS Logic
` VIH
M1 is in triode and M2 in saturation
i1 = i 2 1 2 2 = K1 V V Vo Vo 2 K (Vdd Vo V ) ( ) T1 T2 IH 2 2 2(Vdd VT 2 ) VIH = + VT1 3R + 1
NMOS Logic
` NM
NML = VIL VOL Some tenth of volt NMH = VOH VIH = Vdd VT2 VIH
` Power
PdisH 0, PdisL = Id Vdd Pdis = 1 2 Id Vdd
NMOS Logic
` Linear Enhancement Load
VGG Vdd + VT2
+ Vdd
VGG
M2 is in triode
M2
Vo
Vi
Linear Enhancement Load
M1
NMOS Logic
` VTC
By this circuit the VOH can be increased (or Vdd can be decreased because Vomax = Vdd )
Vo
Vdd
VOL o
VIL Vdd Vi VT VIH
NMOS Logic
` VIL
M1 is in saturation and M2 in triode
i i Vds2 Vo = 1 rds2 = 1 Vi Vi Vi i1
2 i2 = K 2 Vgs2 V Vds2 Vds2 2 ( ) T 2 i 2 = K 2 ( VGG Vo VT 2 Vds2 ) Vds2
i1 =
1 K1 (Vi VT1 ) 2 2
i1 = K1 ( Vi VT1 ) Vi K1 (Vi VT1 ) Vo = 1 = Vi K 2 (VGG Vo VT 2 Vds2) VIL = f (Vo)
` VIH
M1 and M2 are in triode
rds2 rds1 rds2
NMOS Logic
` Disadvantages:
More chip area is required (since an extra voltage source VGG) Additional interconnection on the chip is needed The required value of R is even larger than a saturated load
+ Vdd
VGG
M2
Vo
Vi
M1
NMOS Logic
` Depletion Load
` Ion implantation processing step is needed to create depletion device, but overcome the disadvantages of the previous circuit
+ Vdd
M2
Vo
Vi
M1
NMOS Logic
` Depletion Load
` VTC
Vi = Low i1 = 0, M1 in cutoff i1 = i 2 = 0 K2 if M2 is in saturation then i 2 = (Vgs2 VT 2 ) 2 , Vgs2 = 0 i 2 > 0 2

` Therefore M2 is in triode
Vo
Vdd
VOL o
VIL Vdd Vi VT VIH
NMOS Logic
` Depletion Load
` VOL, VIL, VIH
K2 2 K1 V V V V 2 = (0 VT 2 ) 2 VOL = ? ( ) T1 OL OL OH 2 K1 (Vgs1 VT1 ) Vo = 1 = 1, i1 = i 2 VIL = ? Vi K 2 (Vgs2 VT 2 Vds2) K2 Vo 2 ( VIH VT1 ) Vds1 Vds12 2 i1 = K1 = i = (0 V ) , = 1 VIH = ? T2 2 2 Vi
NMOS Logic
` Some Gates
` In all previous structures which different only in load, the following Gates can be implemented. Note that the NMOS Gates are not available as separately packaged individual circuits, but they are used extensively in LSI systems
NOR Gates NAND Gates
NMOS Logic
` Some Gates
` NOR Gate
+ Vdd
RL
Y A
A
M2
M1 B
NMOS Logic
` Some Gates
` NAND Gate
+ Vdd
RL
Y A
M2
A B
M1
NMOS Logic
` Some Gates
` In NOR Gate two transistors are paralleled but in NAND Gate two transistors are in series. Because of the need for increased area when adding NAND inputs, NAND logic with more than 2 inputs is not economically be attractive in NMOS. NOR logic is preferable ` In NAND the M2 has body effect ` In NOR we need the less interconnection (this can be shown from layout)
NMOS Logic
` Transient in NMOS Circuits
+ Vdd M2
Cgs2
+ Vdd
Cs sub2
Vo
Cgd1
Vi
CL
M1
Cd sub1
C tot = CL + Ceq d sub1 + Ceq s sub2 + Cgs2 + 2 Cgd1
NMOS Logic
` Super Buffer (1)
` If Fan-out is very large then Ctot will be large. For reduction it and decrease the switching time the Super Buffer circuit is used ` In this circuit if Vi is Low state then V1 will be high very more rapid than Vo. Thus the Gate of M2 is in high state very rapidly. Therefore M2 will be in saturation which result the reduction of switching time (ton)
+ Vdd
M4
V1
+ Vdd
M2
Vo
M1
Vi
M3
Super Buffer (1) Circuit
NMOS Logic
` Super Buffer (2)
` It is non-Inverting ` Describe the operation of this circuit!
+ Vdd
M4 V1
+ Vdd
M2
Vo
M1
M3
Vi
Super Buffer (2) Circuit
NMOS Logic
` Pseudo-NMOS
` What makes a circuit fast?
I = C dV/dt -> tpd (C/I) DV low capacitance high current small swing
` Logical effort is proportional to C/I ` PMOS are the enemy!

High capacitance for a given current
` Can we take the PMOS capacitance off the input? ` Various circuit families try to do this
NMOS Logic
` Pseudo-NMOS
` In the old days, NMOS processes had no PMOS
Instead, use pull-up transistor that is always ON
` In CMOS, use a PMOS that is always ON

Make PMOS about effective strength of pulldown network
NMOS Logic
` Pseudo-NMOS
` Uses a p-type as a resistive pullup, n-type network for pulldowns
+ Vdd
M2
Vo
Vi
M1
NMOS Logic
` Pseudo-NMOS Characteristics
` Compared to CMOS, this family has higher packing density, since for n inputs only n+1 transistors are required ` The main disadvantages with Pseudo-NMOS Gates is the large static power dissipation that occurs whenever a pulldown path is activated ` Has much smaller pullup network than static gate ` Pulldown time is longer because pullup is fighting
+ Vdd
M2
Vo
Vi
M1
NMOS Logic
` Pseudo-NMOS Output Voltages
` Logic 1 output is always at Vdd ` Logic 0 output is above Vss ` VOL = 0.25 (Vdd - Vss) is one plausible choice
+ Vdd
M2 Vo
Vi
M1
NMOS Logic
` Pseudo-NMOS Design Topics
` For logic 0 output, pullup and pulldown form a voltage divider ` Must choose n, p transistor sizes to create effective resistances of the required ratio ` Effective resistance of pulldown network must be computed in worst case series n-types means larger transistors
+ Vdd
M2
Vo
Vi
M1
NMOS Logic
` Pseudo-NMOS Transistor Ratio Calculation
` MOSFET sizing is important ` Need to have reasonable W/L ratios for circuit to work correctly ` VOL>VSS but must be low enough to turn off/on next MOSFET in the chain ` Static current drain when on ` Vout is a function of the number of parallel and series N channels in the pull down network
NMOS Logic
` Pseudo-NMOS Transistor Ratio Calculation
` For single supply
VOH = Vdd, For the worst case one NMOS to be on V K n ( Vdd VTn ) VOL 2 VOL = K n (Vdd VT ) 1 VOL 0 K p << K n
2 OL
+ Vdd
KP ( Vdd VTP = 2 Kp 1 2 Kn
Y A B
C
Assuming that VT = VTn = VTp
NMOS Logic
` Pseudo-NMOS VTC ( W/Ln=1)
3.0
2.5
2.0
W/Lp = 4
Vout [V]
1.5
W/Lp = 2
1.0
0.5
W/Lp = 0.5 W/Lp = 0.25
W/Lp = 1
0.0 0.0
0.5
1.0
1.5
2.0
2.5
Vin [V]
NMOS Logic
` Pseudo-NMOS Gates
` Design for unit current on output ` PMOS fights NMOS
Y inputs f
NMOS Logic
` Pseudo-NMOS Power
` Pseudo-NMOS draws power whenever Y = 0
Called static power P = IVDD A few mA / gate * 1M gates would be a problem This is why NMOS went extinct!
` Use Pseudo-NMOS sparingly for wide NORs ` Turn off PMOS when not in use
en Y A B C
NMOS Logic
` Pseudo-NMOS ( NAND) Layout Example
Out
In1 In2 In3 In4
CMOS Logic
` Static CMOS Logic Family
` All of the circuits described in the previous sections have a large static power dissipation. This disadvantage can be overcome by using Static CMOS Logic Family
CMOS Logic
` NOT
+ Vdd
M2
Vi
Vo
M1
CMOS Logic
` Two inputs NAND
+ Vdd
M3
M4
Y B A
M2
M1
CMOS Logic
` Two inputs NOR
+ Vdd
B Y
CMOS Logic
` NAND is more suitable for CMOS because by suppose the equal W/L for NMOS and PMOS transistors, the PMOS transistor has more resistance respect to NMOS, therefore it is better to design circuit by paralleling the PMOS and cascading the NMOS ` The better Technology for digital circuit is N-Well, because in this Technology the NMOS transistors are made in the Sub. Which result better characteristic for transistor
CMOS Logic
` Realization of More Complicated Gate Circuits ` a) Y = A(B+C) ` It can be implemented in three levels:
Gate Level Transistor Level Layout Level
CMOS Logic
` Realization of More Complicated Gate Circuits ` a) Y = A(B+C)
Gate Level
It consists of 10 transistors, 4 transistors for NOR, 2 for NOT and 4 for NAND
B
C
CMOS Logic
Transistor Level
It need only 6 transistors
+ Vdd
B
A
C Y
A
CMOS Logic
Layout Level
By proper construction of layout, the parasitic capacitors are also reduced and area can be saved
CMOS Logic
` Realization of More Complicated Gate Circuits ` b) XNOR (Y = AB + AB)
Gate Level
16 transistors are needed
CMOS Logic
` Realization of More Complicated Gate Circuits ` b) XNOR (Y = AB + AB)
Transistor Level (1)
How many transistors are A needed?
+ Vdd
A
Y = AB + AB
CMOS Logic
` Realization of More Complicated Gate Circuits ` b) XNOR
Previous circuit can be simplified by eliminating two wiring lines
+ Vdd
A B
B A
Y = AB + AB
CMOS Logic
` Realization of More Complicated Gate Circuits
` b) XNOR
In this circuit we have static power dissipation in the state of (A=0,B=1) or (A=1,B=0)
+ Vdd
M3
Y = AB + AB
M1
M2
CMOS Logic
` Realization of More Complicated Gate Circuits ` b) XNOR
Transistor Level (4) (For less dissipation)
Note to the state of A = B = Vdd
A 0 0 Vdd Vdd
B 0 Vdd 0 Vdd
Y Vdd 0 0
Vdd-Vth
+ Vdd
M3
M4
Y = AB + AB
M1
M2
CMOS Logic
` Realization of More Complicated Gate Circuits ` c) XOR
As Previous the Source and Drain of M3 (or M4) are replaced by each other in different states, for example in state of A=0, B=0 the b connection of M3 is Source
A 0 0 Vdd Vdd
B 0 Vdd 0 Vdd
Y Vth
Vdd-Vth
+ Vdd
M2
a
M3
b a
M4
Y = AB + AB
Vdd 0
M1
A
CMOS Logic
` Realization of More Complicated Gate Circuits ` d) Tri-State Outputs
A floating state at the output is needed
Non-Inverting
En = 1 Y = D En = 0 Y = Hi Z
En
D Y
+ Vdd
Y
En
CMOS Logic
` Realization of More Complicated Gate Circuits ` d) Tri-State Outputs
A floating state at the output is needed
Inverting
En = 1 Y = Hi Z En = 0 Y = D
En
D Y
+ Vdd
En
CMOS Logic
` Realization of More Complicated Gate Circuits ` e) Schmitt Trigger
M3 and M6 have minimum sized geometries With Vin = 0 , the transistors M1 and M2 will be on but conducting negligible Drain current since M4 and M5 are off
+ Vdd
Vx
M1 M3
M2
Vin
Vy
Y
M4
Vy Vx Vdd Vy Vdd M6 on Vz = Vy VTN
Vz
M6 M5
+ Vdd
CMOS Logic
` Realization of More Complicated Gate Circuits ` e) Schmitt Trigger
When Vin rise to VTN, M5 turns on, but M4 is off. M5 and M6 form an NMOS amplifier. Thus as Vin rises, Vz is falling and in the certain voltage M4 turns on. With both M4 and M5 conducting, Vy rapidly goes to zero turning off M6. With Vy=0, M3 turns on, which aids in turning off M2 as Vx goes from Vdd to Vy-VTP As Vin decrease from Vdd to zero the operation is essentially similar. But now M1 turns on, in different voltage and
+ Vdd
Vx Vin
Vy
M1 M3 M2
Y
M4
Vz
M6 M5
+ Vdd
CMOS Logic
` Transmission Gates Family
` ` ` ` ` ` Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates N transistors instead of 2N No static power consumption Ratioless Bidirectional
CMOS Logic
` NMOS Only Switch
Vdd
X
In
Voltage [V]
3.0
In
2.0
Out x
1.0
0.0
0.5
1.5
Time [ns]
CMOS Logic
` NMOS Only Switch
VB does not pull up to 2.5V, but 2.5-VTN Threshold voltage loss causes (M2 may be weakly conducting forming a path from Vdd to GND) NMOS has higher threshold than PMOS (body effect)
CMOS Logic
` NMOS Only Switch
Pass transistor gates should never be cascaded as on the left Logic on the right suffers from static power dissipation and reduced noise margins
CMOS Logic
` NMOS Only Switch
Solution1: Level Restoring Transistor
V dd Vdd Level Restorer B A Mn X M1 Mr M2 Out
CMOS Logic
` NMOS Only Switch
Solution1: Level Restoring Transistor Full swing on x (due to Level Restorer) so no static power consumption by inverter No static backward current path through Level Restorer and PT since Restorer is only active when A is high Restorer adds capacitance, takes away pull down current at X
Advantages

For correct operation Mr must be sized correctly (ratioed)
CMOS Logic
` NMOS Only Switch
Solution2: Multiple VT Transistors
low V T transistors
In2 = 0V A = 2.5V
on
Out
off but leaking

In1 = 2.5V B = 0V
sneak path
CMOS Logic
` NMOS Only Switch
Solution2: Multiple VT Transistors
Technology solution: Use (near) zero VT devices for the NMOS TGs to eliminate most of the threshold drop (body effect still in force preventing full swing to Vdd) Impacts static power consumption due to subthreshold currents flowing through the TGs (even if VGS is below VT)
low V T transistors
In2 = 0V A = 2.5V
on
Out
off but leaking

In1 = 2.5V B = 0V
sneak path
CMOS Logic
` NMOS Only Switch
Disadvantage:
It can be bad because the signal can be degraded We do not allow a few gates in series for one signal (Pure TG logic is not regenerative, the signal gradually degrades after passing through a number of TGs)
Advantage:
Allow us to save transistor or less stage of logic A Z
CMOS Logic
` CMOS Transmission Gates Family
` PMOS
A Y
` CMOS
C
C
Y
CMOS Logic
` There are many symbols for transmission gate
B A Z A
B A Z
B Z OR B'
B' BOOK
B' ME
` Be careful, because it is bi-directional
CMOS Logic
` This circuit performs a function similar to that of the well known diode bridge
C = Vss, C = 0 Both transistor are on A = Y

` The input voltage VA (which must be between Vss and Vdd) is then connected to the output through the parallel on resistance of the channels of the two transistors. As VA approaches Vdd, the N-channel device cuts off but the P-channel device remains non saturated, as VA approaches Vss, the Pchannel device cuts off but the N-channel device remains non saturated. Therefore there is always a non saturated transistor between input and output
C
Y
A
C
CMOS Logic
` For more understanding note to this circuit ` We assume:
Vy(0 ) = 0, C = Vdd, C = 0, VTP < Vdd VTN

VA
Vdd
C
S I P
Vy
A
D
t
IN
C
Y CL
CMOS Logic
0 t t Vy = V N = sat ICL = I N + I P = P sat N = sat rP CL A = P triode
C IP
IN
C
TP
t Vy = V t t Vy = Vdd V
TP
TN
N = off rP CL t Vy = Vdd V t t Vy = Vdd TN P = triode
Y CL
CMOS Logic
` It is normally assumed as a resistor
VA (t) = Vddu(t) t Vy(t) = Vdd 1 exp TG TG = R TG CL R TG = rN rP u(t) A
IP
IN
Y CL
CMOS Logic
` rN and rP are approximately as follow (In saturation region)
2VAN rN 2 N (Vdd VTN ) 2VAP rP P (Vdd VTP ) 2 VA is Early Voltage
R rP rN
R TG = rN rP
VTP
Vdd VTN Vdd
Vy
CMOS Logic
` What to note about TG
The inputs must be able to give high current because they are connected directly to Drain and Source of transistors Since each input is connected to an RC circuit, The delay can be considered directly Limited Fan-in Excessive Fan-out Noise vulnerability (not restoring) Supply voltage offset/bias vulnerability Poor high voltage levels if NMOS-only Body effect
CMOS Logic
` Rules of Thumb
Pass-Logic may consume half the power of static logic. But be careful of VT drop resulting in static leakage Pass-Gate Logic is not appropriate when long interconnects separate logic stages or when circuits have high Fan-out load (use buffering)
CMOS Logic
` AND
CMOS Logic
` OR
Y = A + AB = (A + A)(A + B) = A + B
A B
A
A Y AB
Wired OR
CMOS Logic
` MUX
A S = 1 Y= B S = 0
S
A
S
Y
B
S
CMOS Logic
` MUX
S Vdd S F
F = (In1S + In 2 S)
GND
In1
In2
CMOS Logic
` XOR
B A
Y = AB
CMOS Logic
` XNOR
A B
Y = AB + AB
CMOS Logic
` D Latch
1) Load Q n = D n 2) Hold Q n = Q n-1

LD
LD
LD LD
LD
CMOS Logic
` D Latch
1) Load LD = 1
Q=D
D=Q
2) Hold LD = 0
Q
Q
CMOS Logic
` D Latch (Simpler Realization)
If in Load Mode a level voltage opposite to the output of weak inverter is applied to the input by TG, Q = D and weak inverter is not damaged!
LD
LD
Q
Weak Inverter
CMOS Logic
` Delay in Transmission Gate
In
V1
C C
V2
C
Vi
C
Vi +1
C
Vn 1
C
Vn
In
Req V Req V 1 2
Req V Req V Req V Req V i i +1 n 1 n
m 6444 7444 8
Req
In
C
Req
C
Req
C
Req
C
Req
C
Req
C
CMOS Logic
` Delay Optimization
` Delay of RC chain
t P = 0.69 C R e q k = 0.69C R e q
k =1
n(n + 1) 2
` Delay of Buffered chain

m(m + 1) n n + t P = 0.69 C R e q 1 m t buf m 2 n(m + 1) n = 0.69 C R e q + 1 t buf 2 m m opt = 1.7 t Pbuf C Req
CMOS Logic
` TG Points to Remember
` Stored charge leaks away due to reverse-bias leakage current ` Stored value is good for about 1 ms ` Value must be rewritten to be valid ` If not loaded every cycle, must ensure that latch is loaded often enough to keep data valid ` Capacitance comes primarily from inverters gate logic
CMOS Logic
` TG Layout
CMOS Logic
` TG Properties
` Strong pull-up ` Strong pull-down ` May be difficult to design into a circuit (layout) because of close proximity of N and P devices (design rule separation) ` Always requires 2N transisitors for any N x TG design ` Many logic functions (multiplexers in particular) are easily implemented using TG based designs
CMOS Logic
` Complementary Pass-transistor Logic (CPL) or Differential (+) TG Logic
` Dual-rail form of pass transistor logic ` Avoids need for ratioed feedback
A A B B A A B B
PT Network F
A S B S L Y
Inverse PT Network
S B
CMOS Logic
` CPL
B A B A B AND/NAND B
CMOS Logic
` 4 Input NAND in CPL
CMOS Logic
` CPL Advantages
` Differential so complementary data inputs and outputs are always available (so dont need extra inverters) ` Still static, since the output defining nodes are always tied to Vdd or GND through a low resistance path ` Design is modular, all gates use the same topology, only the inputs are permuted ` Simple XOR makes it attractive for structures like adders ` Fast (assuming number of transistors in series is small)
CMOS Logic
` CPL Disadvantages
` Additional routing overhead for complementary signals ` Still have static power dissipation problems ` VOH is very weak! Then we need an inverter at the output
CMOS Logic
` Differential Cascode Voltage Switch Logic (DCVSL)
` Compute both true and complementary outputs using a pair of complementary NMOS pull-down network ` The PMOS transistors are driven by the output of the complementary network ` No static power consumption ` Fast response
Inputs
CMOS Logic
` Example: NAND/AND
Y = AB
Y =A+B
A Series B
CMOS Logic
` General Design
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
F 1 0 0 1 0 1 1 1
C
B A
+
_
0 _ +
_
1
_
+
_
CMOS Logic
` General Design
a
x
b
+
b
x
x
u
+
u
u
u = ax + bx
a
_
u1
u2
u1
u2
CMOS Logic
` General Design
0
C B A
_
1
_
+
_
0 _ +
_
1
_
C
B A
+
_
+
_
+
_
+
_
CMOS Logic
` Example: XOR/XNOR
CMOS Logic
` Rules of Thumb
` ` ` ` ` Step-up (alpha) ratio of 2.7 (e) produces minimum powerdelay product P vs. N (beta) ratio of 2 balances pull-up and pull-down times and noise margins Approximately 75% of static logic are NAND stacks (limit stack to 3-4, use ordering and tapering for speed) Glitches consume approximately 15% of overall chip power Crossover (short-circuit) current consumes ~ 10% of a static chips total power (but is a function of input/output slews, ie sizing)
Summary
` This lecture describes the basic MOS Logic Gates which require no clock or other periodic signal for operation and also implementation of them in three following levels
` Gate Level ` Transistor level ` Layout Level
Contents
` ` ` ` ` ` ` Introduction Dynamic CMOS Logic CMOS Domino Logic CD Domino Logic Dynamic CVSL Sample-Set Differential Logic (SSDL) Summary
Introduction
` As mentioned before Digital MOS circuits can be classified into two categories:
` Static Circuits: require no clock or other periodic signal for operation (except sequential logic). In these circuits at every point in time (except when switching) the output is connected to either GND or Vdd via a low resistance path ` fan-in of N requires 2N devices (n N-type + n P-type) ` Dynamic Circuits: require periodic clock signals, synchronized with data signals, for proper operation even in combinational logic. These circuits rely on the temporary storage of signal values on the (parasitic) capacitance of high impedance nodes ` requires only N + 2 transistors (n+1 N-type + 1 P-type) ` takes a sequence of precharge and conditional evaluation phases to realize logic functions
Introduction
` Why Dynamic Logic? ` In the area of high speed, higher Fan-in, extremely low power dissipation, other digital logic circuit have been considered. In this lecture, two of these alternatives to CMOS are described. The circuits are basically NMOS or CMOS Gates with slight improvements. These are:
` Dynamic CMOS Logic ` CMOS Domino Logic
` Each of them have specific operating advantages over NMOS or CMOS, but exhibit disadvantages in other areas
Dynamic CMOS Logic

` ` Dynamic Gates use a clocked PMOS pullup Two modes: precharge and evaluate
Precharge
Evaluate
Precharge
Dynamic CMOS Logic

` The Foot
` What if pulldown network is ON during precharge? ` Use series evaluation transistor to prevent fight
Y A
precharge transistor
foot
Dynamic CMOS Logic

` Dynamic CMOS Logic
` To make the gate dynamic, a clock pulse is applied to the gate of complementary P and N channel devices. This gate consists of an NMOS Logic circuit whose output node is precharged to Vdd by the PMOS, when the clock is zero. The output node is discharged by the NMOS transistor connected to ground when the clock is high
CLK
PCLK
NMOS Logic Circuit
N CLK
Dynamic CMOS Logic

` Dynamic CMOS Logic
Mp
1 2 3
Me
Precharge (Clk = 0) Evaluate (Clk = 1)
Dynamic CMOS Logic

` Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation ` Inputs to the gate can make at most one transition during evaluation ` Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL
Dynamic CMOS Logic

` Canonical Forms
Dynamic CMOS Logic

` Properties of Dynamic Gates
` Logic function is implemented by the PDN only
should be smaller in area than static complementary CMOS
` Full swing outputs (VOL = GND and VOH = VDD) ` Nonratioed - sizing of the devices is not important for proper functioning (only for performance) ` Faster switching speeds
reduced load capacitance due to lower number of transistors per gate (Cint) so a reduced logical effort reduced load capacitance due to smaller fan-out (Cext) no Isc, so all the current provided by PDN goes into discharging CL Ignoring the influence of precharge time on the switching speed of the gate, tpLH = 0 but the presence of the evaluation transistor slows down the tpHL
Dynamic CMOS Logic

` Properties of Dynamic Gates
` Power dissipation should be better
consumes only dynamic power no short circuit power consumption since the pull-up path is not on when evaluating lower CL- both Cint (since there are fewer transistors connected to the drain output) and Cext (since there the output load is one per connected gate, not two)
` But power dissipation can be significantly higher due to

higher transition probabilities extra load on CLK
` PDN starts to work as soon as the input signals exceed VTn, so set VM, VIH and VIL all equal to VTn
low noise margin (NML)
` Needs a precharge/evaluate clock
Dynamic CMOS Logic

` Leakage Sources
` Subthreshold conduction ` Transistors cant abruptly turn ON or OFF ` Reverse-biased PN junction diode current
Is depends on doping levels And area and perimeter of diffusion regions, typically < 1 fA/m2
109 106 103 100 10-3 10-6 10-9 0 0.3 0.6 0.9 1.2 1.5 VDD trend
tox 0. 6 nm 0. 8 nm 1. 0 nm 1. 2 nm 1. 5 nm 1. 9 nm
` Gate Leakage
Carriers may tunnel thorough very thin gate oxides Negligible for older processes
1.8
VDD
Dynamic CMOS Logic

` Leakage Sources
` Output settles to an intermediate voltage determined by a resistive divider of the pull-up and pull-down networks ` Once the output drops below the switching threshold of the fan-out logic gate, the output is interpreted as a low voltage
2.5 V o lta g e (V ) 1.5 0.5 -0.5 0 20 40
CLK Out
Time (ms)
Dynamic CMOS Logic

` Leakage Sources
` Subthreshold leakage is dominant in modern transistors CLK
p
VOut
e
Evaluate Precharge
Leakage sources
Dynamic CMOS Logic

` Solution to Charge Leakage
Mp M kp
Me
Dynamic CMOS Logic

` Charge Sharing
` Charge stored originally on CY is redistributed (shared) over CX leading to static power consumption by downstream gates and possible circuit malfunction ` When Vout = - Vdd (CX / (CX + CY )) the drop in Vout is large enough to be below the switching threshold of the gate it drives causing a malfunction
A B=0 x Cx Y CY
A Y Charge sharing noise x
V x =V Y =
CY V dd C x + CY
Dynamic CMOS Logic

` Solution to Charge Redistribution
` Add secondary precharge transistors (at the cost of increased area and power)
Typically need to precharge every other node Secondary precharge transistors should be small because their diffusion capacitance slows the evaluation (increase delay) Big load capacitance CY helps as well
secondary precharge transistor
Y A B x
Dynamic CMOS Logic

` Charge Sharing Example
` What is the worst case voltage drop on y? (Assume all inputs are low during precharge and that all internal nodes are initially at 0V)
Dynamic CMOS Logic

` Charge Sharing Example
Vout = Vdd ( Ca + Cc ) Ca + Cc + C y = 2.5V ( 30 ( 30 + 50 ) ) = 0.94V
CLK y=A a Ca =15fF B c Cc =15fF A B C CLK A b B C B d B C
Load inverter
Cy =50fF
Cb =15fF Cd =10fF
Dynamic CMOS Logic

` Backgate Coupling
` Susceptible to crosstalk due to
High impedance of the output node Capacitive coupling
Out2 capacitively couples with Out1 through the gate-source and gatedrain capacitances of M4
CLK A=0 B=0 CLK
Mp M1 M2 Me M6 M4 M3 M5
Out1 =1 CL1
Out2 =0 CL2 In
Dynamic NAND
Static NAND
Dynamic CMOS Logic

` Backgate Coupling
` Capacitive coupling means Out1 drops significantly so Out2 doesnt go all the way to ground
3
Due to clk feedthrough
Voltage
Out1 Due to backgate Clk In

0 2
Out2
-1
Time, ns
Dynamic CMOS Logic

` Clock Feedthrough
` A special case of capacitive coupling between the clock input of the precharge transistor and the dynamic output node due to the gate to drain capacitance ` So voltage of Out can rise above Vdd. The fast rising (and falling edges) of the clock couple to Out
Mp
Me
Dynamic CMOS Logic

` Clock Feedthrough
2.5
Clock feedthrough
1.5
Voltage
0.5
In & Clk Out
-0.5 0 0.5
Time, ns
Clock feedthrough
Dynamic CMOS Logic

` Other Effects
` ` ` ` ` Capacitive coupling Substrate coupling Minority charge injection Supply noise (Ground bounce) Floating output nodes
Dynamic CMOS Logic

` Floating output nodes
` Solutions:
Only connect to gates Add staticizer to refresh the charge
s
0 s 0
Dynamic CMOS Logic

` Advantages:
` For n inputs, dynamic logic requires n+2 transistors ` have small area, high speed and compact layouts
CLK
PCLK
NMOS Logic Circuit
` Disadvantages:
` Circuit operation is more complex due to the required clock ` The inputs can only change during the precharge phase and must be stable during the evaluate portion of the cycle ` Need Monotonicity
can not be cascaded
N CLK
Dynamic CMOS Logic

` Monotonicity
` Dynamic gates require monotonically rising inputs during evaluation
violates monotonicity during evaluation A Y Output should rise but does not Precharge Evaluate Precharge
Dynamic CMOS Logic

` Monotonicity Woes
` Dynamic gates produce monotonically falling outputs during evaluation ` Illegal for one dynamic gate to drive another!
A1 = Precharge X X monotonically falls during evaluation Y Y should rise but cannot Evaluate Precharge
Dynamic CMOS Logic

` Cascading
V Clk In Out1 Out2 t VTn V
Only 0 1 transitions allowed at inputs!
Dynamic CMOS Logic

` Cascading
` Input going from high to low during evaluation
a is 5V when precharge b = 5V, c = 5V During evaluation:
Wanted: b 0V, c 5V But, b takes some time to drop to 0V Consequently, c may fall to some unknown value
` Solution
` NP-CMOS ` NORA Logic ` Domino logic
b a c
Dynamic CMOS Logic

` NP-CMOS
` Only 0 1 transitions allowed at inputs of PDN ` Only 1 0 transitions allowed at inputs of PUN
Clk In1 In2 In3 Clk
Mp
1 1 1 0
Out1
Clk In4
Me
PUN
0 0 0 1
PDN
Me
In5
Mp
Clk
Out2 (to PDN)
Dynamic CMOS Logic

` NORA Logic
` WARNING: Very sensitive to noise!
Me
Clk In1 In2 In3 Clk
Mp
1 1 1 0
Out1
Clk In4
PUN
0 0 0 1
PDN
Me
In5
Mp
Clk to other PDNs
Out2 (to PDN)
to other PUNs
Dynamic CMOS Logic

` An example
Dynamic CMOS Logic

` Dynamic 4 Input NAND Gate
VDD
Out
In1 In2 In3 In4
GND
Dynamic CMOS Logic

` Power Consumption
` Power only dissipated when previous Out = 0
1 2 3
e
Dynamic CMOS Logic

` Power Consumption
` Dynamic Power Consumption is Data Dependent
Assume signal probabilities (Dynamic 2-input NOR Gate) PA=1 = 1/2 PB=1 = 1/2 A B Out Then transition probability 0 0 1 P10 = Pout=0 =
0 1 1
1 0 1
0 0 0
` Switching activity can be higher in dynamic gates!
Dynamic CMOS Logic

` Rules of Thumb
` ` Dynamic logic is best for wide OR/NOR structure (e.g. bitlines), providing 50% delay improvement over static CMOS Dynamic logic consumes 2x power due to its phase activity (unconditional pre-charging), not counting clock power
Dynamic CMOS Logic

` Notes
` No need to implement the complement of the function, leading to smaller area ` We can avoid the long PMOS chains ` Handle the charge sharing problem and floating output nodes ` Input transistors should not change from on to off during evaluation
CMOS Domino Logic

` It is an extension of dynamic CMOS gates that allow cascading of stages ` The simple modification entails incorporating a static CMOS inverter at the output of each logic gate
Clk
Mp
1 1 1 0
Clk Out1
0 0 0 1
Mp Mkp
domino AND
Out2
W X C Y Z A B
In1 In2 In3 Clk
PDN
In4 In5 Clk
PDN
Me
Me
dynamic static NAND inverter
CMOS Domino Logic

` Stage A should be precharged in 1 and evaluate in 2 ` Stage B should be precharged in 2 and evaluate in 1
CMOS Domino Logic

` During precharge (clk=0), the output node of the dynamic gate is precharged high and the output node of the CMOS inverter is low. Then subsequent stages will be turned off during the precharge phase ` When the clk=1, the output of the driving gate will conditionally discharge, allowing the output of the inverter to conditionally go high. Each connected gate output can then make a transition from low-to-high, in sequence ` There is no restriction on the number of logic stages that can be cascaded provided that all stages can evaluate during one clock pulse
CMOS Domino Logic

` pc = 1 and ev = 2
pc =
1
pc
ev = cycle
W n- network
1
ev
precharge input latched here
evaluate output latched here
CMOS Domino Logic

` Wont work! If pc = 2 and ev = 1
pc =
2
ev = cycle
precharge precharge evaluate input latched here evaluate output latched here
CMOS Domino Logic

` Why Domino?
` Like falling dominos!
CMOS Domino Logic

` Produces monotonic outputs
Precharge Evaluate Precharge
domino AND
W
W A B
X C
X Y Z
dynamic static NAND inverter

A B
W H C X
Y H Z = A B
X C
CMOS Domino Logic

` Domino Optimizations
` Each domino gate triggers next one, like a string of dominos toppling over ` Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge ` HI-skewed static stages can perform logic ` Static inverter can be optimized to match fan-out
S0 D0 S1 D1 S2 D2 S3 D3 H S4 D4 S5 D5 S6 D6 S7 D7 Y
CMOS Domino Logic

` Leakage
` Dynamic node floats high during evaluation
Transistors are leaky (IOFF 0) Dynamic value will leak away over time Formerly miliseconds, now nanoseconds!
` Use keeper to hold dynamic node

Must be weak enough not to fight evaluation
weak keeper A 1 k 2 2 X H Y
CMOS Domino Logic

` Noise Sensitivity
` Dynamic gates are very sensitive to noise
Inputs: VIH Vtn Outputs: floating output susceptible noise
` Noise sources
Capacitive crosstalk Charge sharing Power supply noise Feedthrough noise And !
CMOS Domino Logic

` Designing with Domino Logic
` ` If all the inputs come from other domino gates, then all the inputs will be low during the precharge. You dont need to explicit evaluate transistor Need to be a little careful. When precharge begins, the first gates output must precharge before the next gate can precharge. Both evaluate and precharge ripple in this scheme. But, if there is already a tall stack, transistor ratioing will let precharge win anyway. (but you waste power until the precharge ripples)
CMOS Domino Logic

` Example
` During precharge, x, y, z = 1, x, y = 0 ` During evaluation, x = 0 when a = b = 1 ` Therefore, z = a b c d
x a b x c
y y
CMOS Domino Logic

` Advantages:
` Large Fan-in, fewer transistors (n+4 transistors, whereas CMOS requires 2n) ` Single clock can be used to precharge and evaluate all stages at the same time ` It is attractive for high-speed circuits ` 1.5 2x faster than static CMOS ` Widely used in high-performance microprocessors
` Disadvantages:
` ` ` ` ` ` Each logic block must incorporate a separate inverter Each block performs only non-inverting logic Monotonicity Leakage Charge sharing Noise
CMOS Domino Logic

` Dual Rail Domino
` Domino only performs noninverting functions
AND, OR but not NAND, NOR, or XOR
Y_l inputs f f Y_h
` Dual-rail domino solves this problem

Takes true and complementary inputs Produces true and complementary outputs
sig_h 0 0 1 1
sig_l 0 1 0 1
Meaning Precharged 0 1 invalid
CMOS Domino Logic

` Example AND/NAND
` Given A_h, A_l, B_h, B_l ` Compute Y_h = A * B, Y_l = ~(A * B)
Pulldown networks are conduction complements
Y_l = A*B A_l B_l
A_h B_h
Y_h = A*B
CMOS Domino Logic

` Example XOR/XNOR
` Sometimes possible to share transistors
Y_l = A xnor B A_h A_l B_l
A_l B_h A_h
Y_h = A xor B
CMOS Domino Logic

` Rules of Thumb
` ` Typical domino keepers have W/L = 5-20% of effective width of evaluate tree Typical domino output buffers have a beta ratio of ~ 6:1 to push the switch point higher for fast rise-time
CD Domino Logic
` We noted that dynamic inputs never make 1 to 0 transitions while in evaluation ` Two solutions:
` Precharge outputs low using an inverting gate (standard domino) ` Delay the evaluate clock until inputs settle (CD domino)
CD Domino Logic
` Self-timed dynamic logic family ` Consists of a dynamic gate, and an optional delay element for the clock signal
Mpre Out = a+b a clk(i) b Meval delay clk(i+1)
CD Domino Logic
` Advantages
` Uses single-rail circuits, rather than dual-rail for standard domino ` Provides both inverting and non-inverting functions ` High-speed, large fan-in NOR and OR circuits
CD Domino Logic
` Delay Matching
` CD domino requires delay matching between the slowest dynamic gate at a level and a delay element ` A 20% margin is typically added to the delay of the fixed delay element to account for PVT variations ` Thus, 20% of the speed gain possible with CD domino is not realized ` Average speed gain of (60+20)% is theoretically possible
` Use digitally programmable delay elements (PDEs) to reduce the margin and attain a speed improvement without affecting the reliability in the presence of variations
CD Domino Logic
` Clocking Scheme
` The circuits are fully levelized ` The delay element on each level is tuned to the
slowest gate at its level, plus a 20% margin
(other gates) . . dynamic gate (other gates) . . dynamic gate (other gates) . . dynamic gate
primary inputs
dynamic gate
dynamic gate
dynamic gate
clk1
fixed delay gate level 1
clk2
clk3
clk4
Dynamic CVSL
` Positive feedback does not exist
F
C
In{
NMOS Logic Array
} In
Sample-Set Differential Logic (SSDL)

` It is one type of Dynamic CVSL with positive feedback ` By this logic the low level output is guaranteed to zero in evaluation phase
F C
F
C
In{
NMOS Logic Array
} In
Summary
` This lecture describes many basics CMOS Logic Gates which require clock or other periodic signal for operation ` These circuits rely on the temporary storage of signal values on the (parasitic) capacitance of high impedance nodes

Mos Logic

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MOS Logic and Gate Circuits

Introduction NMOS Logic

Transmission Gates Family

Differential Cascode Voltage Switch Logic Rules of Thumb

W L VoL C Speed P RL Area

Vds2 = Vgs2 Vds2 > Vgs2 VT2 M2 is in saturation

i Vo = 1 ( rds1 rds2 ) Vi Vi Vo rds1 rds2 rds1 = i1

i1 = K1 ( Vgs1 VT1 Vo ) Vo K1Vo Vo = = 1 Vi K1 (Vgs1 VT1 Vo) Vo = Vi VT1 2 V VT1 Vi = VIH IH = Vo 2

i1 = i 2 1 2 2 = K1 V V Vo Vo 2 K (Vdd Vo V ) ( ) T1 T2 IH 2 2 2(Vdd VT 2 ) VIH = + VT1 3R + 1

PdisH 0, PdisL = Id Vdd Pdis = 1 2 Id Vdd

VGG Vdd + VT2

VIL Vdd Vi VT VIH

i1 = K1 ( Vi VT1 ) Vi K1 (Vi VT1 ) Vo = 1 = Vi K 2 (VGG Vo VT 2 Vds2) VIL = f (Vo)

rds2 rds1 rds2

Vi = Low i1 = 0, M1 in cutoff i1 = i 2 = 0 K2 if M2 is in saturation then i 2 = (Vgs2 VT 2 ) 2 , Vgs2 = 0 i 2 > 0 2

VIL Vdd Vi VT VIH

C tot = CL + Ceq d sub1 + Ceq s sub2 + Cgs2 + 2 Cgd1

Super Buffer (1) Circuit

` Logical effort is proportional to C/I ` PMOS are the enemy!

` In CMOS, use a PMOS that is always ON

Assuming that VT = VTn = VTp

W/Lp = 0.5 W/Lp = 0.25

In1 In2 In3 In4

Vy Vx Vdd Vy Vdd M6 on Vz = Vy VTN

V dd Vdd Level Restorer B A Mn X M1 Mr M2 Out

For correct operation Mr must be sized correctly (ratioed)

off but leaking

off but leaking

` Be careful, because it is bi-directional

C = Vss, C = 0 Both transistor are on A = Y

Vy(0 ) = 0, C = Vdd, C = 0, VTP < Vdd VTN

N = off rP CL t Vy = Vdd V t t Vy = Vdd TN P = triode

VA (t) = Vddu(t) t Vy(t) = Vdd 1 exp TG TG = R TG CL R TG = rN rP u(t) A

2VAN rN 2 N (Vdd VTN ) 2VAP rP P (Vdd VTP ) 2 VA is Early Voltage

Vdd VTN Vdd

1) Load Q n = D n 2) Hold Q n = Q n-1

Req V Req V Req V Req V i i +1 n 1 n

` Delay of Buffered chain

Dynamic CMOS Logic

Dynamic CMOS Logic

Dynamic CMOS Logic

Dynamic CMOS Logic

Precharge (Clk = 0) Evaluate (Clk = 1)

Dynamic CMOS Logic

Dynamic CMOS Logic

Dynamic CMOS Logic

Dynamic CMOS Logic

` But power dissipation can be significantly higher due to

` Needs a precharge/evaluate clock

Dynamic CMOS Logic

Dynamic CMOS Logic

Dynamic CMOS Logic

Dynamic CMOS Logic

Dynamic CMOS Logic

A Y Charge sharing noise x

Dynamic CMOS Logic

Dynamic CMOS Logic

Dynamic CMOS Logic

CLK y=A a Ca =15fF B c Cc =15fF A B C CLK A b B C B d B C

Dynamic CMOS Logic

Dynamic CMOS Logic

Due to clk feedthrough

Out1 Due to backgate Clk In

Dynamic CMOS Logic