EXP 1

2.What happens VR is more positive than V(1)? (In CKT1)

If VR is more positive than V(1) then for circuit 1 all the diodes will always be forward biased and hence
output will always be low irrespective of input.
3.What happens if not all inputs have the same upper level? (In CKT1 , In CKT1)
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Answer:

If for any reason not all the inputs have the same upper level V(1), then the output of the positive AND gate of
the circuit-ii will equal V(1)min, the least positive value of V(1). The diode connected to V(1) min conduct, clamping the
output to this minimum value of V(1) and maintaining all other diodes in the reverse-biased condition.

The output of a positive-logic OR gate is equal to the most positive level V(1).

4.Why the resistance in the output circuit is so high? Why diode D2 is used? (In CKT3, CKT4)
Answer:

In circuit III & IV, high value of RC is used to minimize the collector current when the transistor is in
saturation. As IC is reduced, hfe(min) is also reduced. As a result, the transistor is driven more into saturation. Fan-out is
also increased with the fall in IC.

If at least one input is at V(0), the V P = 0.2 + 0.7 = 0.9V. Hence if only one diode D 1 is used between P and B,
then VBE becomes 0.3V, where 0.6V represents the diode cut-in voltage. Since the cutin base voltage is 0.5V, and then
theoretically Q is cut off. But a small (>0.2V) spike of noise will turn Q on. This is why D 2 is used, to prevent the gate
from malfunctioning.

5.Can emitter and collector be interchanged? (In CKT3, CKT4)

In this circuit, the transistor is used with its collector and emitter interchanged. It will saturate when the emitter-
base junction becomes forward-biased. In this case,

I' / IB < hfe (R)

Since hfe (R) is very low, I' has to be much smaller than IB, with the result that V CE(sat) will be very small. This is
indeed the usual reason

for operating the BJT in the reverse saturation region. The disadvantage of the reverse saturation mode is a
relatively long turnoff time.

6.What is the significance of hfe(min)? (In CKT3, CKT4)

Answer:

In the NAND and NOR diode-transistor logic (DTL) gates (circuit – iii, iv), when the outputs are in the 0
state, the transistor operates in the saturation region. In order to have the transistor in saturation, the transistor must be
on and hfe of the transistor must be greater than the minimum value of hfe. Here hfe(min) denotes the ratio of the collector
current and the base current when the output voltage equals V(0). As hfe(min) is reduced, the transistor is driven deeper
into saturation.

Higher hfe(min) also suggests increased fan-out of the circuit.

EXP 2
 1. Which factor affect the switching speed of the transistor and how?
Answer:

The internal capacitive effect of the transistor affects the switching speed of it and it does not switch in zero
time. When the input voltage v1 rises from the negative (zero) level V(0) to the positive level V(1), the collector
current does not respond immediately. Rather a delay time t D elapses before any appreciable collector current begins to
flow. This delay time is required mainly for the EBJ depletion capacitance to charge up to the forward-bias voltage
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VBE (approximately 0.7V). After this charging process is completed, the collector current begins an exponential rise
toward a final value of βIB.

In fact, it is during the interval of the rising edge of IC that the excess minority carrier charge is being stored in the
base region. Since the transistor will saturate, the collector current will be limited to I C(sat). The excess minority charge
stored in the base region does contribute in a corresponding collector current component. Rather, this extra charge
arises from the forcing of more current into the base than is required to saturate the transistor.

Let us now consider the turn-off process. When the input voltage v1 returns to the low level V(0), the collector
does not respond but remains constant for a time, ts. This is the time required to remove the saturating charge from the
base, known as the storage time. The reverse current I B1 helps to “discharge the base” and remove the extra stored
charge; in the absence of IB1, the saturating charge has to be removed entirely by recombination. Once the extra charge
stored has been removed, the collector current begins to fall exponentially with a time constant determined by the
junction capacitances and the output voltage reaches the 1 level, V(1).

(Last 2 Questions are missing : APPEND here)

EXP -3

2. What are the difference of transistors T1 & T2 with that of a multi-emitter

transistor and discuss with respect to operations?
If T1 and T2 are replaced by a multi-emitter transistor, then it can easily be verified that
the circuit performs the NAND operation. The output will be low in only one case: when both
inputs are high. Extensions to more than two inputs can be achieved by diffusing additional
emitter regions.

Although theoretically an unused input terminal in a multi-emitter transistor may be

left open circuited, this is generally not a good practice. An open-circuit input terminal acts as
an “antenna” that “picks up” interfering signals and thus could cause erroneous gate
switching. An unused input terminal should therefore be connected to the positive power
supply through a resistance. In this way, the corresponding base-emitter junction will be
reverse-biased and thus will have no effect on the operation of the gate. The series resistance
is included in order to limit the current in case of breakdown of the bas-emitter junction due
to transients on the power supply.

But when a multi-emitter transistor is not used, the circuit can be modified according to
the total no. of inputs just by adding or removing additional transistors.

3. What is totem-pole stage?

If the collector-circuit resistor, RC of the inverter is replaced by an active pull-up circuit
containing a transistor, then the output configuration is called a totem-pole amplifier, because
the transistor T5 “sits” upon T4. It is also referred to as a power-driver, or power-buffer, output-
stage.

4. Why totem-pole stage is used in place of passive pull-up resistor?

 At the output terminal of the DTL or TTL gate there is a capacitive load C L, consisting of
the capacitances of the reverse-biased diodes of the fan-out gates and any stray wiring
capacitance. If the collector-circuit resistor of the inverter is RC (called a passive pull-up), then,
when the output stage changes from the low to the high state, the output transistor is cut-off
and the capacitance charges exponentially from VCE(sat) to VCC. The time constant RCCL of this
waveform many introduce a prohibitively long delay time into the operation of these gates.
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The output delay may be reduced by decreasing RC, but this will increase the power
dissipation when the output is in its low state and the voltage across R C is VCC – VCE(sat). In order
to minimize the power dissipation, a better solution is applied by using a totem-pole stage
where an active pull-up circuit (transistor) replaces the passive pull-up element, RC.

5. What is the function of T3?

The transistor T3 acts as a phase splitter, since the emitter voltage is out-of phase with the
collector phase (for an increase in base current, the emitter voltage increases and the collector
voltage decreases). Thus it is used to generate two complementary voltage signals required to
drive the totem-pole circuit.

6. Why resistor R4 is used?

If the resistance R4 were omitted, there would result a faster change un output from
V(0) to V(1). However R4 is needed to limit the current spikes during the turn-on and turn-off
transients.

7. Why diode D0 is used in the circuit?

Without diode D0 in the circuit, T5 would conduct slightly when the output is low. To
prevent this, the diode is inserted; its voltage drop keeps the base-emitter junction of T5
reverse-biased. In this way, only T4 conducts when the output is low.

8. Why two totem-pole gates cannot be WIRED-AND?

If the output from one gate is high while that from a second gate is low, and if these
two outputs are tied together, then this situation results in a transient current spikes. Hence
if, the WIRED-AND were used, the power supply would deliver a steady current of 41mA under
these circumstances.

This is why, two totem-pole gates should not WIRED-AND.

9. What do you mean by open collector gates?

Answer:
Page6

Circuit: Open-collector gate

Instead of a totem-pole output, some TTL devices have an open-collector output. This
means they use only the lower transistor of a totem-pole pair. Because the collector of T 4 is
open. A gate like this won’t work properly until an external pull-up resistor is connected.

The output of open-collector gates can be wired together and connected to a common
pull-up resistor. This is known as WIRE-AND. The big disadvantage of a open-collector gates is
their slow switching speed.

8.What are the features and advantages of TTL gates?:

a. TTL uses transistors almost exclusively; it has become the most popular family of
SSI and MSI chips. It is the transistor which gives TTL the highest speed of any
saturated logic.
b. A standard TTL has a power dissipation of about 10 mW. It may vary from this value
because of signal levels, tolerances, etc., but on the average, it’s 10mW per gate.
c. The propagation delay time of a TTL gate is in vicinity of 10 ns.
d. The advantage of a totem-pole connection is its low output impedance.

EXP 4

2.Analyze the operation of RTL NOR gate with the experimental data.
If one of the inputs is high (let, Vi1 = 3.5V), then the corresponding transistor becomes on
and saturates. This results in VO = 15 mV which is low (logic 0). When other input is also high
(Vi2 = 3.46V), then the corresponding transistor (Q2) turns on and operates in the saturated
region. Thus the output voltage remains in the logic 0 level (VO = 11.7 mV).

High output is observed only when both of the inputs are low. When, V i1 = 3.7 mV. Vi2 = 3
mV, then both Q1 and Q2 are off simultaneously. In this situation, the output voltage, VO = 4.95
V ≈ VCC.

3.What is the importance of studying the RTL gate?

• NOR operations can be performed with the RTL gate. Since, the NOR gate is a universal
gate, any logic functions can be implemented with this RTL gate.
 • The RTL gate is the first manufactured logic family. It is no longer used in new systems
because its fan-out is low, the output depends upon the fan-out, the noise margins are
small and the output swing is low (not compatible with TTL). But the RTL gate leads to a
convenient introduction to DCTL, which is used in MOS and CMOS logic.

EXP 5
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1. What are the purposes of emitter-followers in the ECL circuit? :

The emitter followers have two purposes: First, they shift the level of the output signals
by one VBE drop. Thus in this circuit the output levels become -1.55V and -0.75V. These shifted
levels are centered approximately around the reference voltage (VR = -1.15V), which means
that one gate can drive another. This compatibility at input and output is always an essential
requirement in the design of gate circuits.

The second function of the output emitter followers is that they provide the gate with
low output resistances and with the large output currents required for charging load
capacitances.

2. What are the advantages and disadvantages of ECL gates?

Advantages:

I. Since the transistors do not saturate, then the highest speed of any logic family is
available.
II. Complementary outputs are available.
III. Current switching spikes are not present in the power supply leads.
IV. Outputs can be tied together to give the implied-OR function.
V. There is little degradation of parameters with variations in temperature.
VI. The number of functions available is high.
VII. Data transmission over long distances by means of balanced twisted-pair 50Ω is
possible.
Disadvantages:

I. A small voltage difference (800 mV) exists between the two logic levels and the noise
margins are only ±200 mV.
II. The power dissipation is high relative to other families.
III. Level shifters are required for interfacing with other families.
IV. Capacitive loading limits the fan-out.

3. Why ECL is the fastest of all logic gates?

Emitter-coupled logic (ECL) is the fastest logic circuit family. High speed is achieved by
operating all transistors out of saturation, thus avoiding storage time delays, and by keeping
the logic signal swings relatively small (about 0.8V), thus reducing the time required to
charge and discharge the various load and parasitic capacitances.

5. Calculate the noise margins?

NM(0):

When all the inputs are at V(0) = -1.55V, Q1 and Q2 are cut-off and Q3 is conducting. The
voltage at the common emitter is VE = -1.15 - 0.7 = -1.85V. Then the base-to-emitter voltage
of an input transistor is VBE = -1.55 + 1.85 = 0.30V. As a result, an input transistor is within
0.50 – 0.30 = 0.20V of cutin. So, NM(0) = -0.20V.
 NM(1):

If at least one input is high, then Q3 is cut-off. Now VE becomes (-0.75-0.7) = -1.45V and
VBE3 = -1.15 + 1.45 = 0.30V. Hence a negative spike at the input of 0.20V drops V E by the
same amount and brings VBE3 to 0.50V or to the edge of conduction. So, NM(1) = 0.20V

EXP 6
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1. Analyze the operation of SR FF with the experimental data.

Hold condition:

When both S and R are the logic level ‘1’ and clock pulse (CLK) is provided, the input
transistors T1, T2, T5 and T6 operate in their saturation region. Thus V1 and V2 will be at V(0).
The experimental values of V1 and V2 are 0.01V (approx.). Since both R and S are at logic level
‘0’, the voltages at Q and Q will be retained. The experimental values also show the same
result.

S R Qn-1 Qn Qn
1 1 0.01 V 0.01 V 2.30 V
1 1 2.30 V 2.30 V 0.01 V

Set condition:

When S is at logic level ‘0’ and R is at ‘1’ and negative clock pulse is provided, the
input transistors T5, T6 remain off, but T1 turns on. Thus V1 being the NOR output of two V(0)
inputs will be at V(1), but V2 will be at V(1). The experimental values of V1 and V2 are 0.01V
and 2.64V respectively.

Since S is at logic level ‘1’ and R is at ‘0’, whenever the clock pulse arrives, Q will be at
V(1) and Q at V(0).

S R Qn-1 Qn Qn
0 1 0.01 V 2.30 V 0.01 V
0 1 2.30 V 2.30 V 0.01 V

Reset condition:

When S is at logic level ‘1’ and R is at ‘0’ and negative clock pulse is provided, the
input transistors T5 turns on but T1 and T2 turns off. Thus V1 and V2 will be at V(1) and V(0)
respectively. The experimental values of V1 and V2 are 0.01V and 2.64V respectively.

Since S is at logic level ‘0’ and R is at ‘1’, whenever the clock pulse arrives, Q will be at
V(0) and Q at V(1). The experimental values also reveal the proper operation of the reset
condition of the SR FF.

S R Qn-1 Qn Qn
0 1 0.01 V 0.01 V 2.30 V
0 1 2.30 V 0.01 V 2.30 V
 2. What is the race around condition in SR FF? Discuss with respect to the internal
circuit
Answer:

When both S and R are high simultaneously, there will be a race condition in the FF. It is
never used because it leads to unpredictable operation.
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As, S and R are at the logic ‘0’, whenever the negative clock pulse arrives, both V1 and V2
become high (=2.64V). The two output NOR gates will cause both Q and Q to become ‘0’. In
this case, the complementary labelling of these two variables becomes incorrect. However
when both R and S returns to ‘0’, both transistors, T 3 and T7 try to come out of saturation. It is
a race between the transistors to see which one desaturates first. The faster transistor (the
one with the shorter saturation delay time) will win the race and latch the circuit. Since either
transistor can be faster, the Q output is unpredictable. This is why the race condition must be
avoided.