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Interrupts
Hardware Event
When an interrupt occurs, the main program temporarily suspends execution and branches to the interrupt service routine (ISR), perform the operation, and terminates with a return from interrupt instruction (RETI).
Ref. I. Scott Mackenzie L Ch Thng 2
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Interrupts
An interrupt = Occurrence of a condition (an event) Deal with the event while another program is executing Do many things simultaneously When an interrupt occurs, the main program temporarily suspends execution and branches to the interrupt service routine (ISR), perform the operation, and terminates with a return from interrupt instruction (RETI). ISR vs. subroutine: Similarity: CPU executes another program and then returns to the original program. Difference: It is NOT known when the main program suspends execution.
Ref. I. Scott Mackenzie L Ch Thng 3
Interrupt Sources
2 external interrupts (/INT0 and /INT1), 2 timer interrupts (TF0 and TF1), a serial interrupt (RI or TI), and Timer 2 interrupt (8052 only) Ref. I. port Scott Mackenzie L Ch Thng 4
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EA : Global enable/disable - : Undefined ET2: Enable Timer 2 interrupt ES: Enable Serial port interrupt ET1: Enable Timer 1 interrupt EX1: Enable External 1 interrupt ET0: Enable Timer 0 interrupt EX0: Enable External 0 interrupt
1 = Enable; 0 = Disable
Eg. Timer 1 interrupt is enabled as follow: SETB ET1 SETB EA or MOV IE,#10001000B Eg. External 0 and serial interrupts are enabled as follow: SETB EX0 SETB ES SETB EA or L Ch Thng MOV IE,#10010001B 5
Interrupt Priority
PT2 PS PT1 PX1 PT0 PX0
IP (Interrupt Priority) Register
PT2 : Priority for Timer 2 interrupt If 2 interrupts occur simultaneously a high-priority ISR executes PS: Priority for Serial port interrupt If a low-priority ISR is executing PT1: Priority for Timer 1 interrupt when a high-priority interrupts PX1: Priority for External 1 interrupt the low-priority is interrupted A high-priority interrupt can PT0: Priority for Timer 0 interrupt interrupt a low-priority ISR. PX0: Priority for External 0 interrupt A high-priority ISR cannot be interrupted. 1 = Higher Level; 0 = Lower Level If 2 interrupts of the same priority occur simultaneously a fixed polling sequence determines which is serviced first
Ref. I. Scott Mackenzie L Ch Thng
The polling sequence is external 0, Timer 0, external 1, Timer 1, serial 6 port, Timer 2.
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Processing Interrupts
When an interrupt (an event) occurs: The corresponding interrupt flag is set The current instruction completes execution. The PC is saved on the stack. The PC is loaded with the interrupt vector, which is the address of the start of the ISR. The interrupt flag is automatically cleared, except RI &TI (and TF2 & EXF2 for 8052) The ISR executes and takes action in response to the interrupt. The ISR finishes with a RETI (return from interrupt) instruction. This retrieves the old value of the PC from the stack and execution of the main program continues. Ref. I. Scott Mackenzie L Ch Thng 7
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An Example
Assume that Timer 1 interrupt was enabled. When Timer 1 is overflow TF1 is set (automatically by hardware) The current PC is saved on the stack PC 001BH (and the main program is interrupted) The instruction at address 001BH (i.e. the first instruction of the ISR for Timer 1) executes. When the ISR is done, the RETI instruction retrieves the old value of the PC from the stack and the main program continues. Question: What will happen if the Timer 1 is NOT overflow (i.e. NO interrupt signal occur) but TF1 is set by software (i.e. by using SETB TF1)?
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Memory Organization
3-byte instruction
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Furnace Controller
Using interrupts, design an 8051 furnace controller that keeps a building at 20oC 1oC. Temperature sensors are connected to /INT0 and /INT1 and provide /HOT and /COLD signals. The furnace ON/OFF solenoid is connected to P1.7. /HOT = 0 if T > 21oC /COLD = 0 if T < 19oC P1.7 = 1 : Furnace ON P1.7 = 0 : Furnace OFF
P3.2
P3.3
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Furnace Controller
Using interrupts, design an 8051 furnace controller that keeps a building at 20oC 1oC.
ORG 0000H LJMP MAIN ORG 0003H CLR P1.7 RETI ORG 0013H SETB P1.7 RETI ORG 0030H MOV IE,#85H SETB IT0 SETB IT1 SETB P1.7 JB P3.2,SKIP CLR P1.7 SJMP $ END
E0ISR:
E1ISR:
;turn furnace on
MAIN:
SKIP:
;enable external 0 & 1 interrupts ;negative edge triggered for external 0 ;negative edge triggered for external 1 ;turn furnace on ;if T > 21 degrees, ; turn furnace off ;do nothing
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P3.2
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P3.2
50 ms
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P3.2
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References
I. Scott Mackenzie, The 8051 Microcontroller Cc ti liu trn Internet khng trch dn hoc khng ghi tc gi
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