LOW NOISE LOW OFFSET OPERATIONAL AMPLIFIER FOR

NANOPORE-BASED GENE SEQUENCER

By
Zhineng Zhu
B.S. Hefei University of Technology, 1998
A THESIS
Submitted in Partial Fulllment of the
Requirements for the Degree of
Master of Science
(in Electrical Engineering)
The Graduate School
The University of Maine
May, 2007
Advisory Committee:
David E. Kotecki, Associate Professor of Electrical and Computer Engineering,
Advisor
Donald M. Hummels, Professor of Electrical and Computer Engineering
Rosemary Smith, Professor of Electrical and Computer Engineering
LIBRARY RIGHTS STATEMENT
In presenting this thesis in partial fulllment of the requirements for an advanced
degree at The University of Maine, I agree that the Library shall make it freely available
for inspection. I further agree that permission for fair use copying of this thesis for
scholarly purposes may be granted by the Librarian. It is understood that any copying
or publication of this thesis for nancial gain shall not be allowed without my written
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Signature:
Date:
LOW NOISE LOW OFFSET OPERATIONAL AMPLIFIER FOR
NANOPORE-BASED GENE SEQUENCER
By Zhineng Zhu
Thesis Advisor: Dr. David E. Kotecki
An Abstract of the Thesis Presented
in Partial Fulllment of the Requirements for the
Degree of Master of Science
(in Electrical Engineering)
May, 2007
A nanopore-based gene sequencer generates a modulated current signal with the
expected magnitude to be in the range of several pico-amps to a nano-amp, and the
bandwidth up to 10MHz. To detect such a weak signal, an ultra-low noise, low offset,
high precision CMOS operational amplier is designed in a 0.35m CMOS process.
Most of the literature on low noise amplier design emphasizes icker noise
reduction. This research analyzed and optimized a proposed differential pair and opera-
tional amplier, with both the icker noise and the thermal noise minimized simultane-
ously. The size of each MOSFET is optimized, making the input pair the only dominant
noise source. The input pairs bias current is maximized to reduce the thermal noise.
Also this bias current is rationed between the active current source load and the current
mirror load. This ration of bias current makes the optimization of the ampliers noise
performance and DC gain separated, which is often a trade-off in normal operational
amplier design. An operational amplier with the input-referred voltage noise Power
Spectral Density (PSD) of less than 2nV/

Hz for frequencies above 1MHz is realized.

The DC gain of this amplier is up to 120dB. The extra bias current and the cascode
structure also result in a high speed design: the unity gain bandwidth of this operational
amplier is more than 200MHz with 20pF loading, providing a sufcient close loop gain
in the MHz range.
CMOS operational ampliers generally have a higher offset voltage than bipolar
ones. In this design, a digital offset trimming method is studied and used to cover 10mV
input-referred offset. Its effect on noise performance is minimized. This method is
suitable for low voltage and continuous mode applications.
Power Supply Rejection Ratio (PSRR) is an important parameter for the low
noise operational amplier. The PSRR limitation of the taped-output operational am-
plier with common source output stage is analyzed. An operational amplier with
cascode compensation scheme is studied, which shows the potential improvement in
PSRR.
ACKNOWLEDGMENTS
A special thanks to my wife, Ming Luan, for her constant support and encour-
agement.
I would like to express my sincere gratitude to Professor Kotecki for his guidance
and assistance throughout the course of this research work. Thanks to Professor Collins
and Professor Smith for their advices and support. Thanks to Professor Hummels for
the time and reviewing my thesis. Thanks to Steve for his kindly help in the CAD and
chip testing. Thanks to Sanjeev, Alma and Bingxin for their discussions and happy time
in the past two years.
This work was supported by the National Institutes of Health, Bethesda, MD,
under contract 5R01HG003565-03.
ii
TABLE OF CONTENTS
ACKNOWLEDGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
Chapter
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2. Purpose of this Research. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3. Thesis Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Noise in MOSFETs and Basic CMOS Operational Ampliers. . . . . . . . . . . . . . . . . . . . 6
2.1. Noise Sources in MOSFETs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.1. Thermal noise in the channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.2. Flicker noise in the channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.3. Noise of polysilicon gate resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.4. Noise from the distributed substrate resistance . . . . . . . . . . . . . . . . . . . . . 10
2.2. Noise Performance of the CMOS Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. Novel Structure for a Low Noise Operational Amplier using MOSFETs . . . . . . . 18
3.1. Noise Analysis of New Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.1. The noise contribution of the input stage M
1,2
. . . . . . . . . . . . . . . . . . . . . 21
3.1.2. The noise contribution of the active current source load M
3,4
. . . . . 21
3.1.3. The noise contribution of current mirror load M
7,8
. . . . . . . . . . . . . . . . 22
3.1.4. The noise contribution of cascode stage M
5,6
. . . . . . . . . . . . . . . . . . . . . . 22
3.1.5. The noise contribution of current bias MOSFET M
0
. . . . . . . . . . . . . . 23
3.1.6. Total output noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2. Noise Reduction Techniques for this New Structure . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.1. Determination of the input pair type for M
1,2
. . . . . . . . . . . . . . . . . . . . . . 25
3.2.2. Optimization of the bias current I
D2
of the input pair . . . . . . . . . . . . . . 26
3.2.3. Optimization of the sizes and aspect ratios of MOSFETs. . . . . . . . . . 26
3.2.4. Noise performance of the folded-cascode differential pair. . . . . . . . . 29
3.3. DC Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4. AC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.5. Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6. Offset Reduction and Auxiliary Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
iii
4. Testing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.1. Tape-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2. Noise Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3. PCB Board Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.4. Measured Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.4.1. Input Common Mode Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.4.2. Output Voltage Swing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.4.3. Transient Verication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.4.4. AC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5. PSRR of Low Noise Operational Amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.1. Modied Output Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.2. PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1. Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.2. Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
BIOGRAPHY OF THE AUTHOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
iv
LIST OF TABLES
Table 3.1. Optimized devices size of the two-stage operational ampli-
er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 3.2. MOSFETsaspect ratio in the bias circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 4.1. Operational ampliers or their rst stage included in the
chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
v
LIST OF FIGURES
Figure 1.1. Nanopore gene sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 1.2. Typical input-referred voltage noise PSD for a MOSFET . . . . . . . . . . . . . . 4
Figure 2.1. MOSFET noise model: a) Model of thermal noise in the
channel, b) Input-referred voltage noise model . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2.2. Reduction of gate noise through layout, a) single-nger MOS-
FET, b) single-nger MOSFET with contact at both ends, c)
multiple-nger MOSFET and d) multiple-nger MOSFET
with contacts at both ends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2.3. Contribution mechanism of substrate noise to the drain current. . . . . . . . 11
Figure 2.4. a) Differential pair with current mirror load, b) noise model
of a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2.5. Two stage operational amplier with noise sources . . . . . . . . . . . . . . . . . . . . 14
Figure 2.6. Four basic CMOS differential pairs, a) resistive load, b)
diode-connected load, c) active current source load and d)
folded-cascode differential pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3.1. Proposed structure of the low noise differential pair . . . . . . . . . . . . . . . . . . . 19
Figure 3.2. Noise model of differential pair in Figure 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 3.3. Small-signal noise model for input stage M
1,2
. . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3.4. Small-signal noise model for current mirror load M
7,8
. . . . . . . . . . . . . . . . 22
Figure 3.5. Small-signal noise model for the cascode stage M
5,6
. . . . . . . . . . . . . . . . . . 22
Figure 3.6. Small-signal noise model for bias current source M
0
. . . . . . . . . . . . . . . . . . 24
Figure 3.7. Optimum gate length of the input pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 3.8. The noise performace of the circuit in Figure 3.1 . . . . . . . . . . . . . . . . . . . . . . 27
Figure 3.9. The noise performace of the circuit with PMOS as the input
pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 3.10. Modied structure of the operational amplier with an aux-
iliary port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 3.11. Two stage low noise low offset operational amplier . . . . . . . . . . . . . . . . . . 31
Figure 3.12. Small signal model of the circuit in Figure 3.11 . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 3.13. AC performance with parasitic resistances and capacitances. . . . . . . . . . . 34
Figure 3.14. Noise performance with parasitic resistances and capacitances . . . . . . . . 34
vi
Figure 3.15. Self-biasing V
threshold
reference with start-up circuit . . . . . . . . . . . . . . . . . . . 35
Figure 3.16. Schematic of entire bias circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 3.17. Offset tuning scheme with operational amplier in open
loop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 3.18. Offset tuning scheme with operational amplier inverting-
congured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3.19. Setup for auxiliary input design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 3.20. DC sweep of the auxiliary input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 3.21. Noise level with and without auxiliary input . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 3.22. Diagram of offset tuning block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 3.23. Connection between counter and DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 3.24. Timing of offset tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 3.25. Simulation of offset tuning: a) Switching point, b) DAC
output, c) Calibration output, d) Operational amplier output . . . . . . . . . 46
Figure 4.1. Microphotograph of the op amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 4.2. Microphotograph of the chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 4.3. Diagram of the noise measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 4.4. The diagram of the PCB board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 4.5. Bias current generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 4.6. Bias voltage generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 4.7. PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 4.8. PCB Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 4.9. Common mode input range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 4.10. Sinewave input test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 4.11. Measured sine wave input: a)Input=1kHZ, Gain=50, b) In-
put=1kHz, Gain=3, and c)Input=1MHz, Gain=3 . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 4.12. AC gain test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 4.13. AC gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 5.1. AC performance with 20pF load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 5.2. New structure with cascode compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 5.3. PSRR simulation results: a) Positive PSRR, b) Negative
PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
vii
Figure 5.4. Cascode-compensated operational ampliers ACperformance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 5.5. Noise level of the cascode-compensated operational ampli-
er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
viii
CHAPTER 1
Introduction
1.1 Background
A proposed gene sequencer generates a modulated signal based on the tunneling
current through a single strand of DNA passing through a nanopore as illustrated in
Figure1.1. This signal is expected to be in the range of several pico-amps to a nano-
amp, and the bandwidth can be up to 10MHz. This corresponds to a change of 100-
1000 electrons being detected as different base pairs pass through the nanopore. To
detect such a weak signal, an ultra-low noise, low offset, high precision transimpedance
amplier is needed [1].
There are many low noise, high precision ampliers available. Operational am-
pliers designed using bipolar technology have achieved a wide bandwidth and superior
voltage noise performance. For example, the AD8099 from Analog Devices[2] has
about 1nV/

Hz of input voltage noise at 10KHz, and a Gain-Bandwidth Product

(GBP) as high as 3.8GHz. There are also designs which use the lateral pnp transis-
tors provided in digital CMOS processes as the input stage of the amplier to achieve
very-low voltage noise performance[3]. However, a bipolar operational amplier needs
several micro amps of input current to bias the input stage. Such high bias current can in-
troduce several pA/

Hz of input-referred current noise. For example, the AD8099 has

more than 2pA/

Hz noise Power Spectral Density (PSD) at frequency up to 100MHz.

The high input-referred current noise prevents bipolar technology from being used in
the nanopore gene sequencer application.
Commercially available CMOS operational ampliers have higher voltage noise
than bipolar ampliers. For example, the LM6211 from National Semiconductor[4] has
5.5nV/

Hz input voltage noise at 10KHz. Another example is the opa725 from Texas
1
Current
Voltage
Tunnelling Current Silicon Nitride
Silicon
Metal
Current Current
Voltage Voltage
Tunnelling Current Silicon Nitride
Silicon
Metal
Figure 1.1: Nanopore gene sequencing
Instruments[5], which has 10nV/

Hz input voltage noise at 10KHz. These CMOS

operational ampliers have a limited bandwidth. The GBP of the op725 is only 20MHz.
This will not provide sufcient close-loop gain at megahertz frequencies need for the
nanopore application. However, CMOS transistors are voltage controlled devices and
there is almost no bias current needed for the input stage. For both the LM6211 and
opa725, the device input bias current is far less than a nano amp and the input-referred
current noise is less than 10fA/

Hz at 1KHz. Therefore, to amplify a current signal

with a magnitude of several pico amps, a CMOS device is preferred over a bipolar
device.
1.2 Purpose of this Research
There are two noise sources in MOSFET devices: icker noise (below 1MHz)
and thermal noise. In order to distinguish the icker noise from the thermal noise, the
PSD of both types of noise are plotted on the same axis as shown in Figure 1.2. The
corner frequency is where both PSDs are equal to each other. From Figure 1.2, it is
observed that icker noise is inversely proportional to frequency and most signicant
at low frequencies. The thermal noise is independent of frequency and dominant at
high frequencies. In the modern deep-submicron CMOS processes, the icker noise
2
source may dominate the device noise at frequencies well into megahertz range. For the
nanopore gene sequencer application, the bandwidth of interest is between 1MHz and
10MHz. In this frequency range, the thermal noise is dominant, and the icker noise
tail will overlap the thermal noise and increase the noise oor. So for deep sub-micron
CMOS process implementation of low noise operational amplier, both types of noise
are signicant in this bandwidth and both need to be considered simultaneously.
Most of the literature addressing the design of low noise operational ampliers
deal only in the low frequency range and therefore emphasize icker noise reduction
techniques[3][6][7][8][9]. In [3], the BiCMOS process is used and bipolar transistors
are chosen for the input pair to address the high CMOS input-referred icker noise prob-
lem, which is not good for amplifying low current signal. Some dynamic techniques,
like auto-zeroing and chopper stabilization [9], can achieve icker noise levels in CMOS
comparable to bipolar devices. But those methods use switch-capacitor circuits which
introduce switching noise and alias high frequency thermal noise, and therefore achieve
low icker noise at the cost of bandwidth and thermal noise performance. The ther-
mal noise PSD of these dynamic circuits could be far higher than 10nV/

Hz [9] at
frequencies in the MHz range.
In this research, special circuit techniques are exploited to reduce both thermal
and icker noise in a CMOS operational amplier designed as a current detector capable
of operating in the frequency range of 1-10MHz. The unity gain bandwidth and DC gain
are maximized. Since the untrimmed DC offset of a CMOS operational amplier can be
up to 20mV , larger than that of bipolar counterpart, a digital trimming method has been
investigated and implemented to reduce the DC offset voltage. The amplier design is
based on a 0.35m CMOS process operated with a 3.3V supply voltage. This amplier
has applications to other systems requiring low levels of current detection.
3
thermal Noise
corner frequency
flicker Noise
(log scale)
) log( 20
2
n
v
c
f f
thermal Noise
corner frequency
flicker Noise
(log scale)
) log( 20
2
n
v
c
f f
Figure 1.2: Typical input-referred voltage noise PSD for a MOSFET
1.3 Thesis Organization
Chapter 1 introduces the research background and problem being addressed.
Chapter 2 describes the various noise sources associated with MOSFETs. For
each noise source a small-signal model is provided. Then the noise performance is ana-
lyzed for the basic operational ampliers with four different loads: current mirror load,
resistor load, diode-connected load and active current source load. Their limitations for
further noise reduction are analyzed.
Chapter 3 introduces a new circuit topology for minimizing noise. Its noise per-
formance is analyzed and the techniques of noise reduction are described and compared
with those basic operational ampliers presented in Chapter 2 and the folded cascode
differential pair. Because of the relatively large offset voltage associated with CMOS
operational ampliers, a digital offset trimming method is also described in chapter
three.
Chapter 4 describes the noise measurement technique. The test circuit is pro-
vided. Some test results are provided.
Chapter 5 presents a low noise operational amplier with a cascode compensa-
tion scheme, which result in an improved PSRR.
4
Chapter 6 summarizes the conclusions for the design and suggestions for future
work are provided.
5
CHAPTER 2
Noise in MOSFETs and Basic CMOS Operational Ampliers
This chapter provides an overview of noise sources in MOSFETs. The noise
performance of four basic CMOS operational ampliers is analyzed. The limiations of
noise reduction techniques for these basic ampliers are discussed.
2.1 Noise Sources in MOSFETs
The noise sources in MOSFETs include: (a) thermal noise introduced by the
channel; (b) icker noise from the channel[10][11]; (c) thermal noise introduced by the
polysilicon gate resistance[12]; (d) thermal noise introduced by the source/drain resis-
tance and (e) thermal noise instroduced by the distributed substrate resistance[13]. In
the design of a low-noise operational amplier, wide transistors are typically chosen for
the input pair and there are lots of contacts connected to the source and drain, therefore
the thermal noise associated with the source/drain resistances can be neglected[14].
2.1.1 Thermal noise in the channel
Thermal noise is generated by the random motion of carriers in the channel[10]
which introduces uctuations, and therefore noise in the drain current. When a MOS-
FET is biased in the active region, this noise source can be represented by a current
noise generator connected from the drain to source as shown in Figure 2.1(a). The PSD
of this current noise generator is i
2
d,thermal
, which is described by
i
2
d,thermal
= 4kT
2
3
g
m
(2.1)
where k is Boltzmanns constant, T is the temperature in Kelvin, and g
m
is the small-
signal transconductance from the gate to the channel.
6
2
,thermal d
i
2
,thermal d
i
(a)
2
,thermal d
v
2
,thermal d
v
(b)
Figure 2.1: MOSFET noise model: a) Model of thermal noise in the channel, b) Input-
referred voltage noise model
To compare the noise performance of the different circuits, the concept of input-
referred noise is introduced. Input-referred noise is a source at the circuit input which
represents the effect of all noise sources in the circuit. It is ctitious and cannot be
measured in the real circuit. For a MOSFET, the current noise source introduced by the
channel is referred back to the gate by dividing the PSD of the current noise generator
by the square of the MOSFET transconductance g
m
. This results in an input-referred
voltage noise source which is connected in series with the gate as shown in Figure 2.1(b).
Its approximate PSD is given by:
v
2
d,thermal
= 4kT
2
3g
m
. (2.2)
Minimizing the channel thermal noise of a MOSFET is straightforward from the above
formula: the small-signal transconductance must be maximized. This can be achieved
by using a large DC bias current and having a large width to length (W/L) ratio for the
device.
2.1.2 Flicker noise in the channel
Flicker noise has been observed in all kinds of devices, from metal lm resistors
to semiconductor devices and even chemical batteries [15]. The MOSFET has one of
the highest PSD of icker noise among all active devices. Its precise origin has not yet
been identied unequivocally. One popular explanation is that in a MOSFET, current
7
ows near the surface between SiO
2
gate oxide and the crystalline silicon substrate.
The silicon crystal terminates at this Si/SiO
2
interface, producing many unoccupied
dangling energy bonds [14]. As charge carriers move along this surface, they are trapped
and released by those energy bonds randomly and introduce icker noise in the drain
current. The PSD of the noise depends inversely on the frequency and the input-referred
icker noise model[16] is given by:
v
2
i,flicker
(f) =
KF
2C
2
ox
WL
1
f
(2.3)
where
=carrier mobility in the channel;
C
ox
=capacitance per unit area of the gate oxide;
W=channel width;
L=channel length;
f=frequency;
KF=icker noise coefcient which is a process-dependant factor on the order of
10
28
F A and can be different for NMOS and PMOS devices. In the 0.35m process
used in this study, KF for the NMOS device is less than that of PMOS device.
From the Equation 2.3, the PSD of the icker noise is inversely proportional to
the active gate area. Therefore devices with large gate areas are chosen to reduce the
icker noise of the MOSFET. Input-referred icker noise is often modeled by connecting
a noise voltage source in series to the gate of a MOSFET like that shown in Figure 2.1(b).
2.1.3 Noise of polysilicon gate resistance
The thermal noise and icker noise in the channel are the two main sources of
noise in MOSFETs. But for a low-noise amplier design, other noise sources need to
be considered. One of these is the noise introduced by the resistance of the polysilicon
gate. The gate of modern CMOS device is made of polysilicon material often with a
8
silicided surface layer instead of metal. However, the polysilicon gate has its drawback,
in that a polysilicon silicided gate is more resistive than metal [12], and therefore more
noisy. For example, a silicided polysilicon gate sheet resistance is about 7/2. For
a transistor with a W/L ratio of 10/1, the noise density from the gate is approximately
1.077nV/

Hz. The sheet resistance of aluminum is about 0.05/2 and the noise
density of aluminum with the same aspect ratio is about 0.0288nV/

Hz, which is
negligible when compared to that of a polysilicon gate. In low-noise amplier design,
wide transistors are adopted for the input pair and the noise contribution from the gate
can be reduced by proper layout.
When the resistance of the gate is calculated, only effective resistance is consid-
ered. The effective resistance of polysilicon gate is actually less than the multiplication
of the technologys sheet resistance by the aspect ratio of the gate. This is because the
gate resistance of a MOSFET is a distributed resistance[12] and its effective value for
the gate when contacted at only one end as shown in Figure 2.2(a) is given by:
R
G
=
1
3
R
SH,G
W
L
(2.4)
where R
SH,G
is the gate polysilicon sheet resistance with the typical value of 7/2 for
a silicided polysilicon gate. If both ends of the gate are connected together, like that in
Figure 2.2(b), the gate resistance becomes:
R
G
=
1
12
R
SH,G
W
L
(2.5)
The above equation works for a single-nger device. If the device consists of
multiple ngers such as that shown in Figure 2.2(c), then the overall gate resistance is
given by
R
G
=
1
3
R
SH,G
W
L
1
N
(2.6)
9
(a) (b)
(c) (d)
Figure 2.2: Reduction of gate noise through layout, a) single-nger MOSFET, b) single-
nger MOSFET with contact at both ends, c) multiple-nger MOSFET and d) multiple-
nger MOSFET with contacts at both ends
where N is the number of ngers. If all of the ngers are connected at both ends as
shown in Figure 2.2(d), then the factor 1/3 should be replaced by 1/12 such that:
R
G
=
1
12
R
SH,G
W
L
1
N
(2.7)
The noise spectral density associated with the gate resistance is then given by:
v
2
g,thermal
= 4kTR
G
(2.8)
To reduce the thermal noise generated by the gate resistance, the transistor is laid-out in
a multi-nger version with both ends of the gate connected together.
2.1.4 Noise from the distributed substrate resistance
Figure 2.3 shows the noise contribution from the substrate to the drain current
[13]. The substrate has a distributed resistance and therefore generates thermal noise
10
2
,thermal sub
v
sub
R
2
,thermal sub
v
sub
R
Figure 2.3: Contribution mechanism of substrate noise to the drain current
v
2
sub,thermal
that can be approximated by:
v
2
sub,thermal
= 4kTR
sub
(2.9)
where R
sub
is substrate distributed resistance. This noise is amplied by the substrate
transconductance g
mb
and coupled to the drain current through a depletion capacitance,
such that the current noise can be represented by:
i
2
sub,thermal
= 4kTR
sub
g
2
mb
(2.10)
The direct way to reduce the noise fromsubstrate is to decrease g
mb
by increasing
the source bulk bias voltage or using a process with heavily doped substrate.
2.2 Noise Performance of the CMOS Differential Pair
To understand the main noise sources involved in an operational amplier, lets
consider the noise performance of a differential pair with a current mirror load shown in
Figure 2.4. The voltage gain of the amplier, A, measured from the gate of M
1,2
to the
11
1
M
2
M
3
M
4
M
DD
V
SS
I
out
V
1
M
2
M
3
M
4
M
DD
V
SS
I
out
V
(a)
1
M
2
M
3
M
4
M
SS
I
2
1 n
v
2
2 n
v
2
3 n
v
2
4 n
v
DD
V
out
V
1
M
2
M
3
M
4
M
SS
I
2
1 n
v
2
2 n
v
2
3 n
v
2
4 n
v
DD
V
1
M
2
M
3
M
4
M
SS
I
2
1 n
v
2
2 n
v
2
3 n
v
2
4 n
v
DD
V
out
V
(b)
Figure 2.4: a) Differential pair with current mirror load, b) noise model of a)
output V
out
is described by the following equitation:
A = g
m2
r
o
=
2
_
(
n
C
OX
(W/L)
2
)
(
2
+
4
)

I
D2
(2.11)
where is is channel length modulation, is carrier mobility in the channel, C
ox
is the
capacitance per unit are of the gate oxide, W and L are MOSFETs width and length
respectively, I
D2
is the bias current of the input pair M
1
and M
2
.
The gain from the gate of M
3,4
to the output V
out
is g
m4
r
o
, where g
m2
and g
m4
are
transconductance of M
2
and M
4
, respectively, and r
o
is small-signal output resistance.
The output noise is given by:
v
2
no
(f) = 2(g
m2
r
o
)
2
v
2
n2
(f) + 2(g
m4
r
o
)
2
v
2
n4
(f) (2.12)
where v
n2
and v
n4
represent the noise from M
2
and M
4
respectively, which include all
those noise sources discussed above and are referred back to the gate of M
2
and M
4
.
12
This noise v
2
no
can be referred back to the ampliers input by dividing the
squared gain from the ampliers input to its output which results in
v
2
ni
(f) = 2v
2
n2
(f) + 2v
2
n4
(f)
_
g
m4
g
m2
_
2
= 2v
2
n2
(f) + 2v
2
n4
(f)
_
(W/L)
4

p
(W/L)
2

n
_
(2.13)
Assuming C
OX,n
= C
OX,p
= C
OX
, the icker noise and thermal noise of this structure
are given by the following two equations:
v
2
flicker
(f) =
KF
n

n
C
2
OX
W
2
L
2
f
_
1 +
KF
p
KF
n
_
L
2
L
4
_
2
_
(2.14)
v
2
thermal
=
16kT
3
_
2
n
C
OX
(W/L)
2
I
D2
_
_
1 +

p
(W/L)
4

n
(W/L)
2
_
_
(2.15)
where KF
n
is the icker noise coefcient of NMOS, KF
p
is the icker noise coefcient
of PMOS,
n
and
p
are carrier mobilities for both NMOS and PMOS respectively.
From the above equations, we nd that each MOSFET introduces both icker noise and
thermal noise. All CMOS voltage operational ampliers have at least two MOSFETs
as the input pair. The more MOSFETs in the circuit, the more noise is introduced.
From Equation 2.15, it is observed that large bias currents can be used to minimize
thermal noise at the cost of power dissipation and voltage gain A. The large bias current
also results in a large overdrive voltage for transistors M
3
and M
4
. The drain to source
voltage V
DS
of M
3
and M
4
has to be large enough to keep the transistors in the saturation
region. Hence
V
DS
> V
threshold
+V
overdrive
(2.16)
Therefore increasing the bias current reduces the voltage headroom at the output. For
the differential pair with current mirror load, it is clear from this analysis that optimizing
the noise performance involves a trade off with other parameters, including the DC gain
and power.
13
A1 A2
2
1
v
2
2
v
A1 A2 A1 A2
2
1
v
2
2
v
Figure 2.5: Two stage operational amplier with noise sources
Figure 2.5 shows a two stage operational amplier. The rst stage has a gain of
A1 and an output noise v
2
1
; the second stage has a gain of A2 and an output noise v
2
2
.
The total gain of the amplier is A = A
1
A
2
. The total output noise of the amplier is
v
2
total
= v
2
2
+A
2
2
v
2
1
(2.17)
When this noise is referred back to the input port, the input-referred noise is
v
2
i
=
v
2
2
A
2
2
A
2
1
+
1
A
2
1
v
2
1
(2.18)
Since the noise from the rst stage is amplied by the second stage, the noise of rst
stage is more important than that of the second stage. The larger the gain of rst stage
A
1
, the less important the noise contribution of second stage. However, the differential
pair with current mirror load has a disadvantage in that the DC gain is inversely propor-
tional to the bias current. The higher the bias current, the lower the DC gain of the rst
stage, which will make the noise from later stage more pronounced.
In this research, the differential pair with more than 4 cascode stages is not pre-
ferred because we used a 0.35m CMOS process with a working voltage of 3.3V. A
differential pair with more than 4 cascode stages will have a headroom problem. So, the
rst effort is to analyze some other basic differential pairs to see whether any of them
can provide a superior noise performance.
14
Differential pair with a resistive load:
The differential pair with resistive load is shown in Figure 2.6(a). Its input-
referred noise is given by:
v
2
ni
= 8kT
_
2
3g
m
+
1
g
2
m
R
D
_
+
KF
n

n
C
2
OX
W
2
L
2
f
(2.19)
For low-noise design, a large bias current (even to the order of a few milliamps) is
needed and the resistor value has to be chosen to minimize thermal noise. The opera-
tional amplier with a large resistive load can reduce the voltage headroom at the output.
Moreover, the gain of this structure is relatively low, which make the noise of the later
stages a larger issue.
Differential pair with a Diode-connected load:
An Differential pair with a diode-connected load is shown in Figure 2.6(b), and
the noise performance is given by Equation 2.14 and 2.15. This structure has the same
problems as the operational amplier with a resistive load. For low noise operational
amplier design, the bias current should be large and the drain-source voltage also needs
to meet Equation 2.16, which results in a small output voltage swing range. Also such a
structure has a small gain.
Differential pair with an active current source load:
The fully differential pair with active current source load is shown in Figure
2.6(c). The structure has a higher output common mode range than those ampliers dis-
cussed above since its load drain-source voltage only need to meet the requirement of
V
DS
> V
overdrive
, a threshold voltage less than that of the differential pair with a current
15
1
M
2
M
1
R
2
R
DD
V
SS
I
1
M
2
M
1
R
2
R
DD
V
SS
I
(a)
1
M
2
M
3
M
4
M
DD
V
SS
I
1
M
2
M
3
M
4
M
DD
V
SS
I
(b)
CMFB
1
M
2
M
3
M
4
M
DD
V
SS
I
CMFB
1
M
2
M
3
M
4
M
DD
V
SS
I
(c)
1
M 2
M
3
M
4
M
SS
I
5
M
6
M
7
M
8
M
A
B
In
+ In
dd
V
2 b
V
4 b
V
Out
1
M 2
M
3
M
4
M
SS
I
5
M
6
M
7
M
8
M
A
B
In
+ In
dd
V
2 b
V
4 b
V
Out
(d) Folded-cascode differential pair
Figure 2.6: Four basic CMOS differential pairs, a) resistive load, b) diode-connected
load, c) active current source load and d) folded-cascode differential pair
16
mirror load and diode-connected structure. The larger headroom provided by this struc-
ture allows the input pair to sink more DC bias current than the other structures. The
input-referred noise density is also given by Equations 2.14 and 2.15. Therefore it has
the potential of the best noise performance among those introduced before. But such
a structure requires a Common Mode Feedback (CMFB) network to dene the output
common-mode level. Any mismatch in the CMFB circuit can introduce extra noise that
could outbalance the advantage of the fully differential structure.
Folded-cascode differential pair:
Figure 2.6(d) gives the structure of a folded cascode differential pair. This struc-
ture has the limitation of maximizing the input pairs bias current for a low noise design.
M
3
and M
4
source bias current for the input pair M
1
and M2, and the current mirror
load M
7
and M
8
. When the bias current of M
1
and M
2
is maximized, the bias current
of M
3
and M
4
is maximized as well. This will reduce the DC voltage level at the drain
of M
3
and M
4
. This reduced DC voltage level will reduce the voltage headroom at the
drain of M
6
, which is especially true when the length of M
3
and M
4
is chosen larger
than normal in a low noise operational amplier design.
From the above discussion, we can appreciate the trade-offs between noise,
power dissipation, voltage headroom when designing a low noise operational ampli-
er. Chapter three describes a new amplier structure which combines the features of
the fully differential pair with active current source load with an amplier with a current
mirror load. That structure has the potentiality of improved noise performance.
17
CHAPTER 3
Novel Structure for a Low Noise Operational Amplier using
MOSFETs
This chapter proposes a new operationality amplier structure offering the po-
tential of better noise performance. The techniques used to reduce noise are described.
In Chapter 2, the noise limitations of the basic CMOS differential pair structure
were discussed. In this chapter a new structure shown in Figure 3.1 is proposed and
analyzed. This structure combines the merits of a fully differential pair with an active
current source load and an differential pair with a current mirror load. The active current
source M
3
and M
4
can source the maximum current for the input pair to reduce thermal
noise. The current mirror M
7
and M
8
combine with the transconductance of the input
pair to dene the DC gain. A cascode stage, M
5
and M
6
, is introduced for the following
three reason:
1. This cascode stage can reduce the Miller effect, thereby increasing the bandwidth
of the amplier. The input pair (M
1
, M
2
) has a gate-drain parasitic capacitance
C
gd
. If there is no cascode stage, the gain A
miller
from input (M
1
, M
2
) to the drain
of M
7
and M
8
will be larger than 1, that is, A
miller
> 1. The Miller effect will
magnify the parasitic capacitance as A
miller
C
gd
, which will limit the ampliers
bandwidth. With the introduction of cascode stage M
5
and M
6
, the voltage at the
drains of M
1
and M
2
is xed, and the gain from the input to the source of M
5,6
is
reduced and therefore the parasitic capacitance at the gate of M
1,2
is minimized.
2. This cascode stage increase the output resistance looking into the drain of M
6
and
therefore increase the gain of this differential pair.
3. The cascode structure reduces the short channel variation of the input stage. In
describing the channel length modulation using the channel length modulation
18
DD
V
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
SS
I
2 b
V
4 b
V
+
In

In
Out
DD
V
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
SS
I
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
SS
I
2 b
V
4 b
V
+
In

In
Out
Figure 3.1: Proposed structure of the low noise differential pair
parameter , we assume that the small-signal output impedance r
o
is constant.
This is not really true. This output impedance varies with the drain-source voltage.
When the drain-source voltage increases, the pinch-off point will move towards
source region resulting in a wider depletion region around the drain and a higher
r
o
. When the drain-source voltage decreases, a lower value of r
o
results. With the
cascode stage M
5,6
, the drain-source voltage of M
1,2
doesnt experience a large
variation and the small-signal resistance of M
1,2
remains almost constant.
Lets examine how the disadvantages of achieving low noise performance for
those differential pairs discussed in Chapter 2 are avoided in this new structure. In this
new structure, the bias current of the ampliers input pair is rationed between M
3,4
and M
7,8
. M
3,4
is sized to source most of the bias current. For example, if the bias
current of M
1,2
is chosen to be 3mA, I
3,4
of M
3,4
can be 2.85mA and I
7,8
can be set as
0.15mA. The common-mode level at the drain of M
3,4
is dened by the cascode stage
M
5,6
, instead of common mode feedback circuit used in the differential pair with active
current source load. To reduce the thermal noise, the large bias current of 3mA is chosen
19
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
DD
V
0
M
2
1 n
v
2
2 n
v
2
3 n
v
2
4 n
v
2
5 n
v
2
6 n
v
2
7 n
v
2
8 n
v
2
0 n
v
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
DD
V
0
M
2
1 n
v
2
2 n
v
2
3 n
v
2
4 n
v
2
5 n
v
2
6 n
v
2
7 n
v
2
8 n
v
2
0 n
v
Figure 3.2: Noise model of differential pair in Figure 3.1
for the input pair M
1,2
. This current is mainly provided by the active load M
3,4
. The
output of the common-mode level is dened by M
7,8
, which takes a very small current
and provides a wider output swing than that provided by a differential pair with a current
mirror load. In the analysis that follows, we show that this structure has the advantage
of increasing the small-signal gain without deteriorating the noise performance. The
large 3mA bias current results in the input pair M
1,2
with a high aspect ratio and a large
transconductance g
m
, these improves the bandwidth and other performances, like low
icker noise and high DC gain.
3.1 Noise Analysis of New Structure
Figure 3.2 shows the noise model for the structure in Figure 3.1. The noise con-
tribution of each gate is referred back to their own gate input, like the noise contribution
of M
3
, which is represented by v
2
n3
connected in series to its gate. In the following noise
calculation, symmetry is assumed, such that the noise contributions of M
1
, M
3
, M
5
and
M
7
are the same as those of M
2
, M
4
, M
6
and M
8
.
20
4 2
|| r r
1 6
v g
m
2 2 n m
v g
8
r
1
v
2 no
v
2 n
v
4 2
|| r r
1 6
v g
m
2 2 n m
v g
8
r
1
v
2 no
v
2 n
v
Figure 3.3: Small-signal noise model for input stage M
1,2
3.1.1 The noise contribution of the input stage M
1,2
The small-signal model shown in Figure 3.3 is for the calculation of M
2
s noise
contribution, where the parasitic capacitances are omitted for simplicity. From this
model, we nd the output noise from M
2
is:
v
no2
= g
m2
r
8
v
n2
g
m2
r
o
v
n2
(3.1)
where r
o
is the small-signal output resistance of the circuit in Figure 3.1.
3.1.2 The noise contribution of the active current source load M
3,4
The small-signal model to calculate the noise contribution of the active current
source load stage is the same as that in Figure 3.3 with v
n2
and g
m2
replaced with v
n4
and g
m4
. So the output noise from the active current load M
4
is:
v
no4
= g
m4
r
8
v
n4
g
m4
r
o
v
n4
(3.2)
21
8
r
1 6
v g
m
8 8 n m
v g 4 2
|| r r
1
v
8 no
v
8 n
v
8
r
1 6
v g
m
8 8 n m
v g 4 2
|| r r
1
v
8 no
v
8 n
v
Figure 3.4: Small-signal noise model for current mirror load M
7,8
3.1.3 The noise contribution of current mirror load M
7,8
The small signal model for noise contribution of the current mirror load is shown
in Figure 3.4. The noise contribution from M
8
is approximately:
v
no8
= g
m8
r
8
v
n8
g
m8
r
o
v
n8
(3.3)
3.1.4 The noise contribution of cascode stage M
5,6
The cascode stages small-signal noise model is shown in Figure 3.5. Here
v
gs6
= v
n6
v
1
. The output noise from this stage is given by:
4 2
|| r r
1
v
6
r
6 6 gs m
v g
8
r
6 no
v
6 n
v
4 2
|| r r
1
v
6
r
6 6 gs m
v g
8
r
6 no
v
6 n
v
Figure 3.5: Small-signal noise model for the cascode stage M
5,6
22
v
no6
=
g
m6
r
6
r
8
r
6
+r
8
+g
m6
r
6
r
2
v
n6

r
8
r
2
v
n6
(3.4)
where v
n6
is noise contribution of M
6
referred back to its gate. The effective transcon-
ductance of M
6
according to Equation 3.4 is approximately 1/r
2
and is much smaller
than transconductance g
m6
of M
6
and g
m2
of M
2
. The operational ampliers small-
signal output resistance r
o
is close to r
8
. The noise generated by the cascade current
buffers and referred back to the ampliers input is v
ni5,6
=
1
g
m2
ro
r
8
r
2
v
n6

1
g
m2
r
2
v
n6
, and
is much smaller than those generated by input stage, active current and current mirror
loads, therefore it is omitted in the later noise analysis.
3.1.5 The noise contribution of current bias MOSFET M
0
M
0
provides the bias current for the input pair, and noise associated with this
transistor will modulate the bias current. Ideally, the active current source load M
3,4
will not see noise from M
0
since their gate voltage experience no change. So this noise
will run through the input pair M
1,2
and the cascade stage M
5,6
to the current mirror
load M
7,8
. The other observation is that the drains voltage of M
8
will track that of M
7
.
So, the noise from M
0
at the output (drain of M
8
) is equal to the noise at the drain of
M
7
. As a result, the small-signal model shown in Figure 3.6 can be used to analysis the
noise contribution of M
0
. The noise fromM
0
is approximately v
no0
=
g
m0
g
m7
v
n0
, and the
amount of noise referred back to the operational ampliers input is v
ni0
=
1
g
m2
ro
g
m0
g
m7
v
n6
.
This is a very small value when compared with other stages input referred noise due to
the large gain g
m2
r
o
from the input pair to the output.
23
1
v
0 0 n m
v g
0
r
1 1
v g
m
1
r
3
r
2
v
7
1
m
g
0 no
v
5
r
2 5
v g
m
1
v
0 0 n m
v g
0
r
1 1
v g
m
1
r
3
r
2
v
7
1
m
g
0 no
v
5
r
2 5
v g
m
Figure 3.6: Small-signal noise model for bias current source M
0
3.1.6 Total output noise
Combining all those noise models discussed above, the total output noise is given
by
v
2
no
(f) = v
2
no0
(f) + 2v
2
no2
(f) + 2v
2
no4
(f) + 2v
2
no6
(f) + 2v
2
no8
(f)
2(g
m2
r
o
)
2
v
2
n2
(f) + 2(g
m4
r
o
)
2
v
2
n4
(f) + 2(g
m8
r
o
)
2
v
2
n8
(f) (3.5)
The input referred noise is
v
2
ni
(f) = 2v
2
n2
(f) + 2v
2
n4
(f)
_
g
m4
g
m2
_
2
+ 2v
2
n8
_
g
m8
g
m2
_
2
= 2v
2
n2
(f) + 2v
2
n4
(f)
_
(W/L)
4

p
I
D4
(W/L)
2

n
I
D2
_
+ 2v
2
n8
(f)
_
(W/L)
8

p
I
D8
(W/L)
2

n
I
D2
_
(3.6)
The following two equations show the input referred icker noise and thermal noise for
this design respectively:
v
2
flicker
(f) =
KF
n

n
C
2
OX
W
2
L
2
f
_
1 +
KF
p
KF
n
_
L
2
L
4
_
2
I
D4
I
D2
+
KF
p
KF
n
_
L
2
L
8
_
2
I
D8
I
D2
_
(3.7)
v
2
thermal
=
16kT
3
_
2
n
C
OX
(W/L)
2
I
D2
_
_
1 +

p
(W/L)
4
I
D4

n
(W/L)
2
I
D2
+

p
(W/L)
8
I
D8

n
(W/L)
2
I
D2
_
_
(3.8)
24
3.2 Noise Reduction Techniques for this New Structure
From the above two equations, we nd there are three techniques that can be
used to reduce the noise:
1. Determination of the input pair type for M
1,2
2. Optimization of the bias current I
D2
of the input pair
3. Optimization of the sizes and aspect ratios of the MOSFETs
3.2.1 Determination of the input pair type for M
1,2
In this structure, NMOS should be chosen for the input pair M
1,2
for the follow-
ing three reasons:
1. The bandwidth we are dealing with is between 1MHz to 10MHz. Over this band-
width range, thermal noise is often dominant. Selecting a NMOS transistor for
the input pair reduces thermal noise according to Equation 3.8, since NMOS tran-
sistors have a lager mobility
n
(often 2 to 3 times) than PMOS transistors.
2. Flicker noise is still important in this design. In a submicron process, the corner
frequency could be greater than 1MHz. In Figure 1.2 we can see that as the
thermal noise oor is reduced, the corner frequency is increased. The icker
noise tail will overlap with the thermal noise oor. In the 0.35m CMOS process
used, the NMOS icker noise coefcient KF
n
is smaller than that of PMOS icker
noise coefcient KF
p
, which is helpful for achieving lower icker noise according
to Equation 3.7.
3. NMOS transistors have a higher transition frequency f
T
than PMOS transistors,
which help achieve a higher bandwidth.
25
3.2.2 Optimization of the bias current I
D2
of the input pair
To further reduce the thermal noise, the bias current I
D2
of the input pair can be
increased up to several milliamps in this new structure. With such large bias current,
the basic CMOS differential pair like the one with current mirror load can have good
noise performance but at the cost of gain and voltage headroom at the output. However,
for this new structure, the increased bias current does not deteriorate either the gain or
voltage headroom . This is one of the highlights of this new structure which is explained
in the DC gain section 3.3 below.
3.2.3 Optimization of the sizes and aspect ratios of MOSFETs
According to Equation 3.7, choosing a large size (WL)
2
for the input pair, and
making the channel length L of the active load M
3,4
and current mirror M
7,8
larger than
that of input pair M
1,2
can help to reduce the icker noise. The aspect ratio (W/L)
2
is chosen to be larger than (W/L)
4
and (W/L)
8
, so the second and third terms in the
bracket of Equation 3.8 is less than 1. This helps to reduce the thermal noise. After
those choices, we can nd that the input pair contributes most of the noise of both types.
The gate length L
1,2
of the input pair could increase or decrease icker noise
according to Equation 3.7. The optimum value is determined by:
v
2
flicker
L
2
= 0 L
2
=

KF
n
KF
p

_
1
L
2
4
I
D4
I
D2
+

1
L
2
8
I
D8
I
D2
_
(3.9)
When the gate lengths of M
3,4
and M
7,8
are rst chosen to be 2.1m to avoid a large
overdrive voltage, I
D2
and I
D4
chosen to be 3mA and 2.85mA respectively, the optimum
gate length of M
1,2
is found to be 0.7m as shown in Figure 3.7.
The simulated input-referred voltage noise performance of the circuit of Figure
3.1 using a 0.35m CMOS process is shown in Figure 3.8. The total noise level is
simulated to be 1.796nV/

Hz at 1MHz and 1.184nV/

Hz at 10MHz.
26
0 0.5 1 1.5 2 2.5 3
x 10
-6
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
x 10
-19
Input Gate Length (m)
N
o
i
s
e

L
e
v
e
l

(
v
2
)
X: 7e-007
Y: 2.873e-019
Figure 3.7: Optimum gate length of the input pair
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
0
1
2
3
4
5
6
7
8
9
x 10
-7
X: 1e+006
Y: 1.796e-009
Frequency(Hz)
n
o
i
s
e

l
e
v
e
l
(
v
/

(
H
z
)
)
X: 1e+007
Y: 1.184e-009
Figure 3.8: The noise performace of the circuit in Figure 3.1
27
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
0
0.5
1
1.5
2
2.5
3
x 10
-6
X: 1e+007
Y: 2.427e-009
Frequency(Hz)
n
o
i
s
e

l
e
v
e
l
(
v
/
(
H
z
)
)
X: 1e+006
Y: 2.306e-009
Figure 3.9: The noise performace of the circuit with PMOS as the input pair
Figure 3.9 shows the simulated noise level of the same structure when using
PMOS transistors as the input pair. The size, aspect ratio and bias current are all
the same as those in Figure 3.8. From this gure we conclude that the PMOS input
pair shows poorer noise performance: the noise level is 2.306nV/

Hz at 1MHz and
2.427nV/

Hz at 10MHz.
From the previous analysis, we nd that the current mirror load M
7,8
sources
a very small amount of bias current compared with the input pair. Thus,
I
D8
I
D2

1
20
,
I
D4
I
D2
and Equation 3.7 and 3.8 are reduced to:
v
2
flicker
(f)
KF
n

n
C
2
OX
W
2
L
2
f
_
1 +
KF
p
KF
n
_
L
2
L
4
_
2
_
(3.10)
v
2
thermal

16kT
2
_
2
n
C
OX
(W/L)
2
I
D2
_
_
1 +

p
(W/L)
4

n
(W/L)
2
_
_
(3.11)
From these two equations, we can nd that the four MOSFETs (M
1,2,3,4
) contribute most
of the noise in this new structure. Also from these two equations, we can nd that the
noise performance of this new structure is comparable with the differential pair with
active load, but it doesnt need CMFB circuit.
28
3.2.4 Noise performance of the folded-cascode differential pair
Figure 2.6(d) shows a folded-cascode differential pair. It has the same small-
signal model as that of Figure 3.1. And its icker and thermal noise are also represented
by Equation 3.7 and 3.8 respectively. But the new structure has better noise performance
than this folded-cascode differential pair. Assuming I
D2
, I
D4
and I
D8
are the bias cur-
rents of M
2
, M
4
and M
8
in Figure 3.1 respectively, and I
f
D2
, I
f
D4
and I
f
D8
are the bias
currents of M
2
, M
4
and M
8
in Figure 2.6(d) respectively, we nd I
D2
= I
D4
+I
D8
and
I
f
D2
= I
f
D4
I
f
D8
. If we choose I
D2
= I
f
D2
, then I
D4
< I
f
D4
and the drain of M
4
in
Figure 2.6(d) will have smaller DC level than that of the drain of M
4
in Figure 3.1. This
smaller DC level in folded-cascode differential pair results in smaller voltage headroom
at the drain of M
6
. This is especially true when a long gate length is chosen for M
3
and
M
4
and a large bias current is chosen for the input pair in a low noise design. Therefore,
this folded-cascode structure has smaller output swing. Lets think about it in another
way, if we apply the same power to both the circuits in Figure 3.1 and Figure 2.6(d),
which means I
D2
= I
f
D4
> I
f
D2
, then new structure has better noise performance since
its input pair has larger bias current which results in lower thermal noise. Hence, the
new structure offers an improvement over the standard folded cascode structure.
3.3 DC Gain
The small-signal DC gain of the differential pair of Figure 3.1 is given by:
A
1
= g
m2
((g
m6
r
o6
(r
o2
r
o4
r
1a
)) r
o8
) (3.12)
where r
oa
is the small signal resistance of the auxiliary port consisting of M
1a
and M
2a
as shown in Figure 3.10. This auxiliary port is used to reduce offset and its detailed
analysis is given in the offset reduction section 3.6 below. Even though the large bias
current reduces r
o2
and r
o4
, the introduction of the cascode stage increases the output
29
1
M
2
M
3
M
4
M
5
M
6
M
7
M 8
M
DD
V
1 SS
I
2 SS
I
a
M
1
a
M
2
2 b
V
4 b
V
+ In In + Ina
Ina
Out
1
M
2
M
3
M
4
M
5
M
6
M
7
M 8
M
DD
V
1 SS
I
2 SS
I
a
M
1
a
M
2
2 b
V
4 b
V
+ In In + Ina
Ina
Out
Figure 3.10: Modied structure of the operational amplier with an auxiliary port
resistance looking into the drain of M
6
and makes the r
o8
the dominant parameter in
determining the DC gain in Equation 3.12. r
o8
can be approximated by r
o8

1
I
D8
and
can be increased in two ways. First the channel length of the transistors M
7,8
can be
increased to reduce the length modulation parameter which is inversely proportional
to the MOSFET channel length for the rst order approximation [14]. In this design, the
current is radioed between the active load M
3,4
and current mirror M
7,8
. So the second
way to increase r
o8
is to minimize the current I
D8
in M
7,8
. Increasing the bias current I
D2
increases the transconductance g
m2
and therefore DC gain. The active load M
3,4
sources
this extra bias current through the input pair M
1,2
, and therefore the thermal noise is
reduced as described by Equation 3.8. By now it can be observed from the previous
discussion that M
1
, M
2
, M
3
and M
4
are primarily responsible for noise reduction, while
M
1
, M
2
, M
5
, M
6
, M
7
and M
8
are responsible for the DC gain. The DC gain and noise,
which is often a trade-off between noise level and gain in differential pair with current
mirror load, can be optimized independently for this proposed structure .
30
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
DD
V
a
M
1 a
M
2
0
M
a
M
0
9
M
10
M 11
M
12
M
13
M
14
M
R
c
C
Out
1 b
I
2 b
I
3 b
I
4 b
V
5 b
I
+ In In
+
a
In

a
In 1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
DD
V
a
M
1 a
M
2
0
M
a
M
0
9
M
10
M 11
M
12
M
13
M
14
M
R
c
C
Out
1 b
I
2 b
I
3 b
I
4 b
V
5 b
I
+ In In
+
a
In

a
In
Figure 3.11: Two stage low noise low offset operational amplier
3.4 AC Performance
The common source conguration is chosen for the output stage of the opera-
tional amplier. Such a stage can achieve about 20-30 dB of gain. A Miller compen-
sation scheme is chosen to achieve reasonable phase margin. A two stage low noise
operational amplier incorporating the new structure for the differential pair is shown in
Figure 3.11. Sizes of the transistors, and the Miller compensation resistor and capacitor
are provided in Table 3.1.
M
1
816/0.7 M
6
66/0.7 M
0a
66/0.7 M
13
220/0.35
M
2
816/0.7 M
7
132/2.1 M
9
385/0.7 M
14
198/2.1
M
3
198/2.1 M
8
132/2.1 M
10
220/0.35 R 940
M
4
198/2.1 M
1a
105/0.7 M
11
408/0.7 C
c
5pF
M
5
66/0.7 M
1b
105/0.7 M
12
66/0.7
Table 3.1: Optimized devices size of the two-stage operational amplier
31
1
R
1
C
c
C
6
r
1 6
v g
m
2 9
v g
m
3
R
3
C
R
2
2 i m
v g
2
R
2
C
2
1 i m
v g
1
v
2
v
out
v
1
R
1
C
c
C
6
r
1 6
v g
m
6
r
1 6
v g
m
2 9
v g
m
3
R
3
C
R
2
2 i m
v g
2
R
2
C
2
1 i m
v g
1
v
2
v
out
v
Figure 3.12: Small signal model of the circuit in Figure 3.11
The small-signal model for the circuit in Figure 3.11 is given in Figure 3.12:
Here R
1
= r
2a
r
2
r
4
C
1
= C
gd2
+C
gd4
+C
gd2a
+C
gs6
R
2
= r
8
C
2
= C
gd6
+C
gd8
+C
gs9
R
3
= r
9
r
10
C
3
= C
gd9
+C
gd10
Analysis of ac small-signal model, after considerable algebra work and discard-
ing some minor parameters such as C
1
and C
2
, results in the following equation:
v
out
v
i
=
g
m2
g
m9
R
2
R
3
sg
m2
R
2
R
3
C
c
(1 g
m9
R)
1 +s(RC
c
+R
3
C
3
+g
m9
R
2
R
3
C
c
) +s
2
RR
3
C
c
C
3
(3.13)
With the assumption that the second pole is far larger than the dominant pole, the dom-
inant pole of above equation can be approximated by:
p
1
=
1
g
m9
R
2
R
3
C
c
. (3.14)
Since the DC gain of this amplier is:
A(0) = A
1
A
2
= (g
m2
((g
m6
r
o6
(r
o2
r
o4
r
2a
)) r
o8
)) g
m9
R
3
= g
m2
R
2
g
m9
R
3
(3.15)
32
and the unity gain bandwidth is still given by GBP = A(0)|p
1
| =
g
m2
Cc
The second dominant pole is:
p
2

g
m9
R
2
RC
3
. (3.16)
and the zero is:
z =
g
m9
C
c
(1 g
m9
R)
. (3.17)
For unity-gain stability, the magnitude of the second dominant pole should be greater
than the GBP such that:
|p
2
|
g
m9
R
2
RC
3
> GBP =
g
m2
C
c
. (3.18)
Therefore
C
c
>
g
m2
RC
3
g
m9
R
2
. (3.19)
From Equations 3.16 and 3.17, we can nd that the zero-nulling resistor R can control
the zero and second dominant pole positions and therefore change the phase margin.
One observation from Equation 3.19 is that in this low noise operational amplier de-
sign, the input transconductance can be larger than the transconductance of the output
driver. If R is chosen close to 1/g
m9
, then p
2
is maximized and stability is achieved with
a minimum C
c
.
For the values given in Table 3.1, the circuit of Figure 3.11 was simulated. The
simulated AC results and noise performance including parasitic resistances and capaci-
tances introduced by the layout are shown in Figure 3.13 and Figure 3.14 respectively.
Simulation results in Figure 3.13 show the DC gain of the design is around 120dB with
unity-gain bandwidth up to 380MHz. The phase margin is around 11
o
. The simulated
total input-referred noise level is lower than 2nV/

Hz from 1MHz to 10MHz.

33
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
10
-100
-50
0
50
100
Frequency(Hz)
G
a
i
n
(
d
B
)
X: 3.802e+008
Y: -0.1363
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
10
-400
-300
-200
-100
0
Frequency(Hz)
P
h
a
s
e
X: 3.802e+008
Y: -169.4
Figure 3.13: AC performance with parasitic resistances and capacitances
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
x 10
-6
X: 1e+006
Y: 1.939e-009
Frequency(Hz)
n
o
i
s
e

l
e
v
e
l

(
v
/

(
H
z
)
)
X: 1e+007
Y: 1.297e-009
Figure 3.14: Noise performance with parasitic resistances and capacitances
34
6 b
M
5 b
M
7 b
M
1 b
M
2 b
M
3 b
M 4 b
M
R
6 b
M
5 b
M
7 b
M
1 b
M
2 b
M
3 b
M 4 b
M
R
Figure 3.15: Self-biasing V
threshold
reference with start-up circuit
3.5 Bias Circuit
The bias network is an important component in the low noise amplier design.
The bias core is shown in Figure 3.15. The advantage of this bias circuit is that the
currents through M
b3,b4
are insensitive to the supply voltage to the rst order, which
means such circuit has superior PSRR performance. A combination of current- and
voltage-routing techniques [10] is used to reduce the mismatch and supply resistance.
The MOSFETs M
b5,b6,b7
consist of a start-up circuit with M
b5
being a long channel
device.
The entire bias network is shown in Figure 3.16. Cascode stages are imple-
mented to increase the output resistance and the values of the transistors are given in
Table 3.2.
3.6 Offset Reduction and Auxiliary Port
In general CMOS operational ampliers exhibit higher input offset voltage than
their BJT counterparts. The photolithography, ion implantation, etching and other process-
related factors can cause a mismatch in the threshold voltage V
t
and gain factor between
35
7 b
M
5 b
M
6 b
M
1 b
M
2 b
M
3 b
M
4 b
M
8 b
M
9 b
M
10 b
M
11 b
M
12 b
M
13 b
M
14 b
M
15 b
M
16 b
M
17 b
M
18 b
M
19 b
M
20 b
M
21 b
M
22 b
M
23 b
M
1 b
V
2 b
V
3 b
V
5 b
V
R
DD
V
7 b
M
5 b
M
6 b
M
1 b
M
2 b
M
3 b
M
4 b
M
8 b
M
9 b
M
10 b
M
11 b
M
12 b
M
13 b
M
14 b
M
15 b
M
16 b
M
17 b
M
18 b
M
19 b
M
20 b
M
21 b
M
22 b
M
23 b
M
1 b
V
2 b
V
3 b
V
5 b
V
R
DD
V
Figure 3.16: Schematic of entire bias circuit
M
b1
220/0.7 M
b7
2.2/2.1 M
b13
220/0.7 M
b19
72/0.7
M
b2
220/0.7 M
b8
220/0.7 M
b14
660/0.7 M
b20
22/2.1
M
b3
220/0.7 M
b9
55/2.1 M
b15
660/0.7 M
b21
110/0.7
M
b4
220/0.7 M
b10
690/0.7 M
b16
22/2.1 M
b22
310/0.7
M
b5
22/0.7 M
b11
690/0.7 M
b17
110/0.7 M
b23
310/0.7
M
b6
2.2/14 M
b12
44/2.1 M
b18
72/0.7 R 940
Table 3.2: MOSFETsaspect ratio in the bias circuit
36
the input pairs and generate a random voltage. Typically, a CMOS operational ampli-
ers offset can be up to 20mV. In this design, there have been many efforts made to
reduce the ampliers noise level. These efforts are inherently helpful in minimizing the
operational ampliers random offset.
Because of the high gain of the rst stage, the offset introduced by the second
stage is negligible. So, the input-referred random offset for the operational amplier
shown in Figure 3.11 is approximated by [10]:
V
OS
V
t1,2
+V
t3,4
g
m4
g
m2
+V
t7,8
g
m8
g
m2
+
V
ov1,2
2
_
(
W
L
)
1,2
(
W
L
)
1,2
+
(
W
L
)
3,4
(
W
L
)
3,4
+
(
W
L
)
7,8
(
W
L
)
7,8
_
(3.20)
The rst term in Equation 3.20 is due to the input pairs threshold mismatch. The second
term is due to the active current source load threshold mismatch referred back to the in-
put of amplier. Having g
m4
smaller than g
m2
to reduce noise is also helpful in reducing
this second term. The third term is negligible because of g
m8
is designed far less than
g
m2
fr noise performance. In this design, the large aspect ratio of the input pair achieves
a small overdrive voltage V
ov1,2
and therefore helps to reduce the last term. The standard
deviation of the difference between the input pairs threshold is used as a measure of the
mismatch. This is dened as [17]

Vt
=
A
Vt

WL
(3.21)
and the mismatch in the current gain factor is given by [17]:

=
A

WL
(3.22)
where A
Vt
, A

T
are process-dependent constants and A
Vt
decreases with gate oxide
thickness. Fromthe above equations, it is observed that the large gate area used to reduce
the icker noise can also reduce the threshold and gain factor mismatches, and therefore
37
the offset between the input pair. This can be intuitively understood if we consider the
icker noise as a low frequency signal and the offset also as a low frequency signal.
The efforts to reduce icker noise will also reduce offset. So, the mechanisms to reduce
noise are consistent with reduction of the input-referred offset.
Even though the input-referred random offset of this design is theoretically low,
it still deserves further reduction because of the systematic offset and the remaining ran-
dom offset. Conventional offset reduction techniques such as on-wafer trimming used
in bipolar technology is very expensive and prevents real-time trimming. Some state-of-
art dynamic offset reduction schemes such as auto-zeroing [9] and chopper stabilization
[18] methods can reduce the offset down to several microvolts, but they often alias high-
frequency noise down to the base band. Moreover, there is unavoidable charge injection
and clock feed through. These issues limit dynamic offset reduction schemes to low
frequency applications. Some other methods, such as the ping-pong amplier [19], use
cascode transistors as a load, and adjust the current running through those cascode tran-
sistors. This method will reduce the voltage headroom at the output of the rst stage and
is problematic in low voltage designs.
In this design, a digital trimming method for offset reduction is introduced and
analyzed. Such a method can provide offset trimming at power-up or upon request. A
schematic representation [19] of this method is shown in Figure 3.17. During the offset
calibration phase, the operational ampliers inputs are connected to a common voltage
source. The counter keeps counting and a new controlling voltage is applied to the
auxiliary port of the operational amplier. Then, the operational amplier generates a
new output which is compared with a reference voltage. The counter will stop counting
when comparator experiences a zero crossing. When the output of comparator changes
its state, the calibration phase is concluded and the output of the DAC is set to the
desired controll voltage. In Figure 3.17, the operational amplier is in the open loop
mode. When the open loop DC gain of the amplier is very large, such a conguration
38
Comparator
DAC
CO=1?
V
c
Cross Zero?
Counter
12-bit
V
ref
CO
yes
Stop
Op Amp
V
OS
Comparator Comparator
DAC
CO=1?
V
c
Cross Zero?
Counter
12-bit
V
ref
CO
yes
Stop
Op Amp
V
OS
Op Amp
V
OS
Figure 3.17: Offset tuning scheme with operational amplier in open loop mode
is not very efcient to reduce the offset to make the output xed within the supply rail
unless using the big size auxiliary input pair at the cost of more noise. But in practical
application, the operational ampliers are seldom used in an open-loop conguration.
They are often used in an inverting, non-inverting or transimpedance conguration with
a gain much less than open-loop DC gain. An example of inverting conguration is
shown in Figure 3.18. The amplier can keep inverting, non-inverting or transimpedance
conguration when offset trimming is taking place.
For this offset calibration, an auxiliary port in introduced to this operational
amplier [20] like that shown in Figure 3.10. The size and bias current of the auxiliary
port are chosen to cover a 10mV input referred offset without adding too much extra
noise. The auxiliary input size and offset adjustable range are determined by the setup
shown in Figure 3.19. The operational ampliers primary port is in the unity-gain
conguration. A 10mV offset is applied to the operational ampliers positive input of
the primary port. The desired DC output level is 0V. The voltage at the positive input of
auxiliary port is biased at a DClevel and the negative input is DCswept from 0V to 3.3V.
The simulation result in Figure 3.20 shows that the output experiences a change from
39
12-bit
Op Amp
Comparator
DAC
CO=1?
V
c
Cross Zero?
Counter
V
OS
V
ref
CO yes
Stop
12-bit
Op Amp
Comparator Comparator
DAC
CO=1?
V
c
Cross Zero?
Counter
V
OS
V
ref
CO yes
Stop
Figure 3.18: Offset tuning scheme with operational amplier inverting-congured
V
OS
V
sweep
V
ref
V
Out
V
OS
V
sweep
V
ref
V
Out
Figure 3.19: Setup for auxiliary input design
40
0 0.5 1 1.5 2 2.5 3
0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
0.02
O
u
t
p
u
t
(
V
)
Input(V)
Output Sweep
Desired Output Level
Figure 3.20: DC sweep of the auxiliary input
20mV down to less than desired DC output level (0V), which means the chosen size of
auxiliary port can cover the selected offset range. The bias current in this auxiliary port
is 10 times less than that of primary port; the aspect ratio is 8 times less than that in
the primary port. Figure 3.21 shows the pre-layout noise performance of the circuits in
Figure 3.1 and Figure 3.10 with the auxiliary port, just a little difference in noise level.
The detailed offset tuning and zero-crossing detection circuit is shown in Figure
3.22. In this gure, there is a DAC, which consists of a segmented wide-swing 12-
bit R-2R conguration [21] shown in Figure 3.23. The 12-bit counters upper 5 bits
are thermo-coded. This makes the accuracy requirement for 1/2 LSB DNL in a 12-bit
converter to be set by 7-bit matching instead of 12-bit. Such segmentation is also helpful
in reducing the glitch area associated with the changing DAC output. Since the output
of DAC drives a capacitive load, the operational amplier as a buffer in this DAC is
omitted.
CNT includes a positive edge triggered 2-bit counter, the counters two output
bits are anded to give C1 output. Therefore receiving three clocks after reset, C1 is set
to

1

to enable DAC and disable itself. During this three-clock period D2, which is two
D ip-ops connected in series, stores the comparators initial status and XOR becomes
41
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
0
1
2
3
4
5
6
7
8
9
x 10
-7
Frequency(Hz)
n
o
i
s
e

l
e
v
e
l
(
v
/

(
H
z
)
)
Wit h Auxi liary Port
Wit hout Auxil iary Port
Figure 3.21: Noise level with and without auxiliary input
CO
Op Amp
Comparator
1 D
1 D
DAC
V
ref+
V
ref-
Clr
Clk
V
c
S
CAL
Out
A1
XOR
D
2
Clkin
D
1
Clk
Clr
Clk
D
1
Clr
Clk
C
1
CNT
Clr
Clk
A
2
En
I1
I2
I3
I4
CO
Op Amp Op Amp
Comparator Comparator
1 D
1 D
1 D1 D
1 D1 D
DAC
V
ref+
V
ref-
Clr
Clk
V
c
DAC
V
ref+
V
ref-
Clr
Clk
V
c
S
CAL
Out
A1 A1
XOR
D
2
Clkin
D
1
Clk
Clkin
D
1
Clk
Clr
Clk
D
1
Clr
Clk
D
1
Clr
Clk
Clr
Clk
C
1
CNT
Clr
Clk
A
2
En
I1
I2
I3
I4
Figure 3.22: Diagram of offset tuning block
42
5
-
b
i
t

C
o
u
n
t
e
r
7
-
b
i
t

C
o
u
n
t
e
r
T
h
e
r
m
o
-
D
e
c
o
d
e
r
3
1
-
b
i
t

R
e
g
i
s
t
e
r
7
-
b
i
t

R
e
g
i
s
t
e
rR
e
s
i
s
t
o
r

S
t
r
i
n
g
31 5
7
38
5
-
b
i
t

C
o
u
n
t
e
r
7
-
b
i
t

C
o
u
n
t
e
r
T
h
e
r
m
o
-
D
e
c
o
d
e
r
3
1
-
b
i
t

R
e
g
i
s
t
e
r
7
-
b
i
t

R
e
g
i
s
t
e
rR
e
s
i
s
t
o
r

S
t
r
i
n
g
31 5
7
38
Figure 3.23: Connection between counter and DAC

. If CLK[n-1] comparators output changes from

1

to

0

, D2 is still

1

and XOR
gates output becomes

1

. Therefore, there is zero crossing for comparator within two

continuous clocks when the XOR equals

1

. D1 is a one-bit D ip-op, which turns off

the clock signal

Clkin

when offset tuning phase is nished to reduce switching noise

in the chip. Also D1 is used to switch the operational ampliers output into or out of
the calibration circuit. The Schmidt Trigger is used to reduce the switching noise in the
comparators output.
The timing for the offset tuning is shown in Figure 3.24. At the beginning, a

Clr

signal (command to start offset tuning) is activated, all the registers are cleared,
and DAC is disabled. The period of

Clr

should be long enough for the operational

amplier and comparators output to become stable. In this gure, the initial output of
the operational amplier is larger than the reference voltage and the comparators output
is

1

. At the time 1, the reset signal is released and the counter CNT begins to count.
The comparators initial status is clocked into D2 at time 2 and the output of the XOR
gate is

0

. This

0

will be kept until comparator changes its output status by having a

zero crossing. At time 3, which is the third clock edge after the reset signal, the counters
output is set to

1

to disable the counter and enable the DAC. The DAC starts to increase
its output. When the DAC increases its output, the operational amplier generates a
new output, which is compared with a reference DC voltage through comparator. This
43
process continues until at time 4, the operational ampliers output becomes less than
the reference voltage. At this time, the comparator changes its output to low and D2
is still comparators previous status, which makes the XOR change its status to logical

to indicate a zero-crossing. Then A1 is set to

0

to disable the DAC and conclude

the offset tuning process. At the time 5, D1 changes to

1

to switch the operational

ampliers output back to the circuit and disable

Clkin

.
Figure 4.11 shows the simulation of the offset tuning. In this simulation, the
operational amplier works with a single supply voltage with the midpoint voltage at
1.65V. Figure 3.25(a) shows the timing of signal D1 in Figure 3.22. It shows that the
calibration phase is concluded at the time of 0.2805s. In Figure 3.25(b), we can see that
the DAC keeps increasing its output until at the time 0.2805s when the output of the
operational amplier becomes less than the reference voltage. Figure 3.25(c) shows the
waveform of signal

CAL

in Figure 3.22. This waveform from 0s to 0.2805s resembles

the waveform in Figure 3.20. After the calibration phase, signal

CAL

becomes oat-
ing, and is no longer used. Figure 3.25(d) shows the waveform

Out

in Figure 3.22.
The signal

Out

is oating during the time from 0s to 0.2805s. After the time 0.2805s,
the operational ampliers output is switched back to the

Out

signal and its value is

close to 1.65V as shown in Figure 3.25(d).
44
C
l
k
_
i
n
C
l
k
C
l
r
C
1
A
1
A
1
D
1
D
2
SX
O
R
C
O
V
c
1
2
3
4
5
O
p

A
m
p
C
l
k
_
i
n
C
l
k
_
i
n
C
l
k
C
l
k
C
l
r
C
l
r
C
1
C
1
A
1
A
1
A
1
A
1
D
1
D
1
D
2
D
2
SSX
O
R
X
O
R
C
O
C
O
V
c
V
c
1
2
3
4
5
O
p

A
m
p
1
2
3
4
5
O
p

A
m
p
F
i
g
u
r
e
3
.
2
4
:
T
i
m
i
n
g
o
f
o
f
f
s
e
t
t
u
n
i
n
g
45
0.05 0.1 0.15 0.2 0.25 0.3 0.35
0.5
0
0.5
1
1.5
2
2.5
3
3.5
X: 0.2805
Y: 5.055e010
time(S)
V
o
lt
a
g
e
(
V
)
Switching Point
(a)
0.05 0.1 0.15 0.2 0.25 0.3 0.35
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
time(S)
V
o
lt
a
g
e
(
V
)
DAC Output
X: 0.2805
Y: 1.646
(b)
0.05 0.1 0.15 0.2 0.25 0.3 0.35
1.5
1.55
1.6
1.65
1.7
1.75
1.8
1.85
1.9
X: 0.2805
Y: 1.65
time(S)
V
o
lt
a
g
e
(
V
)
Calibrated Output
(c)
0.05 0.1 0.15 0.2 0.25 0.3 0.35
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
X: 0.2999
Y: 1.65
time(S)
V
o
lt
a
g
e
(
V
)
OpAmp Output
(d)
Figure 3.25: Simulation of offset tuning: a) Switching point, b) DAC output, c) Calibra-
tion output, d) Operational amplier output
46
CHAPTER 4
Testing Results
4.1 Tape-out
Figure 4.1 shows the microphotograph of the designed operational amplier in
Figure 3.11 with the bias network. Its area is about 0.04mm
2
The taped-out design of
the chip is shown in Figure 4.2. For testing exibility, there are 6 versions of designs on
the chip, with or without internal biases. They are summarized in Table 4.1.
4.2 Noise Measurement
A typical setup for noise measurement is to apply a sine wave to the circuit under
test (CUT), the output of CUT is amplied and measured by a spectrum analyzer. For
such scheme, a sine-wave source is required. Also the radiated signals are easy to couple
into the test system through ground loop and introduce error. For this design, a noise
measurement scheme shown in Figure 4.3 is often used. The advantage of this setup is
that there is no externally input signal applied to the CUT when measuring noise and
the operational ampliers noise is directly amplied and measured. So all the CUT can
be put into a metal box to reduce the coupling of externally radiated signals.
In the test setup shown in Figure 4.3, the designed operational amplier is unity
gain congured [22] and its noise voltage is amplied by the low noise amplier. The
amplied noise is measured by a network/spectrum analyzer in this case an HP4195A.
There is a transfer function dened from the positive input of the operational amplier
to the input of the HP4195A, which can be measured by applying a reference signal
from the HP4195A, through switch S2 to the positive input of the operational amplier.
By dividing the measured output noise spectral density by this transfer function, the
input-referred noise spectral density can be obtained.
47
Figure 4.1: Microphotograph of the op amp
Figure 4.2: Microphotograph of the chip
48
I
b1
I
b2
I
b3
I
b5
V
b4
OpAmp1 OpAmp

external

external external external external

OpAmp2 Firststage

external external external external

OpAmp3 OpAmp internal

internal internal internal external

OpAmp4 OpAmp internal internal internal external external
OpAmp5 Firststage external external external external
OpAmp6 Firststage internal internal internal external
*schematic in Figure 3.11
** external bias
***schematic in Figure 3.10
**** internal bias
Table 4.1: Operational ampliers or their rst stage included in the chip
A HP4195
1 S
2 S
DUT LNA
A HP4195
1 S
2 S
DUT LNA
Figure 4.3: Diagram of the noise measurement
49
4.3 PCB Board Design
Figure 4.4 shows the block diagram of the PCB board, which was designed to
evaluate the chip. There are three supplies on this board: 16V, -16V and -6V. Those
three supplies can be generated through batteries since batteries have lower noise. The
low noise regulator LT1962 is used to generate 3.3V nominal working supply voltage for
the chip. As discussed above, there are circuits to generate the external current sources
to bias the operational amplier or the rst stage in the chip. Figure 4.5 shows how
the precision bias currents are generated. REF102 is a precision voltage source, which
forces the voltage across R to be constant and generates the necessary current. For bias
voltage V
b4
, the bias circuit is just a potentiometer since V
b4
is directly connected to
the CMOS gate. It is the same for In
a
+ and In
a
of the auxiliary input. They are
connected to the potentiometers to adjust the operational ampliers offset voltage. The
outputs of all those operational ampliers in the chip can be connected to the low noise
amplier through switch S for the noise measurement. The circuit shown in Figure 4.6
is to generate reference voltages. The signals V ref+ and V ref are two reference
signals for the internal DAC. The +/-5V voltage regulators generate working voltage for
some active devices on the board. Figure 4.7 shows the layout of designed PCB board,
while Figure 4.8 shows the picture of the fabricated board.
4.4 Measured Results
4.4.1 Input Common Mode Range
Figure 4.9 shows the measured and simulated input common mode range. The
measured results are in good agreement with simulations except where the input changes
from 0V to 1.1V, within which the measured results show 0.6V DC voltage. But this
50
Regulator
Bias
Current
Generator
Voltage
Reference
Generator
5V Regulator
-5V Regulator
CUT
3.3V
I
b1
I
b2
I
b3
I
b5
Out1
Out2
Out3
Out4
Out6
A
S
Out5
16V
-16V
-6V
V
b4
In
a
+ In
a
+
16V 16V 16V
Vref+
Vref+
Voltage
Reference
Generator
13V 2V -1V
Regulator
Bias
Current
Generator
Voltage
Reference
Generator
5V Regulator
-5V Regulator
CUT
3.3V
I
b1
I
b2
I
b3
I
b5
Out1
Out2
Out3
Out4
Out6
A
S
Out5
16V
-16V
-6V
V
b4
In
a
+ In
a
+
16V 16V 16V
Vref+
Vref+
Voltage
Reference
Generator
13V 2V -1V
Regulator
Bias
Current
Generator
Voltage
Reference
Generator
5V Regulator
-5V Regulator
CUT
3.3V
I
b1
I
b2
I
b3
I
b5
Out1
Out2
Out3
Out4
Out6
A A
S
Out5
16V
-16V
-6V
16V
-16V
-6V
V
b4
In
a
+ In
a
+
16V 16V 16V
V
b4
In
a
+ In
a
+
16V 16V 16V
Vref+
Vref+
Voltage
Reference
Generator
13V 2V -1V
Figure 4.4: The diagram of the PCB board
REF102
OP193
Load
16V
R
I
out
6
4
REF102
OP193 OP193
Load
16V
R
I
out
6
4
Figure 4.5: Bias current generator
Op193 Op193
Figure 4.6: Bias voltage generator
51
Figure 4.7: PCB Layout
52
Figure 4.8: PCB Board
53
0 0.5 1 1.5 2 2.5 3 3.5
0
0.5
1
1.5
2
2.5
3
3.5
Voltage
V
o
l
t
a
g
e
DC Sweep
Tested Result
Simulated Result
Figure 4.9: Common mode input range
is not important since the operational ampliers input common mode range is approx-
imately from 1.2V to 3.1V, within which the measured result matches the simulated
results very well.
4.4.2 Output Voltage Swing
The output voltage swing range was measured and found to agree with the sim-
ulation results. The output voltage range was measured to be from 38mV to 3.2V.
4.4.3 Transient Verication
For this taped-out operational amplier, oscillation behavior are seen in the mea-
sured output when the operational amplier is operated in a unity-gain conguration.
There are various possibilities for this. First, for the high speed design, also for stability
reason, it is better to use minimum channel length for the operational ampliers output
stage to maximize its transconductance and minimize its small-signal output resistance
and phase margin. But for the design which is taped-out, the channel length of M
9
in
54
R
1
R
2
Out
In
R
1
R
2
Out
In
Figure 4.10: Sinewave input test setup
Figure 3.11 is 0.7m instead of 0.35m. From the post-layout simulation, we can nd
that the phase margin is only 11
o
. Second, the simulation with package model was not
performed in this taped-out design. The parasitic parameters of the package, like induc-
tance and capacitance which could further reduce the phase margin, were not taken into
consideration.
Even though it is not unity-gain stable, the operational amplier shows some cor-
rect amplication behavior when inverting-congured with some gain. Figure 4.11(a) to
4.11(c) show some arbitrarily selected frequencies and gains for a conguration shown
in Figure 4.10. For Figure 4.11(a), the input signal is 1kHz sine wave, R1=2k and
R2=100k, oscilloscope shows a gain of 50 and a phase difference of 180
o
between the
input and the output. For Figure 4.11(b), input is still 1kHz sine wave, R1 and R2 are
set to be 10k and 30k respectively. The output sine wave shows a gain of 3 with a
180
o
of phase difference from the input. In Figure 4.11(c), the frequency of input signal
is 1MHz and the gain is 3 with R1=10k and R2=30k.
4.4.4 AC Performance
AC gain measurement setup is shown in Figure 4.12. The voltage V
A
at the point
A is too small to be directly measured. The way to work around this is to measure the
voltage V
B
at the point B, and V
A
is calculated according to V
A
= V
B

_
R
0
R
0
+R
3
_
. AC
gain at a given frequency is A =
Out
V
A
. The preliminary measured AC gain is shown in
55
(a) (b)
(c)
Figure 4.11: Measured sine wave input: a)Input=1kHZ, Gain=50, b) Input=1kHz,
Gain=3, and c)Input=1MHz, Gain=3
56
R
1
R
2
R
3
R
0
Out
A
B
In
R
1
R
2
R
3
R
0
Out
A
B
In
Figure 4.12: AC gain test setup
Figure 4.13. The measured gain around 100Hz is around 120dB, a little bit higher than
the simulated result. The measured result shows a peak around several kHz. This is
probably due to parasitic inductance and capacitance on PCB board and package, plus
limited phase margin of operational amplier itself. The measured AC gain beyond
8MHz is not accurate. This is probably also because of the poor layout of PCB board
and AC test scheme.
57
10
0
10
2
10
4
10
6
10
8
10
10
100
50
0
50
100
X: 3.802e+008
Y: 0.1363
Frequency(Hz)
G
a
i
n
(
d
B
)
Simulated Result
Tested Result
10
0
10
2
10
4
10
6
10
8
10
10
400
300
200
100
0
X: 3.802e+008
Y: 169.4
Frequency(Hz)
P
h
a
s
e
Figure 4.13: AC gain
58
CHAPTER 5
PSRR of Low Noise Operational Amplier
5.1 Modied Output Stage
In the rst design, the unity gain phase margin was margined at 11
o
. This is
because that the size of the output stage was not optimized. The length of M
9
in Figure
3.11 was 0.7m, instead of 0.35m, which result in a large small-signal output resis-
tance and small phase margin. To overcome this problem, the size of the output stage of
the operational amplier was redesigned and the length of M
9
was set to 0.35m. The
simulated AC performance with 20pF load is shown in Figure 5.1. From this gure, we
can nd the phase margin is larger than 20
o
with 20pF load. The noise performance is
almost the same.
5.2 PSRR
The power supply rejection ratio (PSRR) hasnt been considered in the anal-
ysis so far. Low noise operational ampliers should have a high PSRR to reject the
disturbance on the power supply line, which is especially important for a single-ended
amplier. For an operational amplier with a common source output, like that in Figure
3.11, the positive PSRR begins to roll off at a relatively low frequency. This can be
explained in the following way. Transistor M
9
is biased through M
10
. Assuming there
is no disturbance on the negative supply line, then the current in M
10
wont change. If
there is ripple on the positive power supply, this ripple will also appears on the gate of
M
9
to keep its bias current constant and equal to that of M
10
. The compensation ca-
pacitance C
c
, which has a value of several picofarads, will couple this ripple onto the
gate of M
9
and directly to the output. In this case, we can nd that the compensation
59
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
10
-100
-50
0
50
100
Frequenct (Hz)
G
a
i
n

(
d
B
)
X: 2.455e+008
Y: -0.1609
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
10
-400
-300
-200
-100
0
Frequenct (Hz)
P
h
a
s
e
X: 2.455e+008
Y: -158.8
Figure 5.1: AC performance with 20pF load capacitance
capacitance couples the power supply disturbance directly to the output and results in
poor positive PSRR.
Therefore, one way to increase the PSRR is to remove this direct coupling.
Ahuja-style frequency compensation [23] introduces an intermediate common gate stage
and the compensation capacitor is connected between the output and the source of the
common-gate transistor. This method can improve PSRR. But this extra stage will add
noise directly to the rst stage and worsen its noise performance. [24] introduces an
internal compensation technique with better PSRR. But this structure has two complex
poles which introduce peaking in the frequency response. There is also a Right Hand
Plane (RHP) zero problem. In a low noise design, the rst stage transconductance is
close or even larger than that of the second stage. It is difcult for this structure to move
non-dominant poles and the RHP zero beyond the unity-gain bandwidth, making it hard
to control stability.
A practical design, with better positive PSRR, is shown in Figure 5.2. The com-
pensation capacitance is connected in between the cascode stage, isolated from Vdd and
ground noise. The positive PSRR is increased, but the negative PSRR deteriorates. This
60
1
M
2
M
3
M
4
M
a
M
5 a
M
6
7
M
8
M
DD
V
a
M
1
a
M
2
0
M
a
M
0
9
M
10
M
11
M
12
M
13
M
14
M
c
C
Out
1 b
V
2 b
V
3 b
V
4 b
V
5 b
V
b
M
5 b
M
6
1
M
2
M
3
M
4
M
a
M
5 a
M
6
7
M
8
M
DD
V
a
M
1
a
M
2
0
M
a
M
0
9
M
10
M
11
M
12
M
13
M
14
M
c
C
Out
1 b
V
2 b
V
3 b
V
4 b
V
5 b
V
b
M
5 b
M
6
Figure 5.2: New structure with cascode compensation
is due to the 25pF compensation capacitance. In this design, the transistors M
5b
and M
6b
work in triode region. According to [22] and [25], the RHP zero is avoided by indirectly
feeding back the feedback current to an internal low-impedance node, which result in
better phase margin. This operational ampliers AC performance with 10pF load is
shown in Figure 5.4. The unity gain bandwidth is simulated to be 240MHz with phase
margin of 25
o
. The noise performance of the new structure is shown in Figure 5.5. The
total noise is 1.876nV/

Hz at 1MHz and 1.22nV/

Hz at 10MHz.
61
10
0
10
2
10
4
10
6
10
8
10
10
-20
0
20
40
60
80
100
120
140
160
Positive PSRR
Frequency(Hz)
P
S
R
R
(
d
B
)
Cascode
Miller
(a)
10
0
10
2
10
4
10
6
10
8
10
10
0
20
40
60
80
100
120
Positive PSRR
Frequency(Hz)
P
S
R
R
(
d
B
)
Cascode
Miller
(b)
Figure 5.3: PSRR simulation results: a) Positive PSRR, b) Negative PSRR
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
10
-50
0
50
100
Frequency(Hz)
G
a
i
n
X: 2.455e+008
Y: -0.02884
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9
10
10
-300
-200
-100
0
Frequency(Hz)
d
e
g
r
e
e
X: 2.455e+008
Y: -155.5
Figure 5.4: Cascode-compensated operational ampliers AC performance
62
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
0
1
2
3
4
5
6
7
8
9
x 10
-7
X: 1e+006
Y: 1.876e-009
X: 1e+007
Y: 1.22e-009
Frequency(Hz)
n
o
i
s
e

l
e
v
e
l

(
v
/

(
H
z
)
)
Figure 5.5: Noise level of the cascode-compensated operational amplier
63
CHAPTER 6
Conclusions
6.1 Summary
Most of the literature on CMOS low noise operational amplier design empha-
sizes icker noise reduction. The standard practice is to increase the size and aspect
ratio of the input pair or replace the CMOS input transistors with bipolar transistors.
Those methods can achieve low icker noise close or comparable to the bipolar transis-
tor counterpart. However, the noise oor within the megahertz bandwidth range is still
high, generally larger than 5nV/

Hz. Some dynamic methods such as chopper sta-

bilization and auto-zeroing also address only icker noise and offset reduction. Those
methods increase the noise oor within the megahertz bandwidth range because of the
factors like noise-aliasing and charge injection, which limit operational ampliers incor-
porating those methods to low frequency (<1MHz) applications. This research analyzed
and optimized a differential pair and operational amplier aimed at minimizing both the
icker noise and the thermal noise. An operational amplier with the input-referred
voltage noise PSD of less than 2nV/

Hz for frequencies > 1MHz was realized.

Most available CMOS low noise operational ampliers have unity gain band-
width of just several megahertz, which can not provide sufcient close loop gain for
applications in megahertz range. The unity gain bandwidth of this new structure is
maximized to several hundreds megahertz and it can be used to either deliver high
signal bandwidth at a high gain, or to extend the achievable bandwidth or gain in tran-
simpedance applications. Whats more, the techniques for noise reduction and DC gain
for this structure are independent. The amplier can achieve low noise performance
and high gain simultaneously, something that is often a trade-off in normal operational
amplier design.
64
CMOS operational ampliers generally have a higher offset voltage than bipolar
operational ampliers. In this design, a digital offset trimming method was investigated
and designed to cover 10mV input-referred offset with only minimal deteriorating the
operational ampliers AC and noise performances. This method is very suitable for
low voltage design.
When this designed operational amplier is put into the test system to measure
the nanopore-base gene sequencer, it is congured as a transimpedance amplier. That
is, the gene sequencers output is connected to the positive input of this operational
amplier, and the operational ampliers negative input is connected to its owns out-
put through a feedback resistor. Since output current signal of the gene sequencer is
limited to the bandwidth from 400kHz to 10MHz, the operational ampliers output is
connected to a band-pass lter to remove the icker noise below 400kHz and thermal
noise above 10MHz.
6.2 Future Work
In this design, the expected noise PSDfromthe taped-out operational amplier is
not successfully measured. The main reason is that the taped-out operational amplier
has limited phase margin, and it is not stable when it is unity-gain congured for the
noise measurement. In Chapter 5, the operational amplier with the same structure is
redesigned and its phase margin is increased. More work would need to nish its layout
and get it fabricated and tested.
When the designed operational amplier is congured as a transimpedance am-
plier, the feedback resistor will also introduce noise. More work will be needed to
analyze the noise issue related to this transimpedance amplier.
There are bias voltages generated from bias network for M
0
, M
3
to M
8
. But the
noise sources in the noise model given in Chapter 3 only include the noise generated by
those MOSFETs themselves, dont include the noise from the bias network. The noise
65
from the bias network hasnt been analyzed so far. More time and research would need
to analyze the noise contribution of the bias network and low pass lter could be put in
between the bias network and biased MOSFETs.
The PSRR of the structure in Figure 3.1 is analyzed in Chapter 5 and a new
cascode structure is proposed. Simulation result shows big improvement in the positive
PSRR for this cascode structure, but the negative PSRR is deteriorated. So, more time
and work would be needed for the analysis of this cascode structure to nd its small-
signal model and increase both positive and negative PSRR.
Chapter 3 describes a continuous-mode offset reduction technique. This method
contains an auxiliary input port which introduces extra noise and extra power. More
work would need to nd other continuous-mode offset reduction techniques. Floating-
gate technology[26] is a potential way for this purpose. [27] successfully implementes a
CMOS operational amplier with only 25V input-referred offset using oating-gate
technology. The advantage of this oating gate method is that it results in a compact ar-
chitecture of designed operational amplier and the offset reduction dissipates no extra
power after one-time programming. This method introduces no extra icker noise ac-
cording to [27]. More work would need to nd its effects on thermal noise performance.
A 3.3V CMOS process is used in this design. In the future, the process with
higher supply voltage can be tried. The higher the supply voltage, the higher the dy-
namic range, then the input pair of the designed operational amplier can sink more
bias current for further noise reduction.
The advantage of the bipolar device is its low icker noise performance, but it
requires big bias current. This bias current has several pA/

Hz current noise. CMOS

transistor is a voltage-controlled device, requiring almost no bias current. But it has
notoriously large icker noise. JFET device provides a combination of the advantages
of the bipolar and CMOS ones: its icker noise is comparable with that of the bipo-
lar transistor and its thermal noise at the megahertz bandwidth is comparable with the
66
CMOS transistor. The bias current for JFET is around pico-amperes. But its input bias
current noise density could be as small as several fA/

Hz up to megahertz range, far

less than that of a bipolar device. [28] describes a JFET device fabricated in a CMOS
process for the low noise application. This JFET device can be used for the input pair
of the low noise operational amplier. In the future work, JFET process or JFET device
customized in a CMOS process can be studied for the low noise operational amplier
design.
67
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69
BIOGRAPHY OF THE AUTHOR
Zhineng Zhu was born in Anhui, China in 1976. He received his high school
education from Tongchen First School in Tongchen, China
He entered the Hefei University of Technology in 1994 and obtained his Bache-
lor and Master degrees in Electrical Engineering in 1998 and 2001 respectively.
In September 2002, he entered Ohio University as a graduate student.
In September 2004, he was enrolled for graduate study in Electrical Engineering
at the University of Maine as a Research Assistant. His current research interests include
low noise and mixed-signal integrated circuit design. And his interests include playing
soccer and ping-pang ball.
He is a candidate for the Master of Science degree in Electrical Engineering from
the University of Maine in May 2007
70