Design/Coding Exercise: Ethernet 802.

3 Management Interface (MDC/MDIO) Design

Design/Coding Exercise: Ethernet Management Interface (MDC/MDIO) Design

Reference: Ethernet 802.3-2000 Specification Clause 22.2. Relevant portion of the spec is reproduced at the end of this document. MDC/MDIO is a 2-wire interface used by Ethernet Station Management Entity to configure as well as read status from various PHY devices connected to it. There can be a maximum of 31 PHY devices sharing the bidirectional MDIO serial line. MDIO Master Block: Design a Master Block which translates host access transactions to MDC/MDIO transaction. This Master Block generally sits in the MAC Device Controller Chip.
mdio_out mdio_oe mdio_in cfg_mdc_pwidth[3:0] cfg_no_preamble mdio

reset_n clk

Mgmt Interface Master Block (mmb_core) [in MAC Device]

mdc

host_mmb_req host_mmb_rw_n host_mmb_phy_addr[4:0] host_mmb_reg_addr[4:0] host_mmb_wr_data[15:0] mmb_host_ack mmb_host_rd_data[15:0] mmb_host_rd_err

MDC/MDIO transaction specification is given in the Appendix of this document. mdc clock is generated by dividing clk by 2*Cfg_mdc_pwidth. Cfg_mdc_pwidth determines the high/low pulse width of MDC in units of clk cycle. Value of 0 for cfg_mdc_pwidth is not valid. When under reset, MDC is not generated and is 0. Cfg_mdc_pwidth can be configured with a value between 3 and 15. If cfg_no_preamble is high, the preamble should be suppressed. If cfg_no_preamble is low, master Host Transaction: Host initiates a MDIO transaction by asserting host_mmb_req along with the corresponding access type (read or write). Read access is indicated by host_mmb_rw_n being 1 and write access is by host_mmb_rw_n being 0. PHY to which the access is slated is provided by host_mmb_phy_addr and within the chosen PHY, one of the 32 registers is chosen by host_mmb_reg_addr. Once MMB completes the requested transaction, it asserts mmb_host_ack for one clock cycle, based on which the host would deassert host_mmb_req. In case of write transaction, MMB writes into PHY devices chosen register with host_mmb_wr_data. In case of read transaction, MMB sends the read data from PHY through mmb_host_rd_data along with mmb_host_ack. Mmb_host_rd_err is generated by MMB if the PHY is not responding to the requested read access (TA not driven with 0 for the second bit).

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Design/Coding Exercise: Ethernet 802.3 Management Interface (MDC/MDIO) Design MDIO Slave Block: Also Design a Slave Block which translates MDC/MDIO transactions to access registers in the PHY device. As many as 32 registers can be accessed. The Slave Block sits in the PHY device. Each PHY device responds to MDC/MDIO transactions only if the PHY address of the transaction matches with that of its own device address (cfg_phy_addr). It can be assumed that ratio of MDC period to clk period is greater than or equal to 4.

reset_n clk cfg_phy_addr[4:0]

mdio_out mdio_oe mdio_in mdio

Mgmt Interface Slave Block (msb_core) [in PHY Device]

msb_reg_req msb_reg_rw_n msb_reg_reg_addr[4:0] msb_reg_wr_data[15:0] reg_msb_ack reg_msb_rd_data[15:0]

mdc

Once msb_reg_req is asserted in a clock cycle (say cycle no 1), host acknowledges and completes the accesses by asserting reg_msb_ack for one clock cycle in cycle no N (where N is the cycle time of the read/write transactions) and returns read data along with ack for read access and writes write data into the corresponding register for write access. Once MSB samples reg_msb_ack as asserted high, it deasserts msb_reg_req. Cycle time for accesses to the host side can be taken as 2 which implies that reg_msb_ack is asserted in the next cycle following msb_reg_req assertion.

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Design/Coding Exercise: Ethernet 802.3 Management Interface (MDC/MDIO) Design Appendix: Management Interface Specification 22.2.2.11 MDC (management data clock) MDC is sourced by the Station Management entity to the PHY as the timing reference for transfer of information on the MDIO signal. MDC is an aperiodic signal that has no maximum high or low times. The minimum high and low times for MDC shall be 160 ns each, and the minimum period for MDC shall be 400 ns, regardless of the nominal period of TX_CLK and RX_CLK. 22.2.2.12 MDIO (management data input/output) MDIO is a bidirectional signal between the PHY and the STA. It is used to transfer control information and status between the PHY and the STA. Control information is driven by the STA synchronously with respect to MDC and is sampled synchronously by the PHY. Status information is driven by the PHY synchronously with respect to MDC and is sampled synchronously by the STA. MDIO shall be driven through three-state circuits that enable either the STA or the PHY to drive the signal. A PHY that is attached to the MII via the mechanical interface specified in 22.6 shall provide a resistive pullup to maintain the signal in a high state. The STA shall incorporate a resistive pull-down on the MDIO signal and thus may use the quiescent state of MDIO to determine if a PHY is connected to the MII via the mechanical interface defined in 22.6. The limits on the values of these pull-ups and pull-downs are defined in 22.4.4.2. 22.2.4.5 Management frame structure Frames transmitted on the MII Management Interface shall have the frame structure shown in Table 2210.

The order of bit transmission shall be from left to right. 22.2.4.5.1 IDLE (IDLE condition) The IDLE condition on MDIO is a high-impedance state. All three state drivers shall be disabled and the PHYs pull-up resistor will pull the MDIO line to a logic one. 22.2.4.5.2 PRE (preamble) At the beginning of each transaction, the station management entity shall send a sequence of 32 contiguous logic one bits on MDIO with 32 corresponding cycles on MDC to provide the PHY with a pattern that it can use to establish synchronization. A PHY shall observe a sequence of 32 contiguous one bits on MDIO with 32 corresponding cycles on MDC before it responds to any transaction. If the STA determines that every PHY that is connected to the MDIO signal is able to accept management frames that are not preceded by the preamble pattern, then the STA may suppress the generation of the preamble pattern, and may initiate management frames with the ST (Start of Frame) pattern.

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Design/Coding Exercise: Ethernet 802.3 Management Interface (MDC/MDIO) Design 22.2.4.5.3 ST (start of frame) The start of frame is indicated by a <01> pattern. This pattern assures transitions from the default logic one line state to zero and back to one. 22.2.4.5.4 OP (operation code) The operation code for a read transaction is <10>, while the operation code for a write transaction is <01>. 22.2.4.5.5 PHYAD (PHY Address) The PHY Address is five bits, allowing 32 unique PHY addresses. The first PHY address bit transmitted and received is the MSB of the address. A PHY that is connected to the station management entity via the mechanical interface defined in 22.6 shall always respond to transactions addressed to PHY Address zero <00000>. A station management entity that is attached to multiple PHYs must have a priori knowledge of the appropriate PHY Address for each PHY. 22.2.4.5.6 REGAD (Register Address) The Register Address is five bits, allowing 32 individual registers to be addressed within each PHY. The first Register Address bit transmitted and received is the MSB of the address. The register accessed at Register Address zero <00000> shall be the control register defined in 22.2.4.1, and the register accessed at Register Address one <00001> shall be the status register defined in 22.2.4.2. 22.2.4.5.7 TA (turnaround) The turnaround time is a 2 bit time spacing between the Register Address field and the Data field of a management frame to avoid contention during a read transaction. For a read transaction, both the STA and the PHY shall remain in a high-impedance state for the first bit time of the turnaround. The PHY shall drive a zero bit during the second bit time of the turnaround of a read transaction. During a write transaction, the STA shall drive a one bit for the first bit time of the turnaround and a zero bit for the second bit time of the turnaround. Figure 2213 shows the behavior of the MDIO signal during the turnaround field of a read transaction.

22.2.4.5.8 DATA (data) The data field is 16 bits. The first data bit transmitted and received shall be bit 15 of the register being addressed. 22.3.4 MDIO timing relationship to MDC MDIO (Management Data Input/Output) is a bidirectional signal that can be sourced by the Station Management Entity (STA) or the PHY. When the STA sources the MDIO signal, the STA shall provide a minimum of 10 ns of setup time and a minimum of 10 ns of hold time referenced to the rising edge of MDC, as shown in Figure 2216, measured at the MII connector.

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Design/Coding Exercise: Ethernet 802.3 Management Interface (MDC/MDIO) Design

When the MDIO signal is sourced by the PHY, it is sampled by the STA synchronously with respect to the rising edge of MDC. The clock to output delay from the PHY, as measured at the MII connector, shall be a minimum of 0 ns, and a maximum of 300 ns, as shown in Figure 2217.

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