ABSTRACT

Networks on chips (NoCs) have been introduced as a remedy for the growing problems of current interconnects in VLSI chips. Being a relatively new domain in research, simulation tools for NoCs are scarce. To fill the gap, we use network simulator NS-2 for simulating NoCs, especially at high level chip design. The huge library of network elements along with its flexibility to accommodate customized designs, NS-2 becomes a viable choice for NoCs. We have used NS-2 to simulate our prototype of a fault tolerant protocol for NoCs.A new chip design paradigm called Network on Chip (NOC) offers a promising architectural choice for future systems on chips. NOC architectures offer a packet switched communication among functional cores on the chip. NOC architectures also apply concepts from computer networks and organize on-chip communication among cores in layers similar to OSI reference model. We have constructed a proto model using a public domain network simulator NS-2 and evaluated design options for a specific NOC architecture which has a two-dimensional mesh of switches. We have also designed our own custom topology so that we can enhance the performance of NoC architecture up to 60% with respect to time and efficiency. In particular, we have analyzed the

simulation results about the timeliness property, throughput, end to end delay in packet forwarding from one node to another. The results are useful for design of an appropriate switch for the NOC. Keywords: NoC, Network Simulator, Switching, VLSI

TABLE OF CONTENT
Page No

.
LIST OF FIGURES LIST OF TABLES LIST OF GRAPHS ABSTRACT Chapter 1-INTRODUCTION
1.1.-Introduction 1.1.1-What is SOC 1.1.2-System on chip Architecture 1.1.3-System on chip Interconnection 1.1.3.1-Type of System on Chip Interconnection 1.1.3.2-The Benefits of System on Chip 1.1.3.3-The Drawbacks of System on Chip 1.1.3.4-Major SOC Applications 1.1.4-Network on Chip 1.1.4.1-Component of NOC
1.1.4.2-Origins of NOC concept 1.1.4.3-Advantages of NOC

vi viii

iv x
1 1 2 2 3 3 4 4 4 4 6 7 8 8 8
i

1.2-Objective 1.3-Motivation

Chapter 2- THEORITICAL BACKGROUND

2.1-Why NoC 2.2-NOC Main Components 2.2.1-Resource Network Interface 2.2.2-Router 2.3-Other Topologies for NOC Architecture 2.3.1-SPIN 2.3.2-CLICH 2.3.3-TORUS 2.3.4-FOLDED TORUS 2.3.5-OCTAGON 2.3.6-BFT 2.4-NOC Switching Techniques 2.4.1-Wormhole Switching 2.4.2-Packet Switching 2.4.3-Circuit Switching

11 11 11 12 11 13 13 13 14 15 16 16 17 17 17 18

Chapter 3 NoC Network Architecture

3.1-Introduction 3.2-Advantages Of NoC Architecture 3.3-Topology 3.3.1-Topology Classification 3.3.1.1-Direct Topologies

20 20 21 21 21 21 ii

3.3.1.2-Indirect Topologies 3.3.1.3-Irregular Topologies 3.4-Routing Algorithm 3.4.1-Static Routing 3.4.2-Dynamic Routing 3.5-Flow Control Schemes 3.6-Quality Of Service 3.7-NoC Network Performance Analysis 3.7.1-Simulation Based 3.7.2-Algorithm Based 3.7.3-Mathematics Based 3.8- NoC Communication Refinement

22 23 23 24 25 26 26 27 27 28 28 28 29 29 29 30 30 30 30 31 31 32 32 32 iii`

Chapter 4-SIMULATION
4.1-What is Simulation 4.2-Why simulation 4.3-Simulation Code 4.4-Simulation:Advantages/Drawbacks 4.4.1-Advantages 4.4.2-Drawbacks 4.5- Basic Concepts in Network Simulation 4.6-Network Simulation and Simulator 4.6.1-Whats in Simulation 4.6.2-Simulation 4.6.3-Simulation Block diagram

4.7-Type Of Network Simulators 4.7.1-Commercial and Open source simulators 4.7.1.1- Advantages Of Commercial Simulator 4.7.1.2- Disadvantages Of Commercial Simulator 4.7.2-Open Source Simulator 4.7.2.1-Advantages Of Open Source Simulator 4.7.2.2-Disadvantages Of Open Source Simulator 4.8-Ns-2 Outline 4.8.1-What is Ns-2 4.8.1.1- Creating Topologies 4.8.1.2-Observing Network Behaviour 4.8.2-Overview 4.8.2.1-Ns Status 4.8.2.2-Ns Functionalities 4.8.3-How do I use It 4.8.3.1- Basics Of Using Ns-2 4.8.4 User View of Ns-2 4.8.4.1-Why Two Languages

33 34 34 34 34 35 35 35 35 35 36 37 37 37 38 38 38 39

Chapter 5-IMPLEMENTATION,RESULT AND ANALYSIS

5.1-Mesh Topology 5.1.1-Model No 1 5.1.2-Output Generated via Code 5.1.3-Flow Of Data Generated In Mesh Topology

51 51 51 51 52 iv

5.1.4-Outcomes 5.2-Proposed Topology 5.2.1-Model No 2 5.2.2- Output Generated Via Code 5.2.3- Flow Of Data Generated In Proposed Topology 5.2.4-Outcomes 5.2.5-Overallanalysis

52 58 58 58 58 59 64

Chapter 6-CONCLUSION AND FUTURE SCOPE Chapter 7-References

65

66

List of Figures
Fig 1.1-PCB to SOC Fig 1.2-ASIC Design Set Up Fig 1.3- Noc Transportation Technique Fig 1.4-NoC Layered Architecture Fig 1.5-NoC Component Resource Fig 2.1-Resource Network Interface Fig 2.2-SPIN Architecture Fig 2.3-CLICH Architecture Fig 2.4-Torus Architecture Fig 2.5-Folded Torus Architecture Fig 2.6-Octagon Technique Fig 2.7-BFT Topology Fig 2.8-Packet Switching Fig 3.1-NoC Operation Fig 3.2-Direct Topology Fig 3.3-4*4 Mesh Topology Fig 3.4-Indirect Topology Fig 3.5-Irregular Topology Fig 3.6-Dynamic Routing Scheme Fig 3.7-Cyclic Dependencies In The Network Routing Fig 3.8-Network Interface Fig 4.1-Simulation

Page No
1 3 5 6 7 12 13 14 15 15 16 17 18 20 21 22 22 23 25 25 27 29 vi

Fig 4.2-Block Diagram Of Simulation Fig 4.3-Topology In The Ns-2 Fig 4.5-User View In The Ns-2 Fig 4.6-Class Hierarchy Fig 5.1-Mesh Topology

33 36 38 39 51

Fig 5.2-Flow Of Data In Mesh Topology

52

Fig 5.3-Proposed Topology

58

Fig 5.4-Flow Of Data In Proposed Topology

58

vii

List Of Tables
Table 4.1-Types Of Simulator Table 5.1-Result Of Mesh Topology Table 5.2-Throughput Results For Mesh Topology Table 5.3-End to End delay results For Mesh Topology Table 5.4-Results Of Proposed Topology Table 5.5-Throghput Results For Proposed Topology Table 5.6-End to End Delay Results For Proposed Topology

Page No
34 52 54 56 59 61 63

viii

List Of Graph
Graph 5.1-Throughput versus time of mesh topology Graph 5.2-End to End delay versus time of mesh topology Graph 5.3-Transmission time of the packets Graph 5.4-Throughput versus time of proposed topology Graph 5.5-End to end delay versus time of proposed topology

Page No
55 57 60 62 64

ix

Chapter 1
1.1 Introduction
This chapter highlights System-on-Chip design challenges and introduces the Network onChip concept. Recent technological development in the field of integrated circuits has enabled designers to accommodate billions of transistors. The level of integration has enhanced computational power enormously. The exponential decrease in the feature size has enabled integration of heterogeneous IP cores on a single chip leading to a new era of integration circuits known as System-on-Chip.[1,2] Technological Advances o Todays chip can contains 100M transistors . o Transistor gate lengths are now in term of nano meters . o Approximately every 18 months the number of transistors on a chip doubles Moores law . The Consequences o Components connected on a Printed Circuit Board can now be integrated onto single chip . o Hence the development of System-On-Chip design .

Figure 1.1 PCB to SoC

1

1.1.1 What is SoC: According to first person The VLSI manufacturing technology advances has made possible to put millions of transistors on a single die. It enables designers to put systems-on-a-chip that move everything from the board onto the chip eventually. According to another person SoC is a high performance microprocessor, since we can program and give instruction to the uP to do whatever you want to do. And according to third person SoC is the efforts to integrate heterogeneous or different types of silicon IPs on to the same chip, like memory, uP, random logics, and analog circuitry. All of the above are partially right, but not very accurate.[2,3] SoC not only chip, but more on system. o SoC = Chip + Software + Integration The SoC chip includes: o Embedded processor o ASIC Logics and analog circuitry o Embedded memory The SoC Software includes: o OS, compiler, simulator, firmware, driver, protocol stack-Integrated development environment (debugger, linker, ICE)Application interface (C/C++, assembly) The SoC Integration includes : o O The whole system solution Manufacture consultant

o Technical Supporting 1.1.2 System on Chip architecture: Typical ASIC design can take up to two years to complete. With increasing Complexity of ICs and decreasing Geometry, IC Vendor steps of Placement, Layout and Fabrication are unlikely to be greatly reduced. In fact there is a greater risk that Timing Convergence steps will involve more iteration. Need to reduce time before Vendor Steps. Need to consider Layout issues up-front.

Figure 1.2: ASIC Design Setup 1.1.3 System on Chip interconnection: Design reuse is facilitated if standard internal connection buses are used. All cores connect to the bus via a standard interface. There are any-to-any connections is easy but Not all connections are necessary. It has global clocking scheme and support to power consumption. 1.1.3.1 Type of System on Chip interconnection: There are four type of system on chip interconnection which is following.

AMBA (Advanced Microcontroller Bus Architecture) is a collection of buses from ARM for satisfying a range of different criteria. APB (Advanced Peripheral Bus): simple strobed-access bus with minimal interface complexity. Suitable for hosting peripherals. ASB (Advanced System Bus): a multi-master synchronous system bus. AHB (Advanced High Performance Bus): a high- throughput synchronous system backbone . Burst transfers and split transactions.

1.1.3.2 The Benefits of System on Chip: There are several benefits in integrating a large

digital system into a single integrated circuit .These include Lower cost per gate. Lower power consumption. Faster circuit operation. More reliable implementation. Smaller physical size. Greater design security.

1.1.3.3 The Drawbacks of System on Chip: The principle drawbacks of SoC design are associated with the design pressures imposed on todays engineers, such as Time-to-market demands. Exponential fabrication cost. Increased system complexity. Increased verification requirements

1.1.3.4 Major SoC Applications: Following is the major application in the field of SoC. Speech Signal Processing. Image and Video Signal Processing. Information Technologies o PC interface (USB, PCI, PCI-Express, IDE, Etc) Computer peripheries (printer control, LCD monitor controller, DVD controller,. etc) . Data Communication o Wire-line Communication: 10/100 Based-T, x DSL, Gigabit Ethernet,.. Etc ,etc . Technological advances mean that complete systems can now be implemented on a single chip. The benefits that this brings are significant in terms of speed, area and power. The drawbacks are that these systems are extremely complex requiring amounts of verification. The solution is to design and verify re-useable IP 1.1.4 Network-on-Chip: This is the alternative of traditional bus-based and point-to4

o Wireless communication: Blue-Tooth, WLAN, 2G/3G/4G, Wi-Max, UWB,

point communication structures. It is already knowing that the networking technique dealing dealing with same kind of problems on traditional computer networks. Conventional computer networking concept can be borrow by the NoC designers with necessary point customization to suit demands of SoCs. In a NOC system, modules exchange data using a network as a public transportation shown in figure 1.3 (a, b, c) subsystem for the information traffic.

a) Bus

b) Point to Point

c) Network

Figure 1.3: NoC transportation technique

The wires in the links of the NoC are shared by many signals. A high level of parallelism is achieved, because all links in the NoC can operate simultaneously on different data packets. Of course, the algorithms must be designed in such a way that they offer large parallelism and can hence utilize the potential of NoC. Although NoCs can borrow concepts and techniques from the well-established domain of computer networking, it is impractical to blindly reuse features of classical computer networks and symmetric multiprocessors. In particular, NoC switches should be small, energy-efficient, and fast. NoCs need to support quality of service, namely achieve the various requirements in terms of throughput, end-to-end delays and deadlines. NoC is the Layered Design of reconfigurable micro networks. It exploits methods and tools used for general network and can achieve better communication in SoCs. Basically NoC is Micro networks based
5

the ISO/OSI model. NoC architecture consists of Data link, Network and Transport layers. Figure 1.4 is showing the layered architecture of the NoC.

Figure 1.4: NoC Layered Architecture

1.1.4.1 Components of a NOC: Figure 1.5 is shown the various component of NoC, like core Component, Network Adapter, Routing Node and link.

Figure 1.5 : NoC Component

1.1.4.2 Origins of the NoC Concept: The idea was talked about in the 90s, but actual research came in the new millennium. The origin of NoC has also been viewed as a paradigm shift from computation centric to communication-centric design as well as the implementation of scalable communication structures. Some well-known early publications on NoC: Guerrier and Greiner (2000) A generic architecture for on-chip packet-switched interconnections. Hemani et al. (2000) Network on chip: An architecture for billion transistor era. Dally and Towles (2001) Route packets, not wires: on-chip interconnection networks. Wingard (2001) MicroNetwork-based integration of SoCs. Rijpkema, Goossens and Wielage (2001) A router architecture for networks on silicon. De Micheli and Benini (2002) Networks on chip: A new paradigm for systems on chip design. A. Ben Abdallah, Masahiro Sowa, "Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization", JASSST2006, Dec. 4-9th, 2006. The NoCs contain a network of routers responsible for end to end delivery of the packets from IP-cores. Application in the network is decide the communication demands of these IP-cores, In the network for seamless integration of theses IP-Cores it is used network interface. 7

1.1.4.3 Advantages of NoC: NoC has following advantage in the network. Tiled architecture with mesh interconnect Point to point communication pipeline Allows for heterogeneous cores o Differing sizes, clock rates, voltages Regularity of the architecture eases interconnect design to a point to point communication. Allows for reuse of tiles. Regular repetition of similar wire segments which are easier to model as DSM interconnects. Allows the application of other high performance interconnect techniques including repeaters due to regularity in design.

1.2 OBJECTIVE
With the increase in integration density and complexity of the system on chip, the conventional interconnects are not suitable to fulfill the demands. The application of traditional network technologies in the form of NOC is a potential solution. NOC design space has many variables. Selection of a better topology results in lesser complexities and better power efficiency. In our project we are evaluating a simple Mesh Topology on the basis of timeliness. And we developed our own topology and have compare the existing mesh topology and our custom topological scenario on the basis of time and efficiency.

1.3 Motivation
Recently, network-on-chip (NoC) architectures are emerging as a candidate for the highly scalable, reliable, and modular on-chip communication infrastructure platform . The NoC architecture uses layered protocols and packet-switched networks which consist of on-chip routers, links, and network interfaces on a predefined topology. There have been many 8

architectural and theoretical studies on NoCs such as design methodology, topology exploration, Quality-of-Service (QoS) guarantee , resource management by software and test and verification. In large-scale SoCs, the power consumption on the communication infrastructure should be minimized for reliable, feasible, and cost-efficient implementations. However, little research has reported on energy- and power-efficient NoCs at a circuit or implementation level, since most of previous works have taken a top-down approach and they did not touch the issues on a physical level, still staying in a high-level analysis. Although a few of them were implemented and verified on the silicon they were only focusing on performance and scalability issues rather than the power-efficiency, which is one of the most crucial issues for the practical application to SoC design.

Chapter 2
2. Theoritical Background
Network-on-a-chip (NoC) is a new approach to System-on-Chip (SoC) design. NoCbased systems can accommodate multiple asynchronous clocking that many of today's complex SoC designs use. The NoC solution brings a Networking method to on-chip communication and brings notable improvements over conventional bus systems [4]. For the communication on chip, NoC has following characteristic. Layered Approach Buses replaced with Networked architectures O Better electrical properties O Higher bandwidth O Energy efficiency o Scalable 2.1Why NoC: There are some reason to used NoC which is define following Physical Nanometer-Technology Effects: Decreasing wire dimensions increases resistance. Decreasing inter-wire spacing increases capacitance, wire coupling delays, and crosstalk noises. Todays long wires (including bus lines) require the periodic insertion of repeaters. NoC favours the use of short wires and the overall reduction of the total wire length in the chip. NoC builds a highly-utilized and shared interconnection network with short links connected by routers. Better Scalability Chip Design Productivity Gap: It is a common assumption that the productivity of the designer increases every year by 21%, while the design complexity increases by 58% (following Moores Law). It calls for the development of highly reusable modules and the availability of third party IP cores. The modules interface should be independent of the chip size and of the number of modules on the chip. 10

 Distributed Nature of Modern Chip Architectures: The next generation of chip designs will incorporate multiple autonomous intelligent modules with a rich collection of communication services among them. The level of parallelism in chips is on the rise With increasing communication demands of processor and memory cores in Systems on Chips (SoCs), scalable Networks on Chips (NoCs) are needed to interconnect the cores. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, application-specific NoC that satisfies the design objectives and constraints of the targeted application domain is required. There are Many NoC solutions exist, each attempting to combining different features. The motivation of different architectures is the application on one side and technology on other side. The idea is to make the NoC application specific NoC, yet be general enough for reuse. No one-fits-all NoC implementation is available though low power high speed solutions are desired. Some of the most important phases in designing the NoC are the synthesis of the topology or structure of the network and setting of various design parameters (such as frequency of operation or link-width). The standard topologies (mesh, torus, etc.) that have been used in macro-networks result in poor performance and have large power and area overhead when used for SoCs. Such topologies are required for on-chip systems where the traffic characteristics of the system cannot be predicted statically, as in chip multiprocessors. However, for most SoCs the system is designed with static (or semi-static) mapping of tasks to processors and hardware cores and hence the communication traffic characteristics of the SoC can be obtained statically [5]. 2.2NoC Main Components: There are three component of a NoC Routers Switches, cores also called resources Resource to network interfaces Abbreviated as RNIs. Figure 2.1 is showing these entire components.

11

Figure 2.1: Resource Network Interface

2.2.1 Resource Network Interface: Resource can be anything like processor, DSP, memory, application specific hardware component, I/O controller, graphic controller etc. Core is produced raw information into packets which transmitted into entire network. Network router connected through RNI which is enabling the resource to send data to router. 2.2.2 Router: Backbone of the NoC system is the router, without this it is impossible to handle network. Functionality of router is to forward incoming packet to the destination source in packet switched network,. If it is directly connected it, or to forward the packet to another router connected to it.

12

2.3 Other Topologies for NoC Architecture 2.3.1 SPIN: SPIN Developed by Guerrier and Greiner. It is used to interconnect template. SPIN(figure 2.2 ) is stand on Scalable, Programmable, Integrated Network. It implements a fat-tree topology with two one-way 32bit data paths links. Packets are sent (via wormhole) as a sequence of flits each of size 4 bytes. Fat tree architecture is use to interconnect IP blocks. Three types of flits; first, data and last. The performance of the network under uniform randomly distributed load shows that the protocol accounts for about 31% of the total throughput, a relatively large overhead. Figure 2.2 is shown basic SPIN architecture with 16 node. Every node has four children and the parent is replicated four times at any level of the tree. The size of the network grows at (N log N)/8. In this architecture, the number of routers converges to R=3N/4, where N is the system size in terms of functional. Among all simple architectures SPIN seems to be complex but despite it is cost-efficient for VLSI.

Figure 2.2: SPIN Architecture

2.3.2 CLICH: NoC design two dimensional mesh network layout is known as Chip13

Level

Integration of Communicating Heterogeneous Elements (CLICHE). In this

architecture resources and switches both are equal and every switch is connected to a specific resource. Each switch is connected to four neighboring switches and one resource. Resources are heterogeneous. A resource can be a processor core, a memory block, an FPGA, a custom hardware block or any other intellectual property (IP) block, which fits into the available slot and compiles with the interface with the NoC switch. Architecture of the CLICH is shown in figure 2.3.

2.3.3 Torus: NoC architecture (Figure 2.4) has a 2D Torus. The Torus and mesh architecture is basically the same; the only difference being that the switches at the edges are connected to the switches at the opposite edge through a wrap-around channel. Torus architecture has five ports in each switch where one connected to the local functional IP and the others connected to the closest neighboring switches. The long endaround connections can yield excessive delays. However, this can be avoided by folding the Torus. 14

Figure 2.4: Torus Architecture

2.3.4 Folded torus: Dally and Towles developed folded torus architecture. The Folded Torus topology and mesh topology has similar architecture, except that the wires are wrapped around from the top component to the bottom and rightmost to leftmost, thereby doubling the bandwidth of a mesh network. Simple architecture is showing in the figure 2.5 [6].

Figure 2.5: Folded Torus 15

2.3.5 Octagon: In the Octagon architecture (in figure 2.6) each component never has to take more than a two-hop path to communicate with one another. The basic model is an eight component topology with twelve bidirectional communication links. Of course, a larger number of components and links can be used, but the overall structure is the same. The switches are arranged in a ring with one link between each, and one link from each component to a central connection point. This topology has some key advantages: There is two-hop communication between any two components in the SoC. High throughput. Used shortest-path routing algorithm.

Figure 2.6: Octagon Technique 2.3.6 BFT : In the Butterfly Fat Tree (BFT) topology shown in figure 2.7, the tree layout is modeled. Every tree node denoted through a set of coordinates (level, position) where level is the level in the tree and position is the spot in right to left ordering. Vertical levels are started with zero numbered at the leaves. The leaves in the trees correspond to each Intellectual property (IP) and the levels above represent one node. Two parent ports used by each switch, and four child ports or connections. 16

Figure 2.7: Butterfly Fat Tree (BFT) topology

2.4 NoC Switching Techniques: Switching strategy defines the way resources are allocated to the packets transferred across the chip. NoC has three type of switching technique which is defined following [7]. 2.4.1Wormhole Switching: Wormhole flow control, also called wormhole switching or wormhole routing is a system of simple flow control in computer networking based on known fixed links. When router send one packets for destination then the wormhole technique does not dictate the route to the destination but it decides. Wormhole technique quickly set up the routing information in the router The name wormhole plays on the way packets are sent over the links: the address is so short that it can be translated before the message itself arrives. 2.4.2Packet Switching: Packet switching technique where each messages is break into several packets which are similar in size. Control, routing information and other information maintained by packet switching. Each packet has separate route from source to destination. This technique is known as store-and-forward (SAF) switching. Packet header information is examined by intermediate routers to clear the packet destination and reveal which one of output channels must be forwarded and sent. Figure 2.8 is showing basic architecture of packet switching. 17

Figure 2.8: Packet Switching

2.4.3 Circuit Switching: Physical route are setup which is reserved between source node to destination node in this switching technique and data transfer time is gone on over the whole time. Reserved route released after completing data transferring. Source node set routing header information in the network which can be destination node information, controlling information, and other necessary information. If network has lot of successive message then circuit switching is the best technique to handle it. Due to reserved route by a special message, it may cause other messages blocking during sending time. 1.M. Horowitz, R. Ho, and K. Mai, The future of wires[1]. This paper discussed that traditional bus and crossbar based method to communication become very inefficient resulting in massive number of wires ,increasing heat and power consumption. This paper results that NoC approach promises the alternative to traditional bus based and point to,point communication architectures. 2. David Atienzaa and Federico Angiolinic Network on chip design and synthesis outlook[14].This paper discussed a thorough study of the current state of the art of NoC implementations using a design flow targeting the new trends imposed by deep submicron manufacturing processes. This paper presents a comparative analysis of different NoC fabrics ranging from regular topologies to highly tuned custom NoCs. 18

3.Partha Pratim Pande and Andre lvanov Performance Evaluation and Design TradeOffs for Network-on-Chip Interconnect Architectures[15].This paper developed a consistent and meaningful evaluation methodology to compare the performance and characterstics of a variety of NoC architectures. This paper results in the detailed comparisons and contrasted different NoC architectures in terms of throughput, latency, energy dissipation and silicon area overhead. 4. Shafi Patel and Parag Parandka Exploring alternative topologies for NoC Architecture [16]. In this paper key research area is Network-On-Chip Interconnect Architectures targeting communication infrastructure specially focusing on optimized topology is worked upon. The simulation is modeled using a conventional network simulator tool packet tracer 5.3 in which we compare optimized topology with mesh topology. This paper results in mesh topology and optimized topology on the basis of timeliness and number of links reduced.

19

Chapter 3
3. NoC Network Architectures
3.1 Introduction: However, as the number of components on a single chip and their performance continue to increase, the design of the communication architecture plays a major role in defining the area, performance, and energy consumption of the overall system. Furthermore, with technology scaling, the global interconnects cause severe onchip synchronization errors, unpredictable delays, and high power consumption. To mitigate these effects, the network on- chip (NoC) approach emerged recently as a promising alternative to classical bus-based and point-to-point (P2P) communication architectures. Aside from better predictability and lower power consumption, the NoC approach offers greater scalability compared to previous solutions for on-chip communication. To alleviate the complex communication problems that arise as the number of on-chip components increases, network chip (NoC) architectures have been recently proposed to replace global interconnects. NoC Operation Example:

CPU request Packetization Routing Receipt and unpacketization (AHB, OCP, ... pinout) Device response (if needed) Packetization and transmission Routing Receipt and unpacketization

Figure 3.1: NoC Operations 20

3.2 Advantages of NoC architectures: NoC architecture has following advantages Tiled architecture with mesh interconnect Point to point communication pipeline Allows for heterogeneous cores Differing sizes, clock rates, voltages Regularity of the architecture eases interconnects design to a point to point communication. Regular repetition of similar wire segments which are easier to model as DSM interconnects. Allows the application of other high performance interconnect techniques including repeaters due to regularity in design. 3.3 Topology: Physical structure of the network is representing by topology. Generally topology shows the connection between nodes in the network that mean physical connection show by topology. It adopted from large-scale networks and parallel computing. A good topology allows to fulfill the requirements of the traffic at reasonable costs Network topology can be compared with a network of roads 3.3.1 Topology classifications: Topology can be classified in three groups. One is direct topology and second is indirect topology and third is irregular topology. 3.3.1.1 Direct topologies: Each switch (SW) is connected to a single PE. As the # of nodes in the system increases, the total bandwidth also increases

Figure 3.2: Direct Topology 21

Example of Direct Topology is Mesh topology shown in figure 3.3. 2D mesh is most popular topology where all links have the same length. This type of topology is eases physical design and area grows linearly with the # of nodes.

Figure 3.3: 4 X 4 Mesh Topology 3.3.1.2 Indirect topologies: A set of PEs are connected to a switch. Fat tree in this Nodes are connected only to the leaves of the tree and more links near root, where bandwidth requirements are higher

Figure 3.4: Indirect Topology 22 3.3.1.3 Irregular Topology: This topology customized for an application. It is usually a

mix of shared bus, direct, and indirect network topologies. This kind of chip does not limit the shape of the PEs or the placement of the routers. It may be considered a "custom" NoC.

Figure 3.5: Irregular Topology (Reduced Mesh Topology) How to Select a Topology: selection of the topology is depending on the following situation. Application decides the topology type o o If PEs = few tens Star, Mesh topologies are recommended

If PEs = 100 or more o Hierarchical Star, Mesh are recommended Some topologies are better for certain designs than others

3.4 Routing Algorithms: Routing algorithm is responsible for correctly and efficiently routing packets or circuits from source to destination. Basically it determines path of the routing so packets may follow through the network graph. Routing algorithm used correct path to forward packets from source node to destination node. It also choose shortest path algorithm so performance of the whole network and packets transmission time can be control. To classify routing we must consider the following criteria [8]. 23

Where the routing decisions are taken? o o Source routing Distributed routing

How a path is defined? o Static (deterministic) o Adaptive

The path length o Minimal o Non Minimal

Classifications of the Routing algorithm in terms of path diversity and adaptively into three categories which are follow [8]: Deterministic Routing: It used same path to send packets from source node to destination node. Network Path diversity can be ignoring by the deterministic routing. It is simple and easy to implementation except load misbalancing due to insensitive to the network. Oblivious Routing: It includes deterministic algorithms as a subset. It maintains all paths from source node to destination node. Adaptive Routing: It distributes traffic dynamically in response to the network state. Which include the status of a node or link, the length of queues and historical network load information? NoC routing algorithm is very useful for the network because, they must prevent deadlock, livelock, and starvation. Choice of a routing algorithm depends on: Minimizing power required for routing Minimizing logic and routing tables

The Routing Table determines for each node the route via which it will send packets to other nodes. The routing table directly influences traffic in the NoC . Here we can also distinguish between 2 methods: Static routing Dynamic (adaptive) routing 3.4.1 Static Routing: The Routing Table is constant. The route is embedded in the packet 24

header and the routers simply forward the packet to the direction indicated by the header. The routers are passive in their addressing of packets (simple routers). 3.4.2 Dynamic Routing: The routing table can change dynamically during operation. Logically, a route is changed when it becomes slow due to other traffic. There is possibly out-of-order arrival of packets. Usually it requires more virtual channels. More resources needed to monitor state of the network.

Figure 3.6:Dynamic routing scheme Routing Algorithms Requirements: Routing algorithms must ensure freedom from deadlocks e.g. cyclic Dependency as shown in Figure 3.7 below.

Figure 3.7: Cyclic Dependencies in the network Routing algorithm must ensure freedom from live locks and starvation.

25

3.5 Flow Control Schemes: Low overhead scheme. It Requires only two control wires, One is going forward and signaling data availability and the other going backward and signaling either a condition of buffers filled (STALL) or of buffers free (GO). Basically it indicates the packet forwarding direction in the network. It deals with correct packets delivery coordination between sending and receiving packets. Flow control scheme can be blocked due to limited bandwidth and limited buffer size. Flow Control Schemes has one type of error known as T-Error. Due to more aggressive scheme it can detect faults by making use of a second delayed clock at every buffer stage. Delayed clock re-samples input data to detect any inconsistencies [9]. 3.6 Quality of Service (QoS): QoS refers to the level of commitment for packet delivery. Basically it divides into three categories [10] Best effort (BE) o Only correctness and completion of communication is guaranteed o Usually packet switched Guaranteed service (GS) o makes a tangible guarantee on performance, in addition to basic guarantees of correctness and completion for communication o Usually (virtual) circuit switched Differentiated service o prioritizes communication according to different categories o NoC switches employ priority based scheduling and allocation policies Interface: Different interface shall be connected to the network. The network uses a specific protocol and all traffic on the network has to comply to the format of this protocol.

26

Figure 3.8: Network Interface 3.7 NoC Network Performance Analysis: Simulation based and Algorithm based NoC performance analysis is discussed here. The simulation-based analysis is performed within the Nostrum Network-on-Chip Simulation Environment (NNSE). The algorithmbased approach addresses the feasibility test of delivering real-time messages in wormhole-switched networks. Network Performance Analysis Methods: Network performance analysis methods categories are Simulation-based. Algorithm-based and Mathematics-based.

3.7.1 Simulation-Based: Network and traffic model is build by this approach. Traffic loading in the network can be simulated network operation. Synthetic and realistic traffic models can be applied on simulation-based approach. Furthermore, it allows us to perform system-wide simulation where the interaction between the network and traffic sources/sinks may be captured and the performance-cost tradeo is examined. The evaluation of the network performance is conducted after simulation statistics are collected. The simulation speed can be different depending on the modeling details [11].

27

3.7.2 Algorithm-Based: Assumptions on network communication models make by the algorithm-based approach. The network delivery characteristics and switch arbitration behavior are captured by the communication model. An algorithm-based approach usually assumes that traffic has certain properties, for example, periodicity and independence. 3.7.3Mathematics-Based: The mathematics-based approach builds mathematical models for network and traffic. The mathematics-based approach is most efficient but limited in capability. Through formal derivation in mathematical based approach calculate the performance figure. Queuing theory and probability theory are the two basic analytic tools for network performance evaluation. Queuing theory is useful for analyzing a network in which packets spend much of their time waiting in queues. Probability theory is more useful in analyzing networks in which most contention time is due to blocking rather than queuing. The performance analysis methods, as described above, are not isolated. They can be used to validate against each other. To validate a model, we need to compare its results against known good data at a representative set of operating points and network configurations. They may be composed to take the advantages of each method. For instance, simulation and formal methods may be combined to speed up the simulation-based performance analysis [12]. 3.8 NoC Communication Refinement: In this it start with a system model specified in the synchronous model of computation. Through a top-down procedure, it refine the communication in the system model into NoC communication via the communication interface of a NoC platform. In the NoC case, the communication architecture is preferably predefined as a platform and the Application Level Interface (ALI), which provides primitives for inter-process communication, is the only way to access the communication services. The NoC communication refinement is therefore to refine the abstract communication in a system specification onto the NoC platform via the ALI [13].

28

Chapter 4
4. Simulation
4.1 What is simulation: Simulation is widely-used in system modeling for applications ranging from engineering research, business analysis, manufacturing planning, and biological science experimentation, just to name a few. Compared to analytical modeling, simulation usually requires less abstraction in the model (i.e., fewer simplifying assumptions) since almost every possible detail of the specifications of the system can be put into the simulation model to best describe the actual system. When the system is rather large and complex, a straightforward mathematical formulation may not be feasible. In this case, the simulation approach is usually preferred to the analytical approach.

Figure 4.1: Simulation

4.2 Why Simulation: real-system not available, is complex/costly or dangerous (eg: space simulations, flight simulations) quickly evaluate design alternatives (eg: different system configurations) evaluate complex functions for which closed form formulas or numerical techniques not available 29

4.3 Simulation Goals: o Support networking research and education o Protocol design, traffic studies, etc. o Protocol comparison Provide a collaborative environment o Freely distributed, open source o Share code, protocols, models, etc o Allow easy comparison of similar protocols o Increase confidence in results o More people look at models in more situations. o Experts develop models

Multiple levels of detail in one simulator

4.4 Simulation: advantages/drawbacks 4.4.1 Advantages: sometimes cheaper find bugs (in design) in advance generality: over analytic/numerical techniques detail: can simulate system details at arbitrary level

4.4.2 Drawbacks: caution: does model reflect reality large scale systems: lots of resources to simulate (especially accurately simulate) may be slow (computationally expensive 1 min real time could be hours of simulated time) art: determining right level of model complexity 30

statistical uncertainty in results

For network simulation, more specifically, it means that the computer assisted simulation technologies are being applied in the simulation of networking algorithms or systems by using software engineering. The application field is narrower than general simulation and it is natural that more specific requirements will be placed on network simulations. For example, the network simulations may put more emphasis on the performance or validity of a distributed protocol or algorithm rather than the visual or real-time visibility features of the simulations. Moreover, since network technologies is keeping developing very fast and so many Different organizations participate in the whole process and they have Different technologies or products running on Different software on the Internet. That is why the network simulations always require open platforms which should be scalable enough to include Different efforts and Different packages in the simulations of the whole network. Network simulator has two purposes which is following. Specific Purpose o ATM o Wireless o TCP/IP General Purpose o modifiable modules o Modules extensibility 4.5 Basic Concepts in Network Simulations: A simulation is, more or less, a combination of art and science. That is, while the expertise in computer programming and the applied mathematical tools account for the science part, the very skill in analysis and conceptual model formulation usually represents the art portion. A long list of steps in executing a simulation process seems to reflect this popular claim. Basically, all these steps can be put into three main tasks each of which carries different degrees of importance. 4.6 Network Simulation and Simulator: Generally speaking, network simulators try to model the real world networks. The principle idea is that if a system can be modeled, then futures of the model can be changed and the corresponding results can be analyzed. 31

Following feature provide by simulator. Easy network topology setup Protocols and application implementation o TCP, UDP, CBR, VBR , o Routing protocols o Queue management protocols Configurability Extensibility o FTP, Telnet, Web,

4.6.1 Whats in a simulation simulated time: internal (to simulation program) variable that keeps track of simulated time. system state: variables maintained by simulation program define system state o e.g., may track number (possibly order) of packets in queue, current value of retransmission timer events: points in time when system changes state o each event has associate event time e.g., arrival of packet to queue, departure from queue precisely at these points in time that simulation must take action (change state and may cause new future events) o model for time between events (probabilistic) caused by external environment. 4.6.2 Simulation: Through simulation in computer and communication network I can find the behaviors of the network and this network can be modeled by calculating the interaction between the Different network components (they can be end-host on network entities such as routers, physical links or packets) using mathematical formulas. Simulation module can be applied on actual or virtual data to calculate observation of data in the network..

32

4.6.3 Simulator Block Diagram:

Figure 4.2: Block Diagram of Simulation

4.7 Type of Network Simulators: There is various type of simulator exists. Each simulator has its own features and performance capability. All type of simulator can be tested on the performance based and accuracy in the results. Table 4.1 is showing different type of simulator based on availability in the market.

33

Table 4.1: Types of Simulator License type Commercial Open Source Network Simulator Name OPNET, Qualnet NS-2,NS-2

4.7.1 Commercial and Open Source Simulators: those simulator which are not providing source code of the software or the affiliated packages to the general users for free they all are commercial type of simulator and those simulator provide source code or affiliated software packages freely for the user they all are open source type of simulator. To use commercial simulator user have to pay to get the license to use their software or pay to order specific packages for their own specific usage requirements, typical example such type of simulator is OPNET. They have some advantage and disadvantage. 4.7.1.1 Advantages of Commercial Simulator: Provide complete code for uses. Provide full documentation for uses. Properly maintain by the vendor.

4.7.1.2 Disadvantages of Commercial Simulator: Not freely available. Costly.

4.7.2 Open Source Simulator: The open source network simulator has disadvantageous in this aspect, of advantage of commercial simulator and generally they are not enough specialized people working on the documentation. Typical open source network simulators include NS2, NS3.

34

4.7.2.1 Advantages of Open Source Simulator: Freely Available in the market. Ease to access. Changes in the code are possible. No maintains dependencies. It can also be very flexible and reflect the most new recent developments of new technologies in a faster way than commercial network simulators 4.7.2.2 Disadvantages of Commercial Simulator: No guaranty of right code. Documentation is not properly. Self maintenance. Control supports can lead to some serious problems Lack of version Applicability and life-time of the open source network simulators are limited

4.8 NS2 Outline: What is it? How do I use it

4.8.1 What is NS2: NS2 is one of the most popular open source network simulators. The original NS is a discrete event simulator targeted at networking research. Network Simulator A package of tools that simulates behavior of networks o o Create Network Topologies Log events that happen under any load

o Analyze events to understand the network behavior

4.8.1.1Creating Topologies: Figure 4.3 is showing the simple topology in the network.

35

Figure 4.3: Topology in the NS2 Nodes o Set properties like queue length, location o Protocols, routing algorithms Links o Set types of link Simplex, duplex, wireless, satellite o Set bandwidth, latency etc. Done through tcl Scripts 4.8.1.2 Observing Network Behavior: Observe behavior by tracing events, Eg. packet received, packet drop etc. figure 4.4 is showing the behavior of the network.

Figure 4.4: Network Behaviour 36

4.8.2 Overview: NS2 is the second version of NS (Network Simulator). NS is originally based on REAL network simulator [REAL]. The first version of NS was developed in 1989 and evolved a lot over the past few years. The current NS project is supported through DARPA. The current second version NS2 is widely used in academic research and it has a lot of packages contributed by different non-benefit groups. Ns is a simulator engine built in C++ and has an OTcl (Object-oriented Tcl) interface that is used for configuration and commands. Thus in order to debug NS we will have to deal with debugging issues involving both OTcl and C++. 4.8.2.1 Ns Status: Following is the current status of the network simulator Periodical release (ns-2.27, Jan 2004) o ~200K LOC in C++ and Otcl, o ~120 test suites and 100+ examples o 392 pages of ns manual o Daily snapshot (with auto-validation)
Platform support

o FreeBSD, Linux, Solaris, Windows and Mac User base o 1k institutes (50 countries), >10k users

4.8.2.2 Ns functionalities: Following are the functionality of the network simulator. Wired O Transportation: TCP,UDP, RTP,SRM o Traffic sources: web, ftp, telnet, cbr, stochastic o Queuing disciplines: drop-tail, RED, FQ, SFQ, DRR o o QoS: IntServ and Diffserv Emulation

Wireless o Ad hoc routing and mobile IP 37

o Directed diffusion, sensor-MAC Tracing, visualization, various utilitiy

4.8.3 How Do I use it? Creating a Simple Topology Getting Traces Using NAM

4.8.3.1 Basics of using NS2: Define Network topology, load, output files in Tcl Script To run,$ ns simple_network.tcl Internally, NS2 instantiates C++ classes based on the tcl scripts Output is in form of trace files

4.8.4User view of NS-2: From the users perspective, NS2 is an OTcl interpreter that takes an OTcl script as input and produces a trace file as output.

Figure 4.5: User view of NS-2 Figure 4.5 contains two sets of languages, namely C++ and OTcl. C++ is used for the creation of objects because of speed and efficiency. OTcl is used as a front-end to setup the simulator, configure objects and schedule events because of its ease of use. 38

4.8.4.1 Why two languages? (Tcl & C++): Following reason to use these two languages in NS-2.
C++: Detailed protocol simulations require systems programming language o byte manipulation, packet processing, algorithm implementation

o o

Run time speed is important Turn around time (run simulation, find bug, fix bug, recompile, re-run) is slower

Tcl: Simulation of slightly varying parameters or configurations o quickly exploring a number of scenarios

iteration time (change the model and re-run) is more important

Figure 4.6: Class Hierarchy

39

Creating the topology: Following example to create topology by using NS2 simulator. #create a new simulator object set ns [new Simulator] #open the nam trace file set nf [open out.nam w] $ns namtrace-all $nf #define a 'finish' procedure proc finish {} { global ns nf $ns flush-trace #close the trace file close $nf #execute nam on the trace file exec nam out.nam & exit 0 } #create two nodes set n0 [$ns node] set n1 [$ns node] #create a duplex link between the nodes $ns duplex-link $n0 $n1 1Mb 10ms DropTail

40

Mesh Topology
OTcl code #Create a simulator object set NS [new Simulator] #Define different colors for data _flows (for NAM) $NS color 1 Blue $NS color 2 red #Open the NAM trace _file set nf [open out.nam w] $NS namtrace-all $nf #Define a `finish' procedure Proc _finish {} { global NS nf $NS flush-trace #Close the NAM trace _file Close $ nf # Execute NAM on the trace _file exec nam out.nam & exit 0 } #Create sixteen nodes set n0 [$NS node] set n1 [$NS node] set n2 [$NS node] set n3 [$NS node] set n4 [$NS node] set n5 [$NS node] set n6 [$NS node] set n7 [$NS node] set n8 [$NS node] 41

set n9 [$NS node] set n10 [$NS node] set n11 [$NS node] set n12 [$NS node] set n13 [$NS node] set n14 [$NS node] set n15 [$NS node] #Create links between the nodes $NS duplex-link $n0 $n1 2Mb 10ms DropTail $NS duplex-link $n1 $n2 2Mb 10ms DropTail $NS duplex-link $n2 $n3 2Mb 10ms DropTail $NS duplex-link $n3 $n4 2 Mb 10ms DropTail $NS duplex-link $n4 $n5 2Mb 10ms DropTail $NS duplex-link $n5 $n6 2Mb 10ms DropTail $NS duplex-link $n6 $n7 2Mb 10ms DropTail $NS duplex-link $n7 $n8 2Mb 10ms DropTail $NS duplex-link $n8 $n9 2Mb 10ms DropTail $NS duplex-link $n9 $n10 2Mb 10ms DropTail $NS duplex-link $n10 $n11 2Mb 10ms DropTail $NS duplex-link $n11 $n12 2Mb 10ms DropTail $NS duplex-link $n12 $n132Mb 10ms DropTail $NS duplex-link $n13 $n14 2Mb 10ms DropTail $NS duplex-link $n14 $n15 2Mb 10ms DropTail $NS duplex-link $n0 $n7 2Mb 10ms DropTail $NS duplex-link $n1 $n6 2Mb 10ms DropTail $NS duplex-link $n2 $n5 2Mb 10ms DropTail $NS duplex-link $n5 $n10 2Mb 10ms DropTail $NS duplex-link $n6 $n9 2Mb 10ms DropTail $NS duplex-link $n7 $n8 2Mb 10ms DropTail $NS duplex- link $n8 $n15 2Mb 10ms DropTail 42

$NS duplex-link $n9 $n14 2Mb 10ms DropTail $NS duplex-link $n8 $n15 2Mb 10ms DropTail $NS duplex-link $n9 $n14 2Mb 10ms DropTail $NS duplex-link $n10 $n13 2Mb 10ms DropTail $NS duplex-link $n4 $n11 2Mb 10ms DropTail #Set Queue Size of link (n2-n3) to 10 $NS queue-limit $n2 $n3 10 #Give node position (for NAM) $NS duplex-link-op $n0 $n1 orient right $NS duplex-link-op $n1 $n2 orient right $NS duplex-link-op $n2 $n3 orient right $NS duplex-link-op $n3 $n4 orient down $NS duplex-link-op $n4 $n5 orient left $NS duplex-link-op $n5 $n6 orient left $NS duplex-link-op $n6 $n7 orient left $NS duplex-link-op $n7 $n8 orient down $NS duplex-link-op $n8 $n9 orient right $NS duplex-link-op $n9 $n10 orient right $NS duplex-link-op $n10 $n11 orient right $NS duplex-link-op $n11 $n12 orient down $NS duplex-link-op $n12 $n13 orient left $NS duplex-link-op $n13 $n14 orient left $NS duplex-link-op $n14 $n15 orient left $NS duplex-link-op $n0 $n7 orient down $NS duplex-link-op $n1 $n6 orient down $NS duplex-link-op $n2 $n5 orient down $NS duplex-link-op $n6 $n9 orient down $NS duplex-link-op $n5 $n10 orient down $NS duplex-link-op $n8 $n15 orient down $NS duplex-link-op $n9 $n14 orient down 43

$NS duplex-link-op $10 $n13 orient down $NS duplex-link-op $n4 $n11 orient down #Monitor the queue for link (n2-n3). (for NAM) $NS duplex-link-op $n2 $n3 queue Pos 0.5 #Setup a TCP connection set tcp [new Agent/TCP] $tcp set class_2 $NS attach-agent $n0 $tcp set sink [new Agent/TCPSink] $NS attach-agent $n3 $sink $NS connect $tcp $sink $tcp set fid_1 #Setup a FTP over TCP connection set ftp [new Application/FTP] $ftp attach-agent $tcp $ftp set type_ FTP #Setup a UDP connection set udp [new Agent/UDP] $NS attach-agent $n1 $udp set null [new Agent/Null] $NS attach-agent $n3 $null $NS connect $udp $null $udp set fid_2 #Setup a CBR over UDP connection set cbr [new Application/Traffic/CBR] $cbr attach-agent $udp $cbr set type_ CBR $cbr set packet_size_1000 $cbr set rate_ 1mb $cbr set random_ false #Schedule events for the CBR and FTP agents 44

$NS at 0.1 $cbr start $NS at 1.0 $ftp start $NS at 4.0 $ftp stop $NS at 4.5 $cbr stop #Detach tcp and sink agents (not really necessary) $NS at 4.5 $NS detach-agent $n0 $tcp ; $NS detach-agent $n3 $sink #Call the _finish procedure after 5 seconds of simulation time $NS at 5.0 finish #Print CBR packet size and interval puts CBR packet size = [$cbr set packet_ size] puts CBR interval = [$cbr set interval] #Run the simulation $NS run

45

Proposed (custom) Topology

OTcl code #Create a simulator object set NS [new Simulator] #Define different colors for data _flows (for NAM) $NS color 1 Blue $NS color 2 Red #Open the NAM trace _file set nf [open out.nam w] $NS namtrace-all $nf set nf [open noc.tr w] $NS trace-all $nf #Define a `_finish' procedure Proc _finish {} { global NS nf $NS _rush-trace #Close the NAM trace _file close $nf #Execute NAM on the trace_ file exec nam out.nam & exit 0 } #Create eighteen nodes set n0 [$NS node] set n1 [$NS node] set n2 [$NS node] set n3 [$NS node] set n4 [$NS node] set n5 [$NS node] set n6 [$NS node] set n7 [$NS node] set n8 [$NS node] 46

set n9 [$NS node] set n10 [$NS node] set n11 [$NS node] set n12 [$NS node] set n13 [$NS node] set n14 [$NS node] set n15 [$NS node] set n16 [$NS node] set n17 [$NS node] #Create links between the nodes $NS duplex-link $n0 $n1 2Mb 10ms DropTail $NS duplex-link $n0 $n16 2Mb 10ms DropTail $NS duplex-link $n7 $n16 2Mb 10ms DropTail $NS duplex-link $n8 $n16 2Mb 10ms DropTail $NS duplex-link $n15 $n16 2Mb 10ms DropTail $NS duplex-link $n1 $n2 2Mb 10ms DropTail $NS duplex-link $n2 $n3 2Mb 10 ms DropTail $NS duplex-link $n3 $n17 2Mb 10ms DropTail $NS duplex-link $n4 $n17 2Mb 10ms DropTail $NS duplex-link $n11 $n17 2Mb 10ms DropTail $NS duplex-link $n12 $n17 2Mb 10ms DropTail $NS duplex-link $n4 $n5 2Mb 10ms DropTail $NS duplex-link $n5 $n6 2Mb 10ms DropTail $NS duplex-link $n6 $n7 2Mb 10ms DropTail $NS duplex-link $n8 $n9 2Mb 10ms DropTail $NS duplex-link $n9 $n10 2Mb 10ms DropTail $NS duplex-link $n10 $n11 2Mb 10ms DropTail $NS duplex-link $n12 $n13 2Mb 10ms DropTail $NS duplex-link $n13 $n14 2Mb 10ms DropTail $NS duplex-link $n14 $n15 2Mb 10ms DropTail 47

#Set Queue Size of link (n2-n3) to 10 $NS queue-limit $n2 $n3 10 #Give node position (for NAM) $NS duplex-link-op $n0 $n1 orient right $NS duplex-link-op $n1 $n2 orient right $NS duplex-link-op $n2 $n3 orient right $NS duplex-link-op $n4 $n5 orient left $NS duplex-link-op $n5 $n6 orient left $NS duplex-link-op $n6 $n7 orient left $NS duplex-link-op $n8 $n9 orient right $NS duplex-link-op $n9 $n10 orient right $NS duplex-link-op $n10 $n11 orient right $NS duplex-link-op $n12 $n13 orient left $NS duplex-link-op $n13 $n14 orient left $NS duplex-link-op $n14 $n15 orient left $NS duplex-link-op $n7 $n16 orient left-down $NS duplex-link-op $n0 $n16 orient left-down $NS duplex-link-op $n8 $n16 orient left-up $NS duplex-link-op $n15 $n16 orient left-up $NS duplex-link-op $n3 $n17 orient right-down $NS duplex-link-op $n4 $n17 orient right-down $NS duplex-link-op $n11 $n17 orient right-up $NS duplex-link-op $n12 $n17 orient right-up #Monitor the queue for link (n2-n3). (for NAM) $NS duplex-link-op $n2 $n3 queue Pos 0.5 #Setup a TCP connection set tcp [new Agent/TCP] $tcp set class_2 $NS attach-agent $n0 $tcp set sink [new Agent/TCPSink] 48

$NS attach-agent $n12 $sink $NS connect $tcp $sink $tcp set fid_1 #Setup a FTP over TCP connection set ftp [new Application/FTP] $ftp attach-agent $tcp $ftp set type_ FTP #Setup a UDP connection set udp [new Agent/UDP] $NS attach-agent $n1 $udp set null [new Agent/Null] $NS attach-agent $n3 $nu11 $NS connect $udp $nu11 $udp set fid_ 2 #Setup a CBR over UDP connection set cbr [new Application/Traffic/CBR] $cbr attach-agent $udp $cbr set type_ CBR $cbr set packet_ size _ 1000 $cbr set rate_ 1mb $cbr set random _ false #schedule events for the CBR and FTP agents $NS at 0.1 $cbr start $NS at 1.0 $ftp start $NS at 4.0 $ftp stop $NS at 4.5 $cbr stop #Detach tcp and sink agents (not really necessary) $NS at 4.5 $NS detach-agent $n0 $tcp ; $NS detach-agent $n3 $sink #Call the _finish procedure after 5 seconds of simulation time $NS at 5.0 finish #Print CBR packet size and interval puts CBR packet size = [$cbr set packet _size] 49

puts CBR interval = [$cbr set interval] #Run the simulation $NS run

50

Chapter 5
5. Implementation, Results and Analysis
We have implemented two topologies, one is mesh topology and second is Proposed (Custom) topology. We selected number of attribute for the simulation; these attribute are number of links, transmission time, total time, start time, destination time etc. Both topologies run one by one on same machine configuration, snap shots and results are showing in the next section. 5.1 Mesh Topology: 5.1.1 Model No 1 This topology has been simulated using network simulator (Ns-2) version 2.3.It consist of 16 nodes. In this simulation nodes are connected with duplex link. In this topology TCP packet has been sent from node0 to node3.FTP protocol has been used in mesh topology. 5.1.2 Output Generated Via Code

Figure 5.1: Mesh Topology

51

 5.1.3 Flow of Data Generated in Mesh Topology

Figure 5.2: Data Flow In Mesh Topology 5.1.4 Outcomes Table 5.1: Results for mesh topology

S. No. 1. 2. 3. 4. 5.

Packet Starting (ms) 1 3 5 7 10 1.14 1.28 1.281 1.42 1.45

Time Destination (ms) 1.21 1.37 1.371 1.5 1.53

Time Total (ms) 1.27 1.42 1.43 1.57 1.6

Time Transmission Time (ms) 0.13 0.14 0.149 0.15 0.150

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Analysis In above figure we can see that we are having mesh topology with 16 nodes having each node connected with duplex link in above simulation. Transmission refers to the act of sending a packet over a network link. In telecommunication networks, the transmission time, is the amount of time from the beginning until the end of a message transmission. In the case of a digital message, it is the time from the First bit until the last bit of a message has left the transmitting node. It is also defined as the time it takes a message to reach its destination from the source. It is the time between the first bit leaving the sender and the last bit arriving the receiver. The first bit leaves earlier and arrives earlier; the last bit leaves later and arrives later. The transmission time of packets for the mesh topology has been calculated above. Node 0 is transmitting node and Node 3 is receiving node and we have to find time taken to reach a TCP packet to its destination from source.

53

Table5.2: Throughput results for mesh topology

Time(Sec) .1 .2 .3 .4 .5 .6 .7 .8 .9 1.0 Throughput 900 1000 1000 800 960 900 990 1000 999 998

Analysis In above table we can see the throughput of mesh topology on basis of time. Throughput is defined as the average number of successfully delivered data packet on communication network or network node. The throughput of mesh topology increases or decreases on basis of time.

54

1200 1000

T H R O U G H P U T

800 600 Time(Sec) 400 200 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Throughput

TIME

Graph 5.1: Throughput versus time of mesh topology Analysis Graph is showing performance of mesh topology. However the x axis of graph represents the time taken by the packets in forwarding from source node to destination node in seconds and y axis of graph represent the throughput. The throughput increases or decreases on basis of simulation time.

55

Table5.3:End to End delay results for mesh topology Time(Sec) .1 .2 .3 .4 .5 .6 .7 .8 .9 Delay(Sec) .09 .087 .086 .084 .081 .086 .08 .09 .09

Analysis In above table we can see the end to end delay of mesh topology on basis of time. End to End delay is defined as the time a packet takes to travel from source to destination and it is calculated in seconds.

56

1 0.9 0.8

D E 0.7 L 0.6 A Y 0.5

0.4 0.3 0.2 0.1 0 .1 .2 .3 .4 .5 .6 .7 .8 .9 Time(Sec) Delay(Sec)

TIME

Graph 5.2: End to end delay versus time of mesh topology

Analysis Graph is showing performance of mesh topology. However the x axis of graph represents the time taken by the packets in forwarding from source node to destination node in seconds and y axis of graph represent the delay in seconds. The end to end delay increases or decreases on basis of simulation time.

57

5.2 Proposed (Custom) Topology 5.2.1 Model No 2 This topology has been simulated using network simulator (Ns-2) version 2.3.It consist of 16 nodes. In this simulation nodes are connected with duplex link. In this topology TCP packet has been sent from node0 to node3.FTP protocol has been used in proposed topology. 5.2.2 Output Generated Via Code

Figure 5.3: Proposed Topology 5.2.3 Flow of Data Generated in Proposed (custom) Topology

Figure 5.4: Data Flow In Proposed Topology 58

5.2.4 Outcomes Table 5.4: Results for proposed (custom) topology S. No. 1. 2. 3. 1 3 5 Packet Starting (ms) 1.11 1.23 1.24 Time Destination (ms) 1.17 1.3 1.31 Time Total (ms) 1.22 1.34 1.341 Time Transmission time (ms) 0.11 0.11 0.101

4. 5.

7 10

1.35 1.37

1.41 1.43

1.46 1.5

0.11 0.13

Analysis In above figure we can see that we are having proposed topology with 16 nodes having each node connected with duplex link in above simulation. Transmission refers to the act of sending a packet over a network link. In telecommunication networks, the transmission time, is the amount of time from the beginning until the end of a message transmission. In the case of a digital message, it is the time from the First bit until the last bit of a message has left the transmitting node. It is also defined as the time it takes a message to reach its destination from the source. It is the time between the first bit leaving the sender and the last bit arriving the receiver. The first bit leaves earlier and arrives earlier; the last bit leaves later and arrives later. The transmission time of packets for the proposed topology has been calculated above. Node 16 is transmitting node and Node 12 is receiving node and we have to find time taken to reach a TCP packet to its destination from source.

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T I M E

No. of Packet

Graph 5.3: Transmission time of the packet

Analysis Graph 5.1 is showing the performance of the topologies. Moreover the x-axis of the graph represents the number of packets as packet 1, packet 3, packet 5, packet 7 and packet 10 and the Y-axis of the graph represents their respective transmission time in ms. It is clear from the graph that the transmission time of packets for the proposed (custom) topology lies between 0.11 to 0.13 shown by the red line and that of mesh topology lies between 0.13 to 0.150 shown by the blue line. Thus proposed (custom) topology is better than mesh topology. The results achieved in terms of time and reduction in number of links.

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Table5.5: Throughput results for proposed topology Time(Sec) .1 .2 .3 .4 .5 .6 .7 .8 .9 1.0 Throughput 900 990 989 988 995 999 998 1000 1090 1099

Analysis In above table we can see the throughput of proposed topology on basis of time. Throughput is defined as the average number of successfully delivered data packet on communication network or network node. The throughput of mesh topology increases or decreases on basis of time.

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1200

T 1000 H R 800 O U 600 G 400 H P 200 U T 0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Time(Sec) Throughput

TIME

Graph 5.4: Throughput versus time of proposed topology

Analysis Graph is showing performance of proposed topology. However the x axis of graph represents the time taken by the packets in forwarding from source node to destination node in seconds and y axis of graph represent the throughput. The throughput increases or decreases on basis of simulation time.

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Table5.6: End to end delay results for proposed topology Time(Sec) .1 .2 .3 .4 .5 .6 .7 .8 .9 1.0 Delay(Sec) .001 .001 .003 .01 .01 .02 .001 .002 .004 .05

Analysis In above table we can see the end to end delay of proposed topology on basis of time. End to End delay is defined as the time a packet takes to travel from source to destination and it is calculated in seconds.

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1.2 1

D E 0.8 L A 0.6 Y
0.4 0.2 0 1 2 3 4 5 6 7 8 9 10

Time(Sec) Delay(Sec)

TIME

Graph 5.5:End to end delay versus time of proposed topology Analysis Graph is showing performance of proposed topology. However the x axis of graph represents the time taken by the packets in forwarding from source node to destination node in seconds and y axis of graph represent the delay in seconds. The end to end delay increases or decreases on basis of simulation time.

5.2.5 Overall analysis Presented results in above tables are showing the performance of the both topology. From the result it is clearly identifying that the performance of the proposed (custom) topology is batter then mesh topology. Performance of the both topology is depend on the number of packets, if packets are increasing then total transmission time, throughput, end to end delay is also increasing but our proposed (custom) topology is producing less transmission time, throughput, end to end delay as compare mesh topology.

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Chapter 6
6. Conclusion and Future Scope
Network-on-Chip are becoming more and more popular as a solution able to accommodate large number of IP cores, offering an efficient and scalable interconnection network. The results achieved in terms of time and reduction in number of links displayed here is encouraging and motivates to take the work further. As discussed earlier the NoC technology can borrow the tools and techniques from conventional computer network technology with required customization. In future work, we intend to test same on a standard NoC benchmark. The other design parameters on NoC will also be explored. This Project presents a unified approach to the conceptualization of heterogeneous onchip networks. The proposed Network-on-Chip exploration framework combines concepts from the traditional networking design environments with recent system level design methodologies to enable a rapid exploration of architectural alternatives. The presented approach has been successfully applied to the system architecture design of an application specific Network Processing Unit, which performs IP forwarding with Quality of Service support, high simulation speed, modeling efficiency and support in performance. Comparison against the commercial topologies clearly demonstrates the value of customized communication architectures and the proposed exploration framework to rapidly explore and benchmark competing design options. For the considered case-study, the loss of accuracy caused by the packet-based communication paradigm proved to be negligible. In this research, we proposed a novel low complexity proposed (custom) topology for design of application specific custom on-chip interconnection architectures. We experimented with many representative multimedia benchmarks to demonstrate the superior quality of proposed (custom) design. Due to their low complexity, proposed topology was able to generate results for all benchmarks in good transmission time. We compared proposed (custom) topology with existing topology whose computational complexity is not bounded. Overall, our proposed topology is far far better then mesh topology. As discussed in the results above. In future work we will focus on the time and size of the chip more effectively. 65

Chapter 7
7. References
[1] M. Horowitz, R. Ho, and K. Mai, The future of wires, Proc. IEEE, vol. 89, pp. 490504, Apr 2001. [2] Radu Marchulescu et al. outstanding research problems in NOC design: system, micro architecture and circuit perspectives IEEE transaction on computer aided design of integrated circuits and systems vol. 8, No. 1, Jan 2009. [3] Murali, S. P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. D. Micheli and L.Rao Design of application-specific networks on chips with floorplan information,in: Proc. of the International Conf. on Computer-Aided Design, 2006. [4] Avinoam Kolodny & Li-Shiuan Peh, IEEE transactions on VLSI systems, vol 17, no. 3, Mar 2009. [5] Salminen et al. Survey of Network-on-Chip Proposals, OCP-IP, Mar 2008. [6] W. J. Dally and B. Towles. Route packets, not wires: On-chip interconnection networks. In Proceedings of the 38th Design Automation Conference, 2001. [7] P. Kermani and L. Kleinrock. Virtual cut-through: A new computer communication switching technique. Computer Networks, 3:267-289, January 1979. [8] M. Millberg, E. Nilsson, R. Thid, and A. Jantsch. Guaranteed bandwidh using looped containers in temporally disjoint networks within the Nostrum network on chip. In Proceedings of the Design Automation and Test in Europe Conference, February 2004. [9] J. T. Brassil and R. L. Cruz. Bounds on maximum delay in networks with de_ection routing. IEEE Transactions on Parallel and Distributed Systems, 6(7):724-732, July 1995. [10] K. Goossens, J. Dielissen, J. Meerbergen, P. Poplavko, A Radulescu, E. Rijpkema, E. Waterlander, and P. Wielage. Networks on Chip, chapter Guaranteeing The Quality of Services. Kluwer Academic Publisher, 2003. [11] S. Mahadevan, F. Angiolini, M. Storgaard, R. Olsen, J. Sparso, and J. Mad-sen. A network traffic generator model for fast network-on-chip simulation. In Proceedings of the Design, Automation and Test in Europe Conference, pages 780-785, March 2005. [12] S. K. Kunzli, F. Poletti, L. Benini, and L. Thiele. Combining simulation an formal 66

method system analysis. In Proceedings of Design, Automation and Test in Europe conference.Pages1 Pages 1-6 March 2006. [13] A. Benveniste and Gerry. an approach to reactive and realtime systems. [14] David Atienza, Federico Angiolini, Srinivasan Murali,Antonio Pullini, Luca Benini and Giovanni De Micheli.Network-On-Chip design and Synthesis Outlook. [15] Partha Pratim, Michael Jones ,Andre lvanov, Cristian Grecu and Resve Saleh, Performance Evaluation and design Trade-Offs for Network On Chip Interconnect Architectures. Vol 54 No-8 Aug 2005. [16] Shafi Patel, Parandkar , Sumant Katiyal and Ankit Agrawal. Exploring Alternative Topologies For Network-On-Chip Architecture.

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List Of Abbreviations
SoC-System on Chip NoC- Network on chip VLSI-Very Large Scale Integration MCSOC-Microcontroller system on chip SPIN-Scalable Programmable Integrated Network CLICH-Chip Level Integration Of Heterogeneous Element TCP-Transmission Control Protocol FTP-File Transfer Protocol UDP-User Datagram Protocol CBR-Constant Bit Rate TCL-Tool Command Language OTcl-Object Oriented Based On Tool Command Language Ns-2-Network Simulation Version 2.34 Nf-Network Function

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