IDEAS FOR DESIGN

resistance. With the given 0.1- value, the output current is limited to 50 A. In a short-circuit situation, capacitor C1 can be fully (and safely) discharged in the PowerFET. Reverse voltages caused by inductive loads are eliminated by D1. When the circuit isnt operating, R14 discharges C1 for safety reasons. Circuit layout is very importanta groundplane is needed to keep inductance low. C1 must be a low-inductance pulse capacitor. Even the FET driver IC2 needs a low-inductance layout and decoupling. During the leading-edge gate currents, up to 2 A are needed to charge the FET input capacitance. Resistors R1 and R2 have to be made of at least 10 paralleled discretes to get a low series inductance. R4 and C3 compensate for the remaining inductance in R2 (the value of C3 can be changed for this). C2, R5, R6, and R7 form a snubber network to protect the FET against voltage spikes. The values for the voltage and current monitor levels are given for a 50- load. Higher currents can be obtained by duplicating the IC2-Q1-R1 stage and connecting them in parallel. R1 helps to equalize the current for each stage. A 100-A pulser has been successfully built in this manner.

Circle 520

High-Voltage Power Pulse Circuit

R.N. SCHOUTEN Faculty of Applied Physics, DIMES, Delft University of Technology, P.O. Box 5046, 2600A Delft, The Netherlands.

ast rise-time high-voltage pulses have many uses ranging from EMC testing to device characterization.The simple, low-cost circuit described here deals with the latter. Its able to generate 0- to 1000-V pulses with currents up to 50 A, and a rise time of 100 ns for 800 V/30 A. The output can withstand short circuits, and capacitive and inductive loads. Pulse length and repetition rate are determined by an optically isolated TTL-input signal. Commercial equipment like pulse/function generators or a PC can be connected to this input. The pulses amplitude is set by the HV supply; a low-cost photomultiplier-type supply (0, 5 ..5 mA) can be used when repetition rates are below 20 Hz. The circuit operates as follows: when applying the HV supply, C1 is charged up to a voltage HV via R1

and D1 (see the figure). A 0-V control signal keeps the PowerFET Q1 in the off state. A 5-V signal on the control input operates the driver IC2, from which a 12-V signal is presented on the gate of the PowerFET Q1, bringing it into conductance. The output of the circuit becomes HV volts as the negative terminal of C1 is now grounded. The pulse ends by making the control signal 0 V. Useful pulse length is limited by he voltage drop during the pulse (caused by discharging C1) and by the 100-s/64-A save limit of the PowerFET. For the values shown, the circuit voltage drop is 10 V for a 1-s, 10-A pulse. The short-circuit and overload protection is based on R1. When the output current is rising, the effective gate-source voltage of the PowerFET diminishes, enlarging the FET

IC1 6N135 0/+5 V Control In 2 R16 200 D2 1N4148 3 4 7 6 1 8

+12 V

C6 100 nF

STE16N100 SGS-Thomson Q1 R8 2k C1 1 F 1 kV C2 10 nF 1 kV R11 330

HV Pulse output

R17 5.6k IC2 MAX626 1 8 7 6 5 C4 100 nF R1 0.1

R9 2k R5 33 R10 2k +12 V HV suppl R6 33 D1 RURP8100 Harris R7 33

R12 330

R2 0.02 C3 22 nF R4 47

R3 4.7k

5 2 3 4

R15 56 1 mV/V

10 mV/A

C5 10 F

R18 10M 1200 V

R14 2.2

Fast risetime pulses of 0 to 1000 V, with currents up to 50 A, can be generated by this simple, low-cost high-voltage power pulse circuit.

ELECTRONIC DESIGN / DECEMBER 1, 1997

R13 330 Voltage monitor

Current monitor

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