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FQA33N10L

September 2000

QFET
FQA33N10L
100V LOGIC N-Channel MOSFET
General Description
These N-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for low voltage applications such as high efficiency switching DC/DC converters, and DC motor control.

TM

Features
36A, 100V, RDS(on) = 0.052 @VGS = 10 V Low gate charge ( typical 30 nC) Low Crss ( typical 70 pF) Fast switching 100% avalanche tested Improved dv/dt capability 175C maximum junction temperature rating

D
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"

G! G DS

! "
" "

TO-3P
FQA Series

Absolute Maximum Ratings


Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TJ, TSTG TL

TC = 25C unless otherwise noted

Parameter Drain-Source Voltage - Continuous (TC = 25C) Drain Current - Continuous (TC = 100C) Drain Current - Pulsed
(Note 1)

FQA33N10L 100 36 25.5 144 20


(Note 2) (Note 1) (Note 1) (Note 3)

Units V A A A V mJ A mJ V/ns W W/C C C

Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TC = 25C)

430 36 16.3 6.0 163 1.09 -55 to +175 300

- Derate above 25C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds

Thermal Characteristics
Symbol RJC RCS RJA Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Case-to-Sink Thermal Resistance, Junction-to-Ambient Typ -0.24 -Max 0.92 -40 Units C/W C/W C/W

2000 Fairchild Semiconductor International

Rev. A, September 2000

FQA33N10L

Electrical Characteristics
Symbol Parameter

TC = 25C unless otherwise noted

Test Conditions

Min

Typ

Max

Units

Off Characteristics
BVDSS BVDSS / TJ IDSS IGSSF IGSSR Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse VGS = 0 V, ID = 250 A ID = 250 A, Referenced to 25C VDS = 100 V, VGS = 0 V VDS = 80 V, TC = 150C VGS = 20 V, VDS = 0 V VGS = -20 V, VDS = 0 V 100 ------0.09 ------1 10 100 -100 V V/C A A nA nA

On Characteristics
VGS(th) RDS(on) gFS Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance VDS = VGS, ID = 250 A VGS = 10 V, ID = 18 A VGS = 5 V, ID = 18 A VDS = 30 V, ID = 18 A
(Note 4)

1.0 ---

-0.039 0.043 28

2.0 0.052 0.055 --

V S

Dynamic Characteristics
Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz ---1250 305 70 1630 400 90 pF pF pF

Switching Characteristics
td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 80 V, ID = 33 A, VGS = 5 V
(Note 4, 5)

VDD = 50 V, ID = 33 A, RG = 25
(Note 4, 5)

--------

17 470 70 120 30 4.7 16

45 950 150 250 40 ---

ns ns ns ns nC nC nC

Drain-Source Diode Characteristics and Maximum Ratings


IS ISM VSD trr Qrr Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 36 A Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge VGS = 0 V, IS = 33 A, dIF / dt = 100 A/s
(Note 4) (Note 6)

------

---90 0.26

36 144 1.5 ---

A A V ns C

Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 0.5mH, IAS = 33A, VDD = 25V, RG = 25 , Starting TJ = 25C 3. ISD 33A, di/dt 300A/s, VDD BVDSS, Starting TJ = 25C 4. Pulse Test : Pulse width 300s, Duty cycle 2% 5. Essentially independent of operating temperature

2000 Fairchild Semiconductor International

Rev. A, September 2000

FQA33N10L

Typical Characteristics

10

ID, Drain Current [A]

ID, Drain Current [A]

VGS 10.0 V 8.0 V 6.0 V 5.0 V 4.5 V 4.0 V 3.5 V Bottom : 3.0 V Top :

10

10

175

10

25
0

10

-55
Notes : 1. VDS = 30V 2. 250 s Pulse Test

Notes : 1. 250 s Pulse Test 2. TC = 25

10 -1 10

10

10

10

-1

10

VDS, Drain-Source Voltage [V]

VGS, Gate-Source Voltage [V]

Figure 1. On-Region Characteristics

Figure 2. Transfer Characteristics

0.20 10
2

0.16

RDS(ON) [ ], Drain-Source On-Resistance

IDR , Reverse Drain Current [A]

VGS = 5V
0.12

10

VGS = 10V
0.08

10

0.04
Note : TJ = 25

175

25

Notes : 1. VGS = 0V 2. 250 s Pulse Test

0.00 0 30 60 90 120

10

-1

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

ID, Drain Current [A]

VSD, Source-Drain voltage [V]

Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage

Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature

3600
Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd

12

3000

10

VGS, Gate-Source Voltage [V]

VDS = 50V
8

2400

Capacitance [pF]

VDS = 80V

1800

Ciss Coss

Notes : 1. VGS = 0 V 2. f = 1 MHz

1200

Crss
600

2
Note : ID = 33A

0 -1 10

0 10
0

10

10

20

30

40

50

VDS, Drain-Source Voltage [V]

QG, Total Gate Charge [nC]

Figure 5. Capacitance Characteristics

Figure 6. Gate Charge Characteristics

2000 Fairchild Semiconductor International

Rev. A, September 2000

FQA33N10L

Typical Characteristics

(Continued)

1.2

3.0

2.5

BV DSS , (Normalized) Drain-Source Breakdown Voltage

RDS(ON) , (Normalized) Drain-Source On-Resistance

1.1

2.0

1.0

1.5

1.0

0.9

Notes : 1. VGS = 0 V 2. ID = 250 A

0.5

Notes : 1. VGS = 10 V 2. ID = 16.5 A

0.8 -100

-50

50

100
o

150

200

0.0 -100

-50

50

100
o

150

200

TJ, Junction Temperature [ C]

TJ, Junction Temperature [ C]

Figure 7. Breakdown Voltage Variation vs. Temperature

Figure 8. On-Resistance Variation vs. Temperature

40
Operation in This Area is Limited by R DS(on)
2

10

30

1 ms 10 ms
10
1

ID , Drain Current [A]


2

ID , Drain Current [A]

100 s

20

DC

Notes : 1. TC = 25 C
o

10

10

2. TJ = 175 C 3. Single Pulse


0

10

10

10

0 25

50

75

100

125

150

175

VDS, Drain-Source Voltage [V]

TC, Case Temperature []

Figure 9. Maximum Safe Operating Area

Figure 10. Maximum Drain Current vs. Case Temperature

(t), T h e rm a l R e s p o n s e

10

D = 0 .5
N otes : 1 . Z J C( t ) = 0 . 9 2 /W M a x . 2 . D u t y F a c t o r , D = t 1 /t 2 3 . T J M - T C = P D M * Z J C( t )

0 .2
10
-1

0 .1 0 .0 5 0 .0 2 0 .0 1

PDM t1
s in g le p u ls e

JC

t2

10

-2

10

-5

10

-4

10

-3

10

-2

10

-1

10

10

t1 , S q u a r e W a v e P u ls e D u r a tio n [s e c ]

Figure 11. Transient Thermal Response Curve

2000 Fairchild Semiconductor International

Rev. A, September 2000

FQA33N10L

Gate Charge Test Circuit & Waveform

50K 12V 200nF 300nF

Same Type as DUT VDS

VGS Qg 5V Qgs Qgd

VGS

DUT
3mA

Charge

Resistive Switching Test Circuit & Waveforms

VDS VGS RG

RL VDD

VDS

90%

5V

DUT

VGS

10%

td(on) t on

tr

td(off) t off

tf

Unclamped Inductive Switching Test Circuit & Waveforms

L VDS ID RG 10V
tp

BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD BVDSS IAS VDD ID (t) VDD
tp

DUT

VDS (t) Time

2000 Fairchild Semiconductor International

Rev. A, September 2000

FQA33N10L

Peak Diode Recovery dv/dt Test Circuit & Waveforms

DUT

+ VDS _

I SD L Driver RG
Same Type as DUT

VDD

VGS

dv/dt controlled by RG ISD controlled by pulse period

VGS ( Driver )

Gate Pulse Width D = -------------------------Gate Pulse Period

10V

IFM , Body Diode Forward Current

I SD ( DUT ) IRM

di/dt

Body Diode Reverse Current

VDS ( DUT )

Body Diode Recovery dv/dt

VSD

VDD

Body Diode Forward Voltage Drop

2000 Fairchild Semiconductor International

Rev. A, September 2000

FQA33N10L

Package Dimensions

TO-3P
15.60 0.20 3.80 0.20 13.60 0.20 3.20 0.10 9.60 0.20 4.80 0.20 1.50 0.05
+0.15

12.76 0.20

19.90 0.20

16.50 0.30

3.00 0.20 1.00 0.20

3.50 0.20

2.00 0.20

13.90 0.20

23.40 0.20

18.70 0.20

1.40 0.20

5.45TYP [5.45 0.30]

5.45TYP [5.45 0.30]

0.60 0.05

+0.15

2000 Fairchild Semiconductor International

Rev. A, September 2000

TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx Bottomless CoolFET CROSSVOLT DOME E2CMOS EnSigna FACT FACT Quiet Series FAST
DISCLAIMER

FASTr GlobalOptoisolator GTO HiSeC ISOPLANAR MICROWIRE OPTOLOGIC OPTOPLANAR POP PowerTrench

QFET QS QT Optoelectronics Quiet Series SuperSOT-3 SuperSOT-6 SuperSOT-8 SyncFET TinyLogic UHC

VCX

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY


FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS Definition of Terms


Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Preliminary

No Identification Needed

Full Production

Obsolete

Not In Production

2000 Fairchild Semiconductor International

Rev. F1