Three-phase soft-switched PWM inverter for motor drive application

J. Shukla and B.G. Fernandes Abstract: A novel soft-switched inverter topology in which three mutually coupled inductors at a time are involved in the resonance process is proposed. By the introduction of magnetic coupling between three resonant inductors, the zero-voltage instants for the inverter can be generated by one auxiliary switch. Also, the resonant energy can be recycled, and the maximum voltage stress on the auxiliary circuit diode components is conned to the DC-link clamp voltage level. The DC link can be clamped to 1.11.3 times the DC-source value. This is unlike the soft-switched inverter in which two mutually coupled inductors are at a time are involved in a resonance process [14], wherein the clamping diode experiences voltage stress of the order of 11 per unit when clamping the DC-link voltage at 1.1 per unit. The proposed inverter also provides pulse-width modulated operation. An analysis of this novel quasi-resonant DC-link inverter topology is presented to reveal its softswitching characteristics. Simulation and laboratory experiments are performed to validate the analysis.

Introduction

Quasi-resonant inverters offer several advantages compared with resonant DC-link inverters [13] with regard to resonant link design and control, device rating requirements and use of pulse width modulation (PWM). Over the years, extensive research work has been carried out in the eld of quasi-resonant DC-Link (QRDCL) PWM inverters [417]. The QRDCL inverter schemes generate zero-voltage (ZV) instants in the DC link at controllable instants that can be synchronised with any PWM transition command, thus ensuring a ZV switching condition of inverter devices. As a result, these inverters can be operated at high switching frequencies with high efciency. Among the different types of QRDCL inverter scheme reported in the literature, the category of inverters in which an inductor is connected between the DC link and the DC source are particularly suited for high-frequency and highpower applications [1017]. This is owing to the fact that these inverters do not have a high-frequency resonant switch in the main power path of the inverter. However, higher DC-link voltage stress [11], a high auxiliary switching device count [13] and the requirement of a separate lowvoltage DC source to clamp the DC link [1517] are the main limitations of these schemes. One of the QRDCL inverter topology falling into this category is the passively clamped QRDCL (PCQRDCL) inverter reported in [14]. This topology (shown in Fig. 1a) can be considered to be a state-of-the-art QRDCL scheme satisfying most of the essential requirements, such as low clamp factor, simple resonance control, guaranteed zerolink voltage condition, PWM capability, use of only one auxiliary switch and recycling of resonant energy. It was shown that, by the introduction of magnetic coupling
r The Institution of Engineering and Technology 2007 doi:10.1049/iet-epa:20050539 Paper rst received 31st August 2005 and in nal revised form 25th May 2006 The authors are with the Electrical Engineering Department, Indian Institute of Technology Bombay, Powai, Mumbai-400076, India E-mail: jagjit@ee.iitb.ac.in, jagjitshukla@yahoo.com IET Electr. Power Appl., Vol. 1, No. 1, January 2007

between two resonant inductors, the zero-voltage instants can be generated by only one auxiliary switch. Also, the DC link can be clamped at 1.11.3 per unit, and resonant energy can be recycled. The only drawback of this scheme was the high reverse voltage requirement of the clamp diode. The voltage-blocking capability of this diode is of the order of 11 per unit for a clamping factor of 1.1 per unit. This problem can be solved by use of a separate, low-voltage DC source. However, realisation of this low-voltage DC source is itself a problem. In the case of a battery-operated inverter, the clamp diode can be connected to a separate low-voltage battery group. In the absence of a battery source, the realisation, of a separate, low-voltage DC source becomes difcult. Another possible solution could be to use a DCDC regulator or a simple R-C parallel circuit to maintain low voltage (refer to Fig. 1b). The use of a DCDC regulator increases the component count and control complexity. Also, if the DCDC regulator is not capable of feeding the processes resonant energy back to the DC source, then this energy is dissipated in resistor. This reduces overall efciency of the inverter. An optimum strategy in which DCDC regulator maintains a separate low voltage for clamping purposes and also feeds back the clamp energy to the DC source has yet not been reported in the literature. Hence, the objective of this paper is to design a QRDCL inverter circuit using one auxiliary switch, in which the maximum voltage stress in all semiconductor diodes is conned to the DC-link clamp voltage level Vc. Also, the resonant energy associated with the clamping action is recovered without the use of an extra switching circuit. Such a QRDCL inverter scheme is shown in Fig. 2, in which three mutually coupled inductors are used to achieve the above features. Only one auxiliary switch is used to generate zero-voltage instants for the inverter switching devices. 2 Principle of operation

Through the introduction of magnetic coupling between three resonant inductors (L1, L2 and L3), as shown in Fig. 2, the zero-voltage instants for the inverter can be
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i3
+

L1

i1

IO L2

D3 i1 L1

IO

D3

L3 i3 S2

i2
+

Sa VC Sa

Sb

Sc
+

L2 S2

i2
+

Sa VC Sa

Sb

Sc

Vs C D2

Vs Sb Sc C D2

Sb

Sc

IM
a b

IM

Fig. 1

Inverters

a Passively clamped QRDCL inverter with mutually coupled inductors proposed in [14] b Quasi-resonant inverter using separate low-voltage DC source for clamping purpose [14]

Fig. 2 Proposed quasi-resonant DC-link inverter using three coupled inductors

i1 L1
+

D1

VC
+

CF L2 i2 CR S2 D2
+

D3

Vs

VC

D
R

Io L3 i3

Fig. 3

Simplied equivalent circuit of proposed QRDCL inverter

generated by one auxiliary switch. Also, the current in the auxiliary inductor L2 can now reverse during the resonant cycle. Thus switch S2 can be turned off under the ZV condition. Clamping is provided by a large lter capacitor CF, which acts as a low-voltage DC source whose average current in steady state is zero. The entire resonant energy associated with the clamping circuit is recycled. This can be easily observed from the waveform of current iCF owing through CF, as shown in Fig. 4. At steady state, the area enclosed by its discharging current (area A1) is equal to the area enclosed by its charging current (area A2). The voltage across CF vCF attains a value equal to K 1Vs, where K is the clamping factor and lies in the range of 1.11.3. This DC voltage across CF is analogous to a separate lowvoltage DC source, as seen in a few QRDCL schemes reported in the literature [1417]. Assuming that the inverter is feeding an inductive load (which can be represented by a constant current source), the steady-state DC voltage across
94

Fig. 4

Resonant link waveforms

CF depends on the values of L1, L2, L3 and CR and the coupling coefcients of mutually coupled inductors k12 , k23 and k13 .
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Analysis and modes of operation

as follows:

Operation of the proposed QRDCL inverter can be explained by reference to Figs. 25. The various modes of circuit operation are described as follows.

 v CR t t 1

Vs L1 L2 2M12

L2 M12 L1 M12 cos ot t1 3  i1 t t1 Io ot t1  i 2 t t 1  Vs oL1 L2 2M12 ! 4 Vs oL1 L2 2M12 " # L1 M12 2 o t t 1 sin ot t1 2 L2 L2 M12 

3.1 Mode 0 t0 t t1 : pseudo steadystate mode (S2, D1, D2 and D3 off)

During this mode, the inverter is said to be in pseudo steady-state mode. The resonant circuit formed by L1 and CR oscillates. The voltage vCR across capacitor CR alternates between Vc KVs and 2 K Vs. Also, the inductor current i1 oscillates around the inverter input current (represented magnitude of this by a constant current source Io ), and the p ripple is Vs Vc=o1 L1 , where o1 1= L1 CR . The DClink voltage vCR settles to Vs owing to the nite resistance of the resonant components. This mode of operation ends at time t1 , when S2 is turned on under the ZV condition to reduce the DC-link voltage vCR to zero. If we neglect the resistance of the circuit, the state equations of this mode are given by iL1 t t0 Vs Vc=R01 sino1 t t0 Io 1 vCR t t0 Vs Vs Vc coso1 t t0 2 p p where R01 L1 =CR and o1 1= L1 CR . Initial conditions for this mode are vCR t0 Vc and iL1 t0 Io .

L1 M12 L2 M12 sin ot t1 2 L1 L2 M12

3.2 Mode 1 t1 t t2 : link voltage reduces sinusoidally (S2 on; D1, D2 and D3 off)
With S2 on, the resonance between L1, L2 and CR causes CR to discharge. Current owing through L1 decreases sinusoidally, and that owing through L2 increases sinusoidally. When voltage across CR vCR becomes equal to the sum of vCF and the voltage induced in L3, D3 turns on, and this mode of operation ends. The equations for link voltage and currents during this mode can be derived

5 p 2 , L12 L1 L2 M12 where, o 1= L12 CRp =L1 L2 M12 and M12 k12 L1 L2 . Initial conditions for this mode are vCR t1 Vs, i1 t1 Io , and i2 t1 0. The duration of this mode is given as    1 A cos1 t2 t1 6 o B where A Vc M23 M13 L2 M12 Vs L1 L2 2M12

2 VsM23 L1 M12 M13 L1 M12 L2 M12

2 L1 M12 L1 L2 M12 2 L1 L2 2M12 L1 L2 M12

Fig. 5

Equivalent circuits during various modes of operation

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3.3 Mode 2 t2 t t3 : link voltage continues to decrease sinusoidally (S2 and D3 on; D1 and D2 off)
A resonant circuit consisting of mutually coupled inductors L1, L2, L3 and CR is formed. Capacitor CR continues to discharge. This mode of operation ends when CR discharges to zero. The equations governing this mode are Z t di1 di2 di3 1 M12 M13 i1 t L1 dt dt dt CR 0 i3 t i2 t Io dt Vs 7 Z t di2 di1 di3 1 M21 M23 i 1 t i 3 t L2 dt dt dt CR 0 i2 t Io dt 0 8 Z t di3 di1 di2 1 M31 M32 L3 i1 t dt dt dt CR 0 i3 t i2 t Io dt vCF 9 p p where M13 k13 L1 L3 , M23 k23 L2 L3 , M12 M21 , M23 M32 , and M13 M31 . Initial conditions for this mode are i1 i1 t2 , i2 i2 t2 , i3 0 and vCR vCR t2 . It was found that this mode of operation occurs for a negligible small interval of time. From Fig. 4, it can be observed that the duration of this mode is very small compared with the time taken by the DC-link voltage to reduce to zero from source voltage value (which itself is small). Thus the change in currents i1 , i2 and i3 during this mode is negligibly small and can be neglected. Also, as the area enclosed by current iCF during this mode is negligible, the contribution of this mode towards steady-state DC-voltage build-up across CF is neglected. A situation in which three mutually coupled inductors are involved in a resonance process with CR occurs twice during the entire circuit operation. One such situation occurs during this mode, and another occurs during mode 4 of operation (discussed later). During mode 4 of operation, such a situation lasts for a longer duration and, hence, is not neglected.

i3 t t3 i3 t2 2 t t3 L1 L2 M12 vCF L2 M13 M12 M23 Vs D 13

2 2 where D L1 L2 L3 L3 M12 L2 M13 2M12 M13 M23 2 L1 M23 . Initial conditions for this mode are i1 i1 t2 , i2 i2 t2 , i3 t2 0 and vCR 0. It should be noted that the initial conditions for currents i1 ; i2 and i3 are their respective values at the end of mode 1 (the effect of mode 2 is neglected), and that of vCR is zero. The duration of this mode is given as

TZero t4 t3

i2 t2 Io i1 t2 i3 t2 D 14 vCF C Vs E

where C L2 M13 M12 M23 M13 M12 L1 M23 L1 L2 2 2 M12 , and E L2 L3 M23 L3 M12 M13 M23 L2 M13 M12 M23 . The expression for the area enclosed by current iCF i3 during this mode is given as 2 2 t4 t3 L1 L2 vCF M12 vCF L2 M13 Vs iCF ;area;M3 M12 M23 Vs 2D 15

3.5 Mode 4 t4 t t5 : capacitor CR charges: stage 1 (S2 on then off; D2 off then on; D3 on; D1 off)
During this mode of operation, CR charges owing to the resonance caused between mutually coupled inductors L1, L2, L3 and CR . Capacitor CF continues to discharge. The state equations for this mode are the same as that of mode 2, except for the initial conditions. If circuit parameters and initial conditions are used, the analytical solution of the mathematical equations governing this mode becomes difcult to solve manually. However, if the numerical values of a few circuit parameters are known a priori, these equations can be solved with ease. Software packages such as Mathematica can be used as an aid to solve the equations. As an example, if numerical value of circuit parameters such as Vs 600, Io 50, L1 281 mH, L2 29 mH, L3 43:8 mH, k12 0:9, k13 0:6, k23 0:5, CR 22 nF are used, with symbolic notations for vCF , i1 t4 , i2 t4 , i3 t4 , the state equations and the expression for area enclosed by iCF are given in Appendix 9. Note that, when the above equations are solved, the capacitor voltage vCF and initial conditions for currents at the start of this mode i1 t4 ; i2 t4 ; i3 t4 are kept as symbolic notations. This helps to solve the circuit from the previous mode to the next mode of operation, and to prove the concept of steady-state DC-voltage build-up across CF, on which the entire circuit operation is based (discussed in the following Section). If (29) is plotted with respect to time, there will be two zero-crossings or solutions (see Fig. 4). This implies that i2 reverses its direction, making the antiparallel diode of switch S2 D2 conduct for a short interval. When D2 is conducting, S2 is turned off under zero-voltage and zero-current switching conditions. This mode of operation ends when D2 turns off.

3.4 Mode 3 t3 t t4 : zero link voltage condition (S2 on and D2 off; inverter freewheeling diodes on; D3 on; D1 off)
During this interval, the freewheeling diodes in the inverter legs represented by D start conducting. Link voltage is clamped at 0 V, and the inverter devices can be turned on/off under zero-voltage condition. A linearly increasing discharge current iCF ows out of the positive electrode of capacitor CF. Current owing through L1 increases linearly, and that owing through L2 decreases linearly. Owing to magnetic coupling between L1 and L2, current owing through freewheeling diodes across the PWM inverter switches decreases linearly. This mode of operation ends when current owing through the freewheeling diodes reduces to zero. The equation for link voltage and currents can be derived as v CR t t 3 0 10

i1 t t3 i1 t2 2 t t3 L2 M13 M12 M23 vCF L2 L3 M23 Vs D 11 i 2 t t 3 i 2 t 2 t t3 L1 M23 M12 M13 vCF M13 M23 L3 M12 Vs D 12

3.6 Mode 5 t5 t t6 : capacitor CR charges: stage 2 (S2, D1 and D2 off; D3 on)

During this mode of operation, a resonant circuit consisting of L1, L3 and CR is formed. Voltage across CR continues to increase. This mode ends when the sinusoidally decreasing discharge current iCF decreases to zero. At this instant,
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D3 turns off. The equations governing this mode are given as Z t di1 di3 1 M13 i1 t i3 t Io dt Vs 16 L1 dt dt CR 0 di3 di1 1 M13 L3 dt dt CR Z
0 t

3.8 Mode 7 t7 t t8 : clamping action (S2, D2 and D3 off; D1 on)

During this mode of operation, the DC-link voltage vCR is clamped at Vs vCF KVs. Current owing through L1 i1 is fed to CF by diode D1. This current decreases linearly. This mode of operation ends when i1 becomes equal to inverter load current Io . After this mode of operation, the DC link returns to mode 0 of operation. The link current and voltage equations are iL1 t t7 Vs Vc t t7 iL1 t7 L1 21 22

i1 t i3 t Io dt vCF 17

The state equations during this mode are derived based on the same arguments made in the previous mode of operation. The initial conditions during this mode are: vCR vCR t5 , i1 i1 t5 , i2 i2 t5 and i3 i3 t5 . The state equations and the expression for area enclosed by iCF during this mode are given in Appendix 9.

vCR t t7 Vs vCF The duration of this mode is given as Io i1 t7 L1 Vs Vs vCF

3.7 Mode 6 t6 t t7 : capacitor CR charges: stage 3 (S2, D1, D2 and D3 off)

During this mode of operation, a resonance circuit consisting of L1 and CR is formed. Voltage across CR continues to increase. Current owing through L1 decreases sinusoidally. This mode ends when the voltage across CR reaches the clamp voltage level KVs Vs vCF . The link current and voltage equations are iL1 t t6 Io i1 t6 Io coso1 t t6 Vs vCR t6 sino1 t t6 R01 18

t8 t7

23

The expression for the area enclosed by current iCF during this mode is given as iCF ;area;M7 0:5t8 t7 i1 t7 Io 4 Link design and control scheme 24

vCR t t6 i1 t6 Io R01 sino1 t t6 Vs vCR t6 coso1 t t6 Vs 19 The duration of this mode is given as q1 0 2 ab 2ab2 4b2 c2 a2 c2 1 A t7 t6 tan1 @ 2b2 c2 o1 20 where a Vs vCR t6 , b i1 t6 Io R01 and c vCF .

The design of QRDCL topology with three coupled inductors shown in Fig. 2 involves the selection of parameters L1, L2, L3, CR , M12 , M23 and M13 to the satisfy the desired link waveform specications such as dv=dt, di=dt, value of K, peak currents in L1, L2, L3 and TZero . The design process for the proposed QRDCL circuit topology is iterative in nature, wherein a simulation study or calculations based on (1)(24) are required to adjust the link parameters and to verify that the design specications are met. The following design guidelines are recommended for the design of the topology. Initially, suitable values for L1 and CR are chosen. Inductance L1 consists of the sum of DC-source inductance and externally connected inductance between the DC source and the DC link. It prevents a signicant rise in

Fig. 6

Plot of vCF against iCF ;area;average , TZero and zero-voltage turn-off time available for S2
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source current above load current value Io when the DC-link voltage reduces below Vs. Hence, L1 in the range of 100500 mH is selected. Capacitance CR consists of stray capacitance across the PWM inverter DC-busbar terminals and externally connected resonant capacitor. Generally, CR in the range of 10100 mH is selected. Inductances L2 and L3 and coupling coefcients k12 , k23 and k13 are chosen in the following range: L2 0:1 L1 , L3 1:5 L2 , k12 maximum possible (usually k12 in the range of 0.850.95 can be obtained), k13 0:6k12 and k23 minimum possible (usually k23 in the range of 0.40.5 can be obtained). Practical considerations limit the minimum value of k23 that can be obtained. Once all circuit parameter values are chosen based on the above-mentioned guidelines, the circuit equations for various modes of operation are executed to check whether essentially required specications are met (such as the steady-state DC-voltage build-up across CF, which decides the clamping factor K of the inverter DC-link voltage). Capacitor CF is chosen such that constant voltage with negligible ripple is maintained across it. As the average value of the charging and discharging current owing through CF is negligibly small (of the order of 0.250.5 A), an empirical value in the range

of 5005000 times the value of CR is sufcient to give satisfactory performance. Thus, under steady-state conditions, when steady DC voltage builds up across CF, the following condition must be satised: iCF ;area;average iCF ;area;M7 iCF ;area;M3 iCF ;area;M4 iCF ;area;M5 0 25

where, iCF ;area;M7 is the area enclosed by iCF during mode 7. When the average area enclosed by the current through CF iCF ;area;average is calculated, a suitable value for vCF % 0:1Vs is assumed, and (15), (32), (36), (24) and (25) are evaluated. This process is repeated by either the increasing (if iCF ;area;average 40) or decreasing (if iCF ;area:average o0) of the value of vCF until the value of iCF ;area;average becomes zero. The value of vCF at which iCF ;area:average becomes zero is the value of the steady-state voltage across CF . The proposed circuit with the parameters given in mode 4 is solved using MATLAB, and the plot of vCF against iCF ;area;average is shown in Fig. 6. It can be observed that the steady-state voltage attained across CF is 121 V. Figure 6 also shows the plot of the zero DC-link voltage period and zero-voltage turn-off period available for S2.

Fig. 7

Simulation results

a M12 is increased from 81.5 mH to 85.5 mH in steps of 2 mH b M13 is increased from 66.56 mH to 74.56 mH in steps of 4 mH c M23 is increased from 17.81 mH to 21.81 mH in steps of 2 mH d CR is increased from 22 nF to 28 nF in steps of 3 nF
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For the same circuit, the effect of change in various circuit parameters (M12 , M13 , M23 , CR , L1, L2 and L3) was studied using a SABER simulator. The simulated waveforms for each individual parameter change are shown in Figs. 7 and 8, respectively. In this study, each circuit parameter was given an incremental change (while other parameters were kept constant), and the results were plotted. These results are enumerated in Table 1 and can help in ne-tuning the circuit parameters until the required specications are met. For example, if the zero-voltage turnoff switching property for S2 is not satised during mode 4 of operation, then M12 should be given an incremental change until this property is satised. It is found that average current stress on additional switching devices such as S2, D1 and D3 are negligibly small. From the simulation study on the proposed circuit with the parameters given in mode 4, the average values of current owing through S2, D1 and D3 are found to be 0.46 A, 0.3 A and 0.26 A, respectively, and their peak values of currents owing are found to be 24 A, 2.5 A and 8 A, respectively (see Fig. 4). Thus S2, D1 and D3 are selected based on their

Table 1: Effect of parameter variation on circuit performance

Circuit parameter Zero-voltage time period Tzero Clamp voltage Available level Vs vCF zero-voltage turn-off period for S2 negligible change decreases increases decreases decreases marginal increase increases increases increases negligible change decreases decreases marginal increase negligible change

k12 m k13 m k23 m CR m L1 m L2 m L3 m

decreases negligible change negligible change increases increases decreases negligible change

Fig. 8

Simulation results

a L1 is increased from 281 mH to 321 mH in steps of 20 mH b L2 is increased from 29 mH to 49 mH in steps of 10 mH c L3 is increased from 43.8 mH to 73.8 mH in steps of 15 mH d During regeneration by taking Io 50 A
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peak current rating and the maximum voltage they need to block. The maximum voltage that S2 needs to block is during mode 7 of operation and is given as   di1 Vmax;blocking;S2 Vs vCF M12 26 dt mode 7 The value of M12 di1 =dt during mode 7 of operation is negative and is of the order of 3040 V for the circuit parameters given in mode 4. It can be easily veried from Fig. 4 that the value of di1 =dtmode 7 % 357143 A s1 , which gives the product M12 di1 =dtmode 7 29 V ( for M12 81:24 mH). Thus the maximum voltage stress on S2 is marginally higher than DC-link clamp voltage level VC Vs vCF . This increased voltage stress on S2 beyond

the DC-link clamp voltage level can be considered negligibly small. The maximum reverse voltage appearing across diode D3 also occurs during mode 7 of operation and is given as   di1 Vmax;reverse;D3 Vs M13 27 dt mode 7 Thus the maximum reverse voltage across D3 always remains marginally less than the DC-link clamp voltage level. It can be observed from Fig. 4 that the maximum reverse voltage across diode D1 occurs during mode 3 and is equal to the DC-link clamp voltage VC Vs vCF . The block diagram of the control circuit for soft-switched PWM inverter control is shown in Fig. 9. Depending upon the PWM inverter modulation strategy, the PWM command generator generates the switching signals for the inverter devices. The change in the conducting state of any inverter switch is rst detected by the edge detector, which generates a turn-on signal to the auxiliary switch S2. This initiates the resonant cycle. The pulse width of the signal applied to the gate of S2 is equal to sum of the time required for the DC-link voltage to reach zero and TZero . To synchronise the change in the conducting state of the inverter devices with the zero link voltage instant, three

PWM Command Generator (Phase A)

Sa Q D To Phase A Flip Switches Flop Q CLK Sb D Sc

PWM Command Generator (Phase B)

Q D Flip Flop Q CLK D

To Phase B Switches Sd

PWM Command Generator (Phase C)

Se D D Q To Phase C Flip Switches Flop Q CLK Sf

Link Detector To Auxiliary Switch S2

Edge Detector

Mono Shot

Fig. 9 Control circuit for synchronising inverter switching with zero DC-link voltage instants

Fig. 10

Simulated plots of vCF and iCF during starting

Table 2: List of SABER templates used for simulating various circuit components and power dissipated in them for different values of inverter switching frequencies
Circuit component SABER template l l l irg4ph50u mur10150e mur10150e irg4ph40u dp Template properties/ comments r 220 mO r 80 mO r 120 mO Inbuilt Saber Template Analogy Inc. Inbuilt Saber Template Analogy Inc. Inbuilt Saber Template Analogy Inc. Inbuilt Saber Template Analogy Inc. Inbuilt Saber Template Analogy inc. Power dissipated with SPWM, 5 kHz 9.1 W 0.52 W 0.18 W 4.5 W 0.21 W 0.84 W 48 W 5.2 W Power dissipated with SPWM, 6 kHz 9.81 W 1.86 W 0.45 W 9W 0.33 W 2.59 W 52 W 5.7 W Power dissipated with SPWM, 7 kHz 10.9 W 1.91 W 0.55 W 10.5 W 0.6 W 4W 60 W 6.2 W

L1 (281 mH, air core) L2 (29 mH, air core) L3 (43.8 mH, air core) Switch S2 Diode D1 Diode D3 Inverter switches Free-wheeling diodes across inverter switches Total

68.55 W

81.74 W

94.66 W

Load and source parameters are: RL 19.68 O, LL 63.94 O, Vs 600 V, Power factor 0.7, Output power 3.6 kW 100
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D-type ip-ops are used. The switching signals generated by the three-phase PWM command generator drive the  D-input pins of the ip-ops, and the output pins Q and Q drive the corresponding top and bottom switches of the
Table 3: Inverter efciency for three different switching frequencies
SPWM carrier frequency, kHz 5 6 7 Average switching frequency of S2, kHz 30 36 42 % efciency

PWM inverter. When the link voltage reaches zero, the zero-voltage detector outputs a signal that is used to clock the D-type ip-ops. Thus it synchronises the change in the conducting state of the inverter devices with the zero link voltage instants, so that the conducting state is changed only at zero-voltage condition. 5 Simulation results

98.09 97.72 97.37

A simulation study of the proposed circuit with parameters given in the mode 4 was performed to verify the analysis and to predict the performance under various load conditions. Simulation results for Io 50 A are shown in Fig. 4. It is observed that the fall time of the link voltage is about 533 ns. The zero link voltage condition, which is utilised for soft-switching of the inverter poles, is maintained

Fig. 11

Experimental results

Fig. 12

Experimental results

a DC-link voltage vCR (top trace, 200 Vper division), S2 gate driver input signal (middle trace, 10 V per division) and current through L2 (bottom trace 16 A per division) Time: 5 ms per division b DC-link voltage (top trace 300 V per division), current through L2 (middle trace, 10 A per division), and current through L1 (bottom trace, 10 A per division) Time: 5 ms per division
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a Current through L2 (top trace, 10 A per division), current through L1 (middle trace, 10 A per division) and current through CF (bottom trace, 10 A per division) Time: 5 ms per division b DC-link voltage (top trace, 300 V per division), current through L1 (middle trace, 5 A per division) and current through CF (bottom trace, 5 A per division) Time: 20 ms per division
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for about 686 ns. The rise time for the DC-link voltage to reach clamp voltage level after a brief zero-voltage period is 3.6 ms. The proposed circuit behaves identically when load regenerates (Io in Fig. 3 reversed in direction). A simulation study was carried out during regeneration with Io 50 A (see Fig. 8d). Figure 10 shows the waveforms of the current through CF and its voltage during starting. It can be observed that vCF settles at 100 V, giving a clamp factor of K 1.16. The on-time of S2 is 1.5 ms. So that the theoretical efciency of the inverter at difference switching frequencies can be estimated, the proposed circuit was simulated using actual SABER templates for various components. The inverter was assumed to be feeding an RL load at power factor of 0.7,

Table 4: List of motor parameters

Motor parameter Rated voltage Rated line-current Stator connection type Frequency Rs Rr Xsl xrl XM Value 400 V 7.8 A Star connected 3F 4 pole 50 Hz 1.1 O 0.9 O 1.8 O 1.8 O 68 O

Fig. 13

Experimental results

a DC-link voltage vCR (top trace, 250 V per division), inverter line-to-line voltage (middle trace, 250 V per division) and current through L1 i1 (bottom trace, 8 A per division) Time: 20 ms per division b Waveforms at fundamental frequency of 50 Hz: DC-link voltage vCR (top trace, 500 V per division), inverter line-line voltage (middle trace, 500 V per division), and motor phase current (bottom trace, 16 A per division) c Waveforms at fundamental frequency of 60 Hz: inverter lineline voltage (top trace, 300 V per division) and motor phase current (bottom trace, 10 A per division) Time: 5 ms per division
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fundamental frequency of 50 Hz and modulation index of 1. The per-phase load parameters, DC-source value and SABER templates used for the simulation study are given in Table 2. As L1, L2 and L3 were chosen to be air core inductors, a linear inductor template with nite resistance was used for simulation. If actual SABER templates are used, the average power dissipated in each circuit component can be determined from the simulation results. These results are given in Table 2. Once the total power dissipation in the entire circuit has been found, the efciency can be calculated. The efciency of the inverter for three different switching frequencies is given in Table 3. It should be noted that the calculated efciencies of the proposed soft-switched inverter, as listed in Table 3, are based on simulation results. 6 Experimental results

with clamping is recycled. The proposed inverter conguration is a solution to the problem of maintaining a separate low-voltage DC source using a low-power DC-toDC converter for clamping the DC link. It is shown that the extra resonant energy can be recycled, while the voltage stress on the clamping diode is maintained equal to the DClink clamp voltage level. The introduction of magnetic coupling between three resonant inductors can minimise the device count. Various modes of operation and link waveforms were analysed to reveal the soft-switching characteristics. Simulation and experimental studies were carried out to verify the proposed concept.

References

So that the simulated results could be validated, a laboratory prototype was built and tested under various load conditions. The circuit parameters used for the experimental study are given in the mode 4 description of circuit operation. Other circuit parameters are: Vs 300 V, CF 5 mF, and the on-time of S2 2.5 ms. Figures 11a12b show the recorded waveforms under no-load condition. Figure 11a shows vCR , the gate signal of S2, and the current through L2, and Fig. 11b shows vCR and currents through L2 and L1. The clamp factor K achieved was 1.3. Figure 12a shows the currents through L1, L2 and L3, respectively, and Fig. 12b shows vCR , L1 current and current through CF. It can be observed from Fig. 11a, that the fall time of the link voltage is approximately 800 ns. The zero link voltage condition, which is utilised for soft-switching of inverter poles, is maintained approximately for 700 ns. The DC-link voltage rises is three distinct steps to reach clamp voltage level after a brief zero-voltage period. The time taken for the DC-link voltage to reach clamp voltage level after a brief zero-voltage period is approximately 5.5 ms. It can be observed that there is fairly good match of simulated waveforms (Fig. 4) and those obtained from the prototype. In the experimental set-up there are stray inductances and capacitances that cause deviation from the simulation results. To demonstrate the PWM capability, a three-phase sine-triangle PWM command generator was implemented to control the six inverter switches. The output of the soft-switched inverter is directly connected to threephase induction motor whose parameters are given in Table 4. The sine-triangle PWM (SPWM) technique is used control the output voltage of the inverter. The frequency of the carrier wave is maintained at 6 kHz. The measured waveforms are shown in Figs. 13ac. Figure 13a shows the link voltage vCR , inverter lineline voltage and current through L1. Figure 13a clearly shows that the change in lineline voltage is synchronised with the zero-voltage instants of the DC link. The load current is sinusoidal, and the performance of the link is found to be satisfactory. 7 Conclusions

1 Divan, D.M.: The resonant dc link inverter a new concept in static power conversion. IEEE-IAS Annual Conf. Rec., 1986, pp. 648656 2 Divan, D.M., and Skibinski, G.: Zero switching loss inverters for high power applications. IEEE-IAS Annual Conf. Rec., 1987, pp. 627634 3 Merterns, A., and Divan, D.M.: A high frequency resonant dc link inverter using IGBTs. IPEC Tokyo, Japan, 1990, pp. 152160 4 He, J., and Mohan, N.: Parallel resonant dc link circuit a novel zero switching loss topology with minimum voltage stresses, IEEE Trans. Power Electron., 1991, 6, pp. 687694 5 He, J., Mohan, N., and Wold, B.: Zero voltage switching PWM inverter for high frequency DC-AC power conversion, IEEE Trans. Ind. Appl.., 1993, 29, pp. 959968 6 Jung, and Cho, G.: Novel type soft switching PWM converter using a new parallel resonant DC link. IEEE-IAS Conf., 1991, pp. 241247 7 Malesani, L., Tenti, P., Tomasin, P., and Toigo, V.: High efciency quasiresonant dc link three-phase power inverter for full-range PWM, IEEE Trans. Ind. Appl., 1995, 31, pp. 141148 8 Choi, J.W., and Sul, S.K.: Resonant link bidirectional power conversion Part-I: Resonant circuit, IEEE Trans. Power Electron., 1995, 10, pp. 479484 9 Wang, K., Jiang, Y., Dudovsky, S., Hau, G., Boroyevich, D., and Lee, F.C.: Novel dc-rail soft switching three-phase voltage source inverter, IEEE Trans Ind. Appl., 1997, 23, pp. 509516 10 Divan, D.M., Malesani, L., Tenti, P., and Toigo, V.: Asynchronised resonant dc link converter for soft switched PWM, IEEE Trans. Ind. Appl., 1993, 29, pp. 940948 11 Lai, J.S., and Bose, B.K.: High frequency quasi-resonant DC voltage notching inverter for AC motor drives. Proc. IEEE Conf., 1990, pp. 12021207 12 Vassilios, G., and Ziogas, P.D.: An optimum modulation strategy for a novel notch commutated three phase PWM inverter, IEEE Trans. Ind. Appl., 1994, 30, pp. 5261 13 Hui, S.Y.R., Gogani, S., and Zhang, J.: Analysis of a quasi-resonant circuit for soft-switched inverters, IEEE Trans. Power Electron., 1996, 11, pp. 106114 14 Chen, S., and Lipo, T.A.: A novel soft switched PWM inverter for AC motor drives, IEEE Trans. Power Electron., 1996, 11, pp. 653659 15 Jafar, J.J., and Fernandes, B.G.: A new quasi-resonant DC-link PWM inverter using single switch for soft switching, IEEE Trans. Power Electron., 2002, 17, p. 1010 16 Jafar, J.J., and Fernandes, B.G.: A quasi-resonant DC-link PWM inverter for induction motor drive. In IEEE-IAS Annual Conf. Rec., 1999, pp. 19972002 17 Jafar, J.J., and Fernandes, B.G.: A novel quasi-resonant DC-link PWM inverter for induction motor drive. In IEEE-PESC Conf. Rec., 1999, pp. 482487

9 Appendix

9.1 State equations during mode 4 of circuit operations

i1 t t4 23:2556 0:534888i1 t4 0:465112i2 t4 1:08022i3 t4 0:0078125t t4 2 cos373683t t4 11:363 0:22726i1 t4 0:22726i2 t4 1:21087i3 t4 cos3:72354 106 t t4 11:89260:237852i1 t4 0:237852i2 t4 0:130654t4 sin373683t t4 3:54682 0:106768 vCF sin3:72354 106 t t4 2:63439 0:00224885 vCF 41561:1t t4 vCF 28
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In this paper, a new circuit topology for a QRDCL softswitching PWM inverter is proposed. It is a simple softswitching topology that is easy to implement and control. The proposed circuit uses one additional switch to create zero-voltage instants in the DC link. The maximum voltage stress on auxiliary circuit diodes is conned to the DC-link clamp voltage level. Also, the resonant energy associated
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i2 t t4 26:7444 0:534888i1 t4 0:465112i2 t4 1:08022i3 t4 cos373683t t4 6:68997 0:133799i1 t4 0:133799i2 t4 0:712902i3 t4 cos3:72354 106 t t4 33:4344 0:668688i1 t4 0:668688i2 t4 0:367315i3 t4 sin373683t t4 2:088190:0628597 vCF sin3:72354 106 t t4 7:406220:00632232 vCF 41561:1t t4 vCF 29 i3 t t4 cos373683t t4 8:50709 0:170142i1 t4 0:170142i2 t4 0:90654i3 t4 cos3:72354 106 t t4 8:50709 0:170142i1 t4 0:170142i2 t4 0:0934603i3 t4 sin373683t t4 2:65539 0:0799336 vCF sin3:72354 10 t t4 1:88445 0:00160866 vCF vCR t t4 45:4545 106 6:96892 109 459:557 13:8338 vCF 2:09814 109 1526:41 1:30302 vCF 45:4545 106 2:09814 109 6890:76 137:815i1 t4 i2 t4 75:703i3 t4 sin3:72354 106 t t4 2:09814 109 cos3:72354 106 t t4 1526:41 1:30302 vCF 6:96892 109 2:54897 10 i1 t4 t t4 4:77932 108 i2 t4 t t4 373683t t4
3 7 6

9.2 State equations during mode 5 of circuit operations

i1 t t5 12:0485 0:759029i1 t5 0:240971i3 t5 1:31032 106 t t5 0:045118 vCR t t5 0:000976563t t5 2 2183:84t t5 vCF cos1:62534 106 t t5 0:240971i1 t5 0:240971i3 t5 12:0485 sin1:62534 106 t t5 1:24596 0:00861631 vCR t5 0:0065397 vCF 33

i3 t t5 37:9515 0:759029i1 t5 0:240971i3 t5 1:31032 106 t t5 0:045118 vCR t t5 0:000976563t t5 2 2183:84t t5 vCF cos1:62354 106 t t5 0:759029i1 t5 0:759029i3 t5 37:9515 sin1:62534 106 t t5 3:92462 0:0271404 vCR t5 0:0205993 vCF 34

30

vCR t t5 vCR t5 0:013655410589:3 73:2297 vCR t5 55:5806 vCF 45:4545 106 0:00016276t t5 4:36557 1011 t t5 2 3:00418 1010 102400 2048i1 t5 2048i3 t5 sin1:62543 106 t t5 3:00418 1010 cos1:62534 106 t t5 10589:3 73:2297 vCR t5 55:5806 vCF 35

459:557 cos373683t t4 1472:29 sin373683t t4 29:4457i1 t4 sin373683t t4 29:4457i2 t4 sin373683t t4 156:891i3 t4 sin373683t t4 13:8338 cos373683t t4 vCF 31 The expression for the area enclosed by current iCF i3 during mode 4 is given as iCF ;area;M 4 4:56936 108 50 i1 t4 i2 t4 0:549308i3 t4 sin3:72354 106 t t4 4:55311 107 15:6069 0:469806 vCF 4:56936 108 11:0758 0:00945482 vCF 1 cos3:72354 106 t t4 4:55311 107 cos373683t t4 15:6069 0:469806 vCF sin373683t t4 50 i1 t4 i2 t4 5:32814i3 t4 32

The expression for the area enclosed by current iCF i3 during mode 4 is given as iCF ;area;M 5 3:00418 1010 77724:6 1554:49i1 t5 1554:49i3 t5 sin1:62534 106 t t5 3:00418 1010 8037:62 55:5834 vCR t5 42:1837 vCF 1 cos1:62534 106 t t5 0:0000813802t t5 466347 9326:95i1 t5 2961:05i3 t5 8:05061 109 t t5 277:205 vCR t t5 2t t5 2 1:34175 107 t t5 vCF 36

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