ELECTRICAL

MEASUREMENTS

ELECTRICAL MEASURMENTS FOR MICROWAVE DEVICES

Selecting a section will link to its page.

A. GENERAL PRECAUTIONS 2

B. HANDLING PRECAUTIONS 2

C. BIAS CIRCUIT 3
1.) DC SUPPLY CIRCUIT 3
2.) RF BIAS CIRCUIT 4

D. MEASUREMENT SYSTEM DIAGRAMS 5

1.) POWER MEASUREMENT SYSTEM BLOCK DIAGRAM 5
Discrete and Partially Matched FETs
2.) POWER MEASUREMENT SYSTEM BLOCK DIAGRAM 6
Internally Matched FETs
3.) IM3 MEASUREMENT SYSTEM BLOCK DIAGRAM 7
4.) PHASE DEVIATION MEASUREMENT SYSTEM BLOCK DIAGRAM 8
5.) PULSE POWER MEASUREMENT SYSTEM BLOCK DIAGRAM 9
Pulsed Drain Bias
6.) NOISE FIGURE AND ASSOCIATED GAIN MEASUREMENT SYSTEM BLOCK
DIAGRAM 10
7.) THERMAL RESISTANCE MEASUREMENT SYSTEM BLOCK DIAGRAM AND
MEASUREMENT PROCEDURE 11

Microwave Support Documentation 1 ANMEM0902

ELECTRICAL
MEASUREMENTS

A. GENERAL PRECAUTIONS

1) Observe recommended operating conditions and absolute maximum ratings:

VDS, IDS, VGS, IG, TCH.

Absolute Maximum Ratings are the limits one should not exceed under any conditions and does
not mean actual applicable bias condition. Fujitsu recommends the following conditions for long
life and reliable operation.

TCH = 145°C max

VDS = See the individual data sheets
VGS = VGS shall be set for the IDS (0.6 IDSS to 0.55 IDSS)
IG = See the individual data sheets

2) Use a sequencing DC power supply.

See the individual data sheets or Figure III-1.

3) Do not apply RF power until the FET is biased on. Turn-off RF power before removing bias.

4) Use only properly designed RF circuits and decoupling circuits to prevent bias circuit oscillations.
Bias oscillations are one of the most common modes of failure for microwave GaAs FETs.
Destruction of the FET often occurs in microseconds. Refer to the individual data sheets or
Figure III-3 , for the recommended bias circuit configuration.

B. HANDLING PRECAUTIONS

GaAs FETS are sensitive to electrostatic discharge. Fujitsu ships all GaAs FETs in electrostatic
protection packaging. User must pay careful attention to the following precautions when taking
FETs out of their packaging.

1) Personnel handling GaAs FETs should be properly grounded by a wristlet chain or equivalent.

2) When mounting the FET in a circuit, the circuit gate and drain connections should be shorted to
ground.

3) When soldering the FET leads, an iron with a grounded tip is required.

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MEASUREMENTS

C. BIAS CIRCUIT
This application note is intended to instruct the user in proper DC biasing of GaAs FET devices. Areas to
be discussed include D.C. supply circuit and RF bias circuit.

1) DC Supply Circuit

When applying D.C. bias to a device in a common source configuration, a negative gate voltage
must be supplied first, followed by a positive drain voltage. Conversely, when removing DC bias,
the drain voltage must be removed first, followed by the gate voltage. A GaAs FET, with drain
voltage applied and floating or zero gate voltage, is likely to oscillate and may damage the device.

In the case of a bias application, a self sequencing, fault protected bias supply is recommended.
Fujitsu has developed a voltage-regulated bias supply which satisfies the requirements for safely
biasing GaAs FETs. An example of the bias supply circuit is shown in Figure III-1.

E1 E2
VIN TR1 VOUT
+12V +10V
R14 R11
+ R15 R16 R18 R13
D12 C2 R17 +
- TR2 C6
D7 D5 -
+ TR3
+ D10 C1 R12
- C7 -
D8
GND C3 GND
+ +
3 + - C5 - C4 D9
2 4
-
8 IC2 5 IC1 E3
VOUT
-5V
Figure III-1. Suggested Circuit

TR1 2SD 1297 R11 CHIP RESISTOR, 1/10W,

TR2,TR3 2SC 2712 510 OHM
IC1 NJM79L05UA (JRC) R12 CHIP RESISTOR, 1/10W,
IC2 LTC1044CSB 680 OHM
D9 ISS1B1 R13 CHIP RESISTOR, 1/10W,
D5, D10 RD51MB1 (NEC) 220 OHM
D7,D8 RD4.3PB (NEC) R17 CHIP RESISTOR, 1/10W,
D12 U1BZ41 1K OHM
C1,C4,C6 CS98E1V6R000-K41B R16 CHIP RESISTOR, 1/10W,
C2 CS98E1V6R800-K41D 6.2K OHM
C3,C5,C7 CS98E1E10R00-K41D R14 CHIP RESISTOR, 1/10W,
510 OHM to 1K OHM
R15 CHIP RESISTOR, 1/8W
100 OHM
R18 390 OHM, 1/8W

This regulated bias circuit is designed to provide a constant positive drain voltage (+VDS) of 10V
and an output current of 20 Amperes.

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MEASUREMENTS

Vin: ON Vin: OFF

+Vout (V)
10
+Vout (V)
5

10 msec
-2

-4
-Vout (V)
-6 -Vout (V)

Figure III-2. Switching Response of the Bias Circuit

2) RF Bias Circuit

The injection of bias voltages into a GaAs FET RF circuit is typically accomplished via a quarter-
wave transformer line as shown in Figure III-3. It is intended to provide a DC connection to the GaAs
FET gate and drain, while perturbing the RF performance characteristics as little as possible.

High impedence λ/4 line High impedence λ/4 line

Low impedence λ/4 line

Low impedence λ/4 line

R2 C2
R1

C1

L1 L2 C1, C2: 1000pF, Chip

R3 L1, L2 : Large inductor at
RF frequency or λ/4 line

}
R1 Chosen for desired
R4 R3 VGS, IDS and
C4
R4 gate impedance
C3 R2 : 50Ω Chip
C6 C3, C4: 1000pF feed thru
R3 x R4 C5, C6: about 10µF
Rg=R1 + C5
-VGS +VDS
R3 + R4

Figure III-3. Connection of the Bias Supply to the GaAs FET's

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D. MEASUREMENT SYSTEM DIAGRAMS

1. POWER MEASUREMENT SYSTEM BLOCK DIAGRAM

Discrete and Partially Matched FETs

POWER POWER
METER METER
VGS VDS

POWER POWER
SENSOR SENSOR

DIRECTIONAL BIAS BIAS

TUNER D.U.T. TUNER ATTEN.
COUPLER TEE TEE

Rg *
50 Ω term.

RF POWER IGS IDS

SOURCE

-VGG +VDD

DC POWER SUPPLY

* Use Fujitsu's recommended gate resistance (Rg) as indicated

on the data sheet for the device under test . Follow device handling
and bias precautions presented at the beginning of this section.

Microwave Support Documentation 5 ANMEM0902

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MEASUREMENTS

2. POWER MEASUREMENT SYSTEM BLOCK DIAGRAM

Internally Matched FETs

SCALER
RF RF POWER NETWORK
AMP SOURCE ANALYZER

VGS VDS
50 Ω term.

DETECTOR DETECTOR

DIRECTIONAL DIRECTIONAL BIAS BIAS DIRECTIONAL

COUPLER COUPLER TEE D.U.T. TEE COUPLER

DC DC
Rg * Block Block
POWER
SENSOR ATTEN.
50 Ω term. 50 Ω term.
IGS IDS
POWER
METER POWER
SENSOR

-VGG +VDD
DC POWER SUPPLY POWER
METER

* Use Fujitsu's recommended gate resistance (Rg) as indicated

on the data sheet for the device under test . Follow device handling
and bias precautions presented at the beginning of this section.

Microwave Support Documentation 6 ANMEM0902

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3. IM3 MEASUREMENT SYSTEM BLOCK DIAGRAM

50 Ω term.

RF POWER
Ω
50 Ω
50 RF
SOURCE
term. AMP
Freq.=f SPECTRUM
3 dB ANALYZER
Hybrid
RF RF POWER
AMP SOURCE
Freq.=f+∆f VDS

ATTEN.
VGS
50 Ω term.

VAR. DIRECTIONAL BIAS BIAS DIRECTIONAL

ATTEN. COUPLER TEE D.U.T. TEE COUPLER

DC DC
Rg * Block Block
POWER
SENSOR ATTEN.
50 Ω term. 50 Ω term.
IGS IDS

POWER
METER POWER
SENSOR

-VGG +VDD
DC POWER SUPPLY POWER
METER

* Use Fujitsu's recommended gate resistance (Rg) as indicated

on the data sheet for the device under test . Follow device handling
and bias precautions presented at the beginning of this section.

Be sure that the power level of signals input to the spectrum analyzer remain in the linear
range of the analyzer's internal mixer.

example: IM3 (D) = -40dBc

Degradation in IM3 (dB)

EFFECT OF A DRIVER AMPLIFIER ON TOTAL IMD 6

IM3 (F) = -30dBc
( IM3(D) - IM3(F)
) IM3 = -30 + 2.4
[
Degradation in IM3 = 20 log 1+10
20
[ = -27.6dBc
4
where IM3(D) is the driver stage IM3
IM3(F) is the final stage IM3

IM3 (D) IM3 (F)

0 10 20 30
IM3 (F) - IM3 (D)

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4. PHASE DEVIATION MEASUREMENT SYSTEM BLOCK DIAGRAM

CONVERTER/ VECTOR
RF RF POWER TEST SET NETWORK
AMP SOURCE ANALYZER
REF TEST

LOW
PASS
FILTER 50 Ω term.

VGS VDS VAR.

PHASE ATTEN.
VAR. SHIFTER
ATTEN.

DIRECTIONAL DIRECTIONAL BIAS BIAS DIRECTIONAL

COUPLER COUPLER TEE D.U.T. TEE ATTEN. COUPLER

DC DC
Block Block
Rg *
POWER
SENSOR ATTEN.
50 Ω term. 50 Ω term.
IGS IDS
POWER
METER POWER
SENSOR

-VGG +VDD

DC POWER SUPPLY POWER

METER

* Use Fujitsu's recommended gate resistance (Rg) as indicated

on the data sheet for the device under test . Follow device handling
and bias precautions presented at the beginning of this section.

Microwave Support Documentation 8 ANMEM0902

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MEASUREMENTS
5. PULSE POWER MEASUREMENT SYSTEM BLOCK DIAGRAM

Pulsed Drain Bias

RF PULSE RF POWER PULSE

AMP MODULATOR SOURCE GENERATOR

PULSE
DRIVER

Pulsed Trig.
VGS Drain
CH-1 OSCILLO-
Bias SCOPE
CH-2

VAR. DIRECTIONAL BIAS BIAS

ATTEN. COUPLER TEE D.U.T. TEE

DC DC ATTEN.
Block Block
Rg *
50 Ω term.

50 Ω term. 50 Ω term.
POWER POWER
SENSOR IGS SENSOR

PEAK PEAK
POWER POWER
METER METER
-VGG +VDD

DC POWER SUPPLY

* Use Fujitsu's recommended gate resistance (Rg) as indicated

on the data sheet for the device under test . Follow device handling
and bias precautions presented at the beginning of this section.

Package Outlines Microwave Support 9 ANMEM0902

ELECTRICAL
MEASUREMENTS
6. NOISE FIGURE AND ASSOCIATED GAIN
MEASUREMENT SYSTEM BLOCK DIAGRAM

LOCAL
OSCILLATOR

NOISE FIGURE
AND GAIN
METER
MIXER

VGS VDS

LOW NOISE
AMPLIFIER

NOISE BIAS TUNER TUNER BIAS

SOURCE D.U.T.
TEE TEE

Rg *
50 Ω term. 50 Ω term.

IGS IDS

-VGG +VDD

DC POWER SUPPLY

* Use Fujitsu's recommended gate resistance (Rg) as indicated

on the data sheet for the device under test . Follow device handling
and bias precautions presented at the beginning of this section.

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7. THERMAL RESISTANCE MEASUREMENT SYSTEM BLOCK DIAGRAM

AND MEASUREMENT PROCEDURE

D.U.T.
S3

S1 S2 VGS Detector
S4

IDS
IM

-VGS +VDS

DC POWER SUPPLY

MEASUREMENT PROCEDURE

Open and close switches S1, S2, S3, and S4 according to the timing diagram illustrated in Figure 2. The heat
interval should be much longer than the thermal response time of the device under test (10 seconds). The
measurement interval should be as short as possible (less than 50 µsec.). The constant measurement current
(IM) is a small current so selected that the measurement power dissipation may be neglected compared to the
heat power dissipation.

The measurement is made in the following manner:

a. VDS is set to a specified value.

b. VGS is set to a specified value, or adjusted S1

to obtain a specified drain current IDS.

c. VGS1 is measured during the pre-heat
S2
measurement interval.
d. VGS2 is measured during the post-heat
measurement interval. S3

Then thermal resistance is calculated as follows:

S4
Rth(Channel-Case) = (VGS1-VGS2)/(K x VDSx IDS )
VGS1 Heat Interval VGS2
Where K is the thermal coefficient of VGS (mV/°C)
Measurement Measurement
Interval Interval
K is obtained in the following manner:
Figure 2. Switch Timing Diagram
a. Short the DUT drain and source to ground.
b. Adjust the gate forward current to the value IM.
c. Measure VGS at two different ambient temperatures less than 100°C.

Then K is calculated as follows:

K=(VGSa-VGSb)/(Tb-Ta) where Tb>Ta

Note: DC bias conditions and accept/reject criteria shall be included in individual device specifications.

Microwave Support Documentation 11 ANMEM0902

for further information please contact:

FUJITSU COMPOUND SEMICONDUCTOR, INC.

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San Jose, CA 95131-1138, U. S. A.
TEL: (408) 232-9500
FAX: (408) 428-9111
www.fcsi.fujitsu.com

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©2001 FUJITSU COMPOUND SEMICONDUCTOR, INC.

Printed in U.S.A. FCSI012001M3.5K