Hybrid Silicon

Nanoelectronics
Oda Laboratory
Tokyo Institute of Technology
Fusion of top-down & bottom-up nanotechnology
100 hp65 hp45 hp32 hp22
ITRS2003 predicts 9 nm gate
•High-k MOSFETs in 2016.
Lg (nm)

Low •FUSI
-pow
High er Dual metal
-per gate
form
Strained Si a nce
FD SOI
Multiple
gate(3D)
10 Quasi
ballistic

2005 2010 2015 Year

TOP-DOWN SILICON
Source
BOTTOM-UP SILICON
Si nanodot (SiND) Si nanorod (SiNR)
Si (111) SiO2
Drain
30nm

In collaboration with
10nm Cambridge Univ.
 Hybrid Silicon Nanoelectronics
１　 Structural control of nanocrystalline Si structures
Si nanodots Si nanorods ナノシリコンドット

ドットサイズ
を揃える

In collaboration with Cambridge Univ.

トンネル膜厚
を揃える
Substrate
UHV
To TMP Chamber
10nm 位置を揃える

Orifice nc-Si dot Structural control

(φ ∼ 5 mm) evaporation
SiH4 gas Dispersion
solution
VHF (144MHz)
Plasma Cell LB film
H2 or
Ar gas
PC control

VHF Plasma CVD system

100n
(room temperature deposition) m
nc-Si dot assembly technique
 Hybrid Silicon Nanoelectronics
２　 Nanocrystalline Si based New functional devices
Acceleration Collector
voltage 電子
100V Thin Au
50 nm
nc-Si layer
50nm
Diode Si substrate
voltage Al electrode

10-3 1

効率 (%)
10-5 10-2
電流 (A/c m 2)

10-7 10-4
ダイオード
放出電子
10-9 効率
10-6

0 10 20 30
引出電圧 (V)

BSD (ballistic electron surface emitting display) Nanodot flash memory

Bending SiO2 beam with Si
Si nanodots
nanodots
G

e- e e e-
- -
Air gap

S MOSFET channel D
2μm
Nanoelectromechanical devices
 Hybrid Silicon Nanoelectronics
３　 Quantum information devices based on nc-Si

Vg2(V)
15nm Vg2 Anti-bonding
0.4
meV
Source Drain 2 Bonding
1 Vg1

Vg2 (V)
nc-Si dot 0
-1
20 nm 10 nm -2
-3
30 nm 15 nm -4 -3 -2 -1 0 1 2 3 4
Vg1 (V)
VVg1(V)
g1
(V)
0.04 T = 20K Observation of quantum-mechanical interaction
-7 between two nc-Si dots （ in collaboration with CU ）
0.02
Current (A) (Log

Initialization Read-out
-8
Vsd (V)

Scale)

0
-9
-0.02

-10
Control
-0.04
3 3.5 4 4.5 5
Gate Voltage (V) Design & fabrication of nc-Si quantum information
Single-electron charging effects devices for solid-state quantum computers
 Hybrid Silicon Nanoelectronics
４　 Multi-scale nc-Si material & device simulation

Pseudopotential
Atomistic
nanostructure DFT （ LCAO base ）
simulation H = i −  ∇ + V ( ρ ) j 2
2 eff
i, j
2m HOMO LUMO
Icosahedral structure SiND (d=1.56nm)

H D
Nanoscale Nonequilibrium
Green’s function
quantum
transport [
G(E ) = E − H − ∑ (E) ] −1

simulation
Nonequilibrium quantum
Equilibrium distribution & transport through SiNR
linear response parameters
D e n s ity Ids (A)
( c m -2 )

Quantum device 2.0D 11

simulation
Mesoscale （ DG method ） 1.0D 11

device ・ circuit
Hybrid circuit
simulation simulation
0.0D

0
20 .5
1 .0
Vg2 (V)

X (n m ) 0
40 -.5
-1 .0 k ( n m -1 )
60 Vg1 (V)

Wigner distribution Quantum equivalent circuit modelling

 Hybrid Silicon Nanoelectronics
５　 High-k dielectric thin films for next generation ULSIs
•HfO2 • Pr-oxide/silicate
Si-O-Si/H-O-H Pr-O-Pr

SiO2 3.5 nm

Normalized Intensity[a.u.]
HfO2 TOA
Pr silicate
3.2 nm
equivalent 90°
52°
formation
界面層 30°
0.8 nm thickness 15°

5 nm
Si基板 ~ 1.2 nm 537 535 533 531 529 527
Binding Energy [eV]
Cross sectional TEM XPS spectrum （ in collaboration with Musashi Tech.)
Fabrication and characterization of high-k dielectric gate insulator
Purge gas O2 gas Material gas
in ellipsometric angle ∆
1 1サイクル
cycle HfO2/Si
167.5
エリプソメトリ角Δの変化

約 1.1Å
∆ [deg]

166.5
1 degree
1度

s
原料 3秒
165.5
Change

Sample s
20秒
パージ
Heater Ellipsometer
酸素 s
40秒
drai 164.5
Novel stacked memory
n time
時間 100
1950 2050 2150 2250 100 sec
秒
In-situ real-time spectroscopic ellipsometry
time [s] study