ISSCC 2003 / SESSION 26 / EMBEDDED AND DIGITAL SYSTEMS / PAPER 26.

4
26.4 A 500MHz MP/DLL Clock Generator for a 5Gb/s
Backplane Transceiver in 0.25m CMOS
Gu-Yeon Wei
1
, John T. Stonick
2
, Dan Weinlader
2
, Jeff Sonntag
2
,
Shawn Searles
2
1
Harvard University, Cambridge, MA
2
Accelerant Networks, Beaverton, OR
The desire for higher network bandwidth drives the development
of high-speed data communication links for backplanes in
routers and switch boxes. Backplane transceivers require clock
generation with low jitter characteristics to ensure robust oper-
ation. This paper describes the implementation of the 500MHz
system clock generator for a 5Gb/s backplane transceiver design
described in [1] and a follow-on 5x5Gb/s version. The clock gen-
erator multiplies a 125MHz reference clock to 500MHz utilizing
a block that is configured to operate either as a multiplying
phase-locked loop (MPLL) or a multiplying delay-locked loop
(MDLL) depending on the noise characteristics of the off-chip
reference clock signal. For a low-jitter input reference clock, the
MDLL configuration is chosen since it avoids the clock jitter
accumulation of an oscillator. However, under noisy conditions,
the MPLL configuration is chosen to filter the input clock noise.
Figure 26.4.1 presents a block diagram of the loop that is config-
ured as either an MPLL or MDLL through a select signal
(sel_mode). In MPLL mode, the delay elements are configured as
a ring oscillator by fixing the multiplexer to always select the fed
back output of the delay line. In MDLL mode, a Mux Control
block periodically flips between the multiplexers two inputs the
input ref clock or delay-line output. Its operation is similar to the
multiplying DLLs described in [2] and [3]. A divide-by-four
counter is also used to select and pass one of four clock edges out
of the voltage-controlled delay lines (VCDL) to the phase-fre-
quency detector (PFD).
The delay elements are nearly full-swing pseudo-differential
cells, slightly modified versions in [4]. As shown in Fig. 26.4.2,
modifications are made to reduce VCO gain and to control the
tuning range. First, to both reduce size requirements for the loop
filter capacitor and sensitivity to noise in the signal path of the
loop, the cells delay is controlled by split tuning the current in a
set of PMOS current sources. The current sources on each side
are split into two devices (e.g., M1a and M1b) with a 3:1 width
ratio. The larger device is controlled through a lower-bandwidth
coarse tuning path while the smaller device is controlled through
a higher-bandwidth fine-tuning path. Split tuning reduces the
VCOs gain by 4. Second, a current source (M3), controlled by a
process monitoring circuit, is added. At the fast corner, current is
reduced to weaken the cross-coupling strength of the PMOS pair
and decrease the oscillation frequency. The opposite occurs for
the slow corner.
The sel_mode signal also configures the loop filter to incorporate
a resistor (for zero compensation) and capacitor for MPLL mode
or just a capacitor for MDLL mode. To avoid the up and down
current mismatches in conventional single-ended charge-pump
circuits, the high-speed differential charge pump (CP) shown in
Fig. 26.4.3 is employed. When the UP and DN signals out of the
PFD are both low or high, equal 50A current exist in both sides
of the CP. When either input is high and the other is low, the dif-
ferential pair steers a 50A differential current onto the loop fil-
ter. The loop filter is realized using Metal-Insulator-Metal (MIM)
capacitors, poly Si resistors, and a set of switches. In MPLL
mode, the switches are configured to create an RC loop filter. In
MDLL mode, the resistor is switched out and the capacitors are
connected in series to reduce the filter cap by a factor of 4 and
increase the MDLLs bandwidth.
Although the PFD and fully differential CP are ideally balanced,
device mismatches, primarily due to threshold voltage offsets, and
finite output impedance create imbalances. The continuous current
in this CP exacerbates these effects. In MPLL mode, the imbalance
creates a static phase error, which is tolerated by the system.
However, in MDLL mode, this phase error accumulates every four
cycles and creates a tone in the output clock signal at the reference
clock rate. To combat this error, a low-bandwidth secondary loop is
added to compensate for current mismatches. The compensation
loop is digital, comprising a bang-bang phase detector and an accu-
mulator to implement an integrator with infinite dc gain. The out-
put of the integrator controls a current DAC that leaks current from
either side of the differential CP.
Lastly, the CP output, which is a differential signal, sets the
VCDL delay. However, the delay elements are controlled with sin-
gle-ended control signals. Hence, as shown in Fig. 26.4.3, a differ-
ential-to-single-ended (D2S) voltage converter required. The
amplifier has two sets of differential inputs: One set is in a unity-
gain configuration driven by a reference voltage (V
REF
). The second
set comes from the CP and skew the output about V
REF
. To accom-
modate a range of operating frequencies and process corners, the
D2S is self-biased by driving V
REF
with a filtered version of the out-
put. This manifests itself as an additional integrator and zero at
the filter cut-off frequency. Therefore, the filter cut-off must be low
enough to guarantee stability. The D2S also introduces a low-pass
filter in the signal path and its bandwidth must be set well above
the unity-gain frequency of the loop. The output of the D2S drives
the fine control of the split-tuned delay elements while the filtered
version, V
REF
, drives the coarse tuning control. In lock, both control
voltages drive to a common voltage and the CPs differential out-
put approaches zero to mitigate output impedance effects.
Figure 26.4.4, presents the jitter histogram plots of the MP/DLL
measurements from a production 5x5Gb/s transceiver chip in both
MPLL and MDLL modes. One of five transmitters is configured to
put out a regular clock pattern while the other links transmitted
and received random 5Gb/s data. Alow-noise reference clock leads
to slightly lower jitter in MDLL mode. However, when high fre-
quency noise (15MHz) of varying amplitudes is injected into the
clock reference, the resulting root-mean-square (rms) jitter mea-
surements in Fig. 26.4.5 show that the MPLL provides noise fil-
tering to reject the added noise as opposed to the all-pass nature
of the MDLL. Lastly, Fig. 26.4.6 presents the MDLLs output clock
signal with and without CP mismatch compensation enabled.
Without compensation (and with the oscilloscope triggered from a
250MHz source), two distinct clock edges are seen arising from the
phase offset induced by mismatches (measured as 81ps). With
compensation enabled, the secondary loop successfully eliminates
this phase offset.
The MP/DLL is fabricated in a 0.25m triple-well TSMC CMOS
process, measures 420 x 500m
2
in area, and consumes approxi-
mately 28mW under normal operation from a 2.5V supply. Given
the uncertainty of input clock source fidelity in real systems, the
experimentally measured results suggest the MPLL as the
default configuration for most cases.
Acknowledgements
The authors would like to thank J. Gorecki, U.-K. Moon and Y. Yang for
their invaluable advice, analog circuit design contributions, and initial
analysis of loop dynamics and noise. We are also grateful to A. Sengir for
layout and G. Lemire for test measurements.
References
[1] J. Sonntag, et al, An Adaptive PAM-4 5Gb/s Backplane Transceiver in
0.25mm CMOS, CICC, 2002.
[2] R. Farjad-Rad, et al, A 0.2-2GHz 12mW Multiplying DLL for Low-
Jitter Clock Synthesis in Highly-Integrated Data-Communication Chips,
ISSCC Dig. Tech. Papers, pp. 76-77, 2002.
[3] A. Waizman, A Delay Line Loop for Frequency Synthesis of De-
Skewed Clock, ISSCC Dig. Tech. Papers, pp. 298-299, 1994.
[4] S.H. Wang, et al, A 500-Mb/s Quadruple Data Rate SRAM Interface
Using a Skew Cancellation Technique, J. Solid State Circuits, April 2001.
2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 2003 IEEE
ISSCC 2003 / February 12, 2003 / Salon 10-15 / 3:15 PM
26
Figure 26.4.1: MP/DLL block diagram. Figure 26.4.2: Modified pseudo-differential delay element.
Figure 26.4.3: Differential CP, loop filter, and D2S block schematics.
Figure 26.4.5: Measured MP/DLL rms jitter vs. added input noise. Figure 26.4.6: Measured MDLL.
PFD
Mux
Ctrl
V
FNE_CTRL
& V
COARSE_CTRL
Diff.
CP
LF
D2S
1
2
5
-
M
H
z
R
e
f

C
l
k
5
0
0
-
M
H
z
O
u
t
p
u
t

C
l
k
2
Edge
Select
UP
DN
Divide-by-4
sel_mode
sel_mode
M1a M1b
3x 1x
M3
process
monitoring
circuit
V
COARSE_CTRL
V
FNE_CTRL
in+ in-
out-
out+
CMFB
UP
UP
DN
DN
V
bn1
V
bn2
V
bn
25uA
D2S
V
COARSE_CTRL
V
FNE_CTRL
V
CP+
V
CP-
V
REF
Loop Filter
(MPLL configuration)
V
bp2
V
cmb
MPLL MDLL
MDLL
MPLL
w/o compensation w/ compensation
Figure 26.4.4: 500-MHz clock jitter histograms in MPLL and MDLL
modes of operation.
2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 2003 IEEE
2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 2003 IEEE
PFD
Mux
Ctrl
V
FNE_CTRL
& V
COARSE_CTRL
Diff.
CP
LF
D2S
1
2
5
-
M
H
z
R
e
f

C
l
k
5
0
0
-
M
H
z
O
u
t
p
u
t

C
l
k
2
Edge
Select
UP
DN
Divide-by-4
sel_mode
sel_mode
Figure 26.4.1: MP/DLL block diagram.
2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 2003 IEEE
M1a M1b
3x 1x
M3
process
monitoring
circuit
V
COARSE_CTRL
V
FNE_CTRL
in+ in-
out-
out+
Figure 26.4.2: Modified pseudo-differential delay element.
2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 2003 IEEE
CMFB
UP
UP
DN
DN
V
bn1
V
bn2
V
bn
25uA
D2S
V
COARSE_CTRL
V
FNE_CTRL
V
CP+
V
CP-
V
REF
Loop Filter
(MPLL configuration)
V
bp2
V
cmb
Figure 26.4.3: Differential CP, loop filter, and D2S block schematics.
2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 2003 IEEE
MPLL MDLL
Figure 26.4.4: 500-MHz clock jitter histograms in MPLL and MDLL modes of operation.
2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 2003 IEEE
Figure 26.4.5: Measured MP/DLL rms jitter vs. added input noise.
MDLL
MPLL
2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03/$17.00 2003 IEEE
w/o compensation w/ compensation
Figure 26.4.6: Measured MDLL.