Sti5500 Register Manual

CO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
D I F N
L A I T N E
STi5500
REGISTER MANUAL
2 4 23 31 46 47 50 53 58 74 81 86 87 89 92 97 103 104 112 117 127 130 131 158 160
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous serial controller (ASC) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio MPEG (AUD) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block move DMA (BMDMA) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration and control (CFG) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock generator (CKG) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital encoder registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External memory interface (EMI) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt level controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPEG DMA controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PES parser (PES) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel input/output (PIO) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM and counter module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SmartCard interface (Sc) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub-picture decoder (SPD) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous serial controller (SSC) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transport stream demultiplexor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Teletext interface (Ttxt) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDRAM block move (USD) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video decoder (VID) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index of Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21 July 2000
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This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice
1 - Introduction
This manual describes all of the STi5500 registers to control the MPEG video and audio subsystems, and all of the peripherals. The complete bit format of all the registers and their functionality is given. The registers are listed in alphabetical order. Registers for other modules are described in the chapter for that module. A full list of all registers with absolute addresses is given in the data sheet. The reset state is defined as the state existing after a hard reset.
L A I IntroductionENT D I F N O C
Accessing registers
STi5500
1.1
The registers can be examined and set by the devlw (device load word) and devsw (device store word) instructions; they cannot be accessed using memory instructions. The registers are all in the peripheral address space in region 2 of the address space. The registers of each module are also grouped in the address space, usually in a 4 Kbyte block. In the register descriptions, the addresses are given as offsets from the base of the appropriate block. Table 1.1 lists the variables used in this document to signify the bases of blocks of registers and gives their values. All unused locations of the register map and unused bits in any register are reserved. Only the value 0 must be written to any of these locations or bits. The values which are read from these locations or bits are undefined. Variable Value 0x20003000 0x20004000 0x20005000 0x20006000 0x00001200 0x20026000 0x00004000 0x00003000 0x00001600 0x00002000 0x20000000 0x20011000 0x20020000 0x20021000 0x20022000 0x2000C000 0x2000D000 0x2000E000 0x2000F000 0x20010000 0x2000B000 0x20007000 0x20008000 0x20009000 0x00001400 0x20002000 0x20024000 0x00001000 Block Asynchronous serial controller (ASC) 0. Asynchronous serial controller (ASC) 1. Asynchronous serial controller (ASC) 2. Asynchronous serial controller (ASC) 3. MPEG audio decoder. Block move DMA controller. Cache configuration. Diagnostic controller unit (DCU). PAL/NTSC digital encoder. External memory interface (EMI). Interrupt controller. Interrupt level controller. MPEG DMA0 controller. MPEG DMA1 controller. MPEG DMA2 (SDAV) controller. PIO port 0 controller. PIO port 1 controller. PIO port 2 controller. PIO port 3 controller. PIO port 4 controller. PWM and counter module. SmartCard interface 0. SmartCard interface 1. Synchronous serial controller (SSC) 0. Sub-picture decoder. Transport stream demultiplexor. Teletext interface. MPEG video decoder.
ASC0BaseAddress ASC1BaseAddress ASC2BaseAddress ASC3BaseAddress AudioBaseAddress BMBaseAddress CacheBaseAddress DCUBaseAddress DENCBaseAddress EMIBaseAddress IntControllerBase InterruptLevelBase MPEGDMA0BaseAddress MPEGDMA1BaseAddress MPEGDMA2BaseAddress PIO0BaseAddress PIO1BaseAddress PIO2BaseAddress PIO3BaseAddress PIO4BaseAddress PWMBaseAddress SmartCard0BaseAddress SmartCard1BaseAddress SSCBaseAddress SubPictureBaseAddress TransportDemuxBase TtxtBaseAddress VideoBaseAddress
Table 1.1 Register block base variables
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STi5500 1.1.1
Video and audio register addressing
The four subsystems audio, DENC, sub-picture and video, are each allocated a 2 Kbyte block of addresses in the internal peripheral address space. Within these register blocks, bits 7 and 8 are used to define the number of wait states used when accessing the registers. Table 1.2 shows the values to add to the register addresses for different numbers of wait states.
CO
D I F N
3 wait states 4 wait states 5 wait states
L A I T N E
Bit 7 1 0 1
1 - Introduction
Wait states
Bit 8 0 1 1
Add to address 0x080 0x100 0x180
Table 1.2 Wait state encoding For example, the audio register AUD_BBE is listed at address 0x70, and is in the audio block, base address 0x00001200. To access this register when 3 wait states are needed, the full address is given by:
FullAddress
= 0x70 + WaitStateCode + AudioBaseAddress = 0x70 + 0x080 + 0x00001200 = 0x000012F0
1.2
Synchronization of video decoder registers
There are two types of video decoder register: synchronized and unsynchronized. Synchronized registers only change value in response to an internal event, either DSYNC or VSYNC, depending on the register. These registers are double-banked; during the write cycle the new value is loaded into a master register, and on the occurrence of the synchronizing event this value is loaded into a slave register, at which time the new value is available to the circuit. If a synchronized register is read, the value returned is that held in the master register. Unsynchronized registers change their value immediately they are written to. Some registers are non synchronized registers with edge triggered write (on end of write cycle). This is to avoid glitches on internal signals during write cycles.
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2 - Register map
This chapter lists all the memory-mapped registers in address order. Details of the contents of each register are given in the rest of this manual. Other addresses should not be accessed. The registers are grouped into modules for ease of reference. The addresses are absolute addresses. The column headed Bits gives the number of significant bits; in the case of serial registers, only 8 bits should be read or written at each access. Register CFG_MCF CFG_CCF VID_CTL VID_TIS VID_PFH VID_PFV VID_PPR1 VID_PPR2 USD_BMS[15:0] USD_BRP[18:0] USD_BWP[18:0] VID_DFP[13:8] VID_DFP[7:0] VID_RFP[13:8] VID_RFP[7:0] VID_FFP[13:8] VID_FFP[7:0] VID_BFP[13:8] VID_BFP[7:0] VID_VBG[13:8] VID_VBG[7:0] VID_VBL[13:8] VID_VBL[7:0] VID_VBS[13:8] VID_VBS[7:0] VID_VBT[13:8] VID_VBT[7:0] VID_ABG[13:8] VID_ABG[7:0] Address 0x00001000 0x00001001 0x00001002 0x00001003 0x00001004 0x00001005 0x00001006 0x00001007 0x00001009 0x0000100A 0x0000100B 0x0000100C 0x0000100D 0x0000100E 0x0000100F 0x00001010 0x00001011 0x00001012 0x00001013 0x00001014 0x00001015 0x00001016 0x00001017 0x00001018 0x00001019 0x0000101A 0x0000101B 0x0000101C 0x0000101D Bits 7 8 5 6 8 8 7 7 16 19 19 6 8 6 8 6 8 6 8 6 8 6 8 6 8 6 8 6 8 Access R/W R/W R/W W R/W R/W R/W R/W Serial R/W Serial R/W Serial R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W Description Memory Refresh Interval. Chip Configuration. Decoding Control. Task Instruction. Picture F-parameters Horizontal. Picture F-parameters Vertical. Picture Parameters 1. Picture Parameters 2. Block Move Size. Memory Read Pointer. Memory Write Pointer. Displayed Luma Frame Pointer. Displayed Luma Frame Pointer. Reconstructed Frame Pointer. Reconstructed Frame Pointer. Forward Luma Frame Pointer. Forward Luma Frame Pointer. Backward Frame Pointer. Backward Frame Pointer. Start of Video Bit Buffer. Start of Video Bit Buffer. Video Bit Buffer Level. Video Bit Buffer Level. Video Bit Buffer Stop. Video Bit Buffer Stop. Video Bit Buffer Threshold. Video Bit Buffer Threshold. Start of audio bit buffer. Start of audio bit buffer.
L A I T Register map N E D I F N CO
STi5500
Table 2.1 Video registers
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STi5500
Register VID_ABL[13:8] VID_ABL[7:0]
VID_ABS[13:8] VID_ABS[7:0]
CO
D I F N
Address
0x0000101E 0x0000101F 0x00001020 0x00001021 0x00001022 0x00001023 0x00001024 0x00001025 0x00001028 0x00001029
L A I T N E
Bits 6 R 8 6 8 6 8 15 8 8 6 14 14 3 8 6 8 7 7 28 28 28 28 28 28 6 1 7 8 8 8 7 1 8 8 8 R R/W R/W R/W R/W
2 - Register map
Description Audio Bit Buffer Level. Audio Bit Buffer Level. Audio Bit Buffer Stop. Audio Bit Buffer Stop. Audio Bit Buffer Threshold. Audio Bit Buffer Threshold. Decoded Frame Size. Decoded Frame Width. Displayed Frame Width. Scan vector OSD Top Field Pointer. OSD Bottom Field Pointer. Pan/Scan Horizontal Vector Integer Part. Pan/Scan Horizontal Vector Integer Part. Panic threshold. Panic threshold. Clock Generator PLL Parameters. Clock Generator Configuration. Smart-Card Clock Divider. Link Clock Divider. Pixel Clock Divider. Pcm Clock Divider. Sdram Clock Divider. Auxiliary Clock Divider. DRAM Configuration. Video reset General Configuration. Status. Interrupt Mask. Interrupt Status. On-screen Display Configuration. Load Pointer. PES Audio Decoding Control. PES Video Parser Control. DSM Trick Mode.
Access
VID_ABT[13:8] VID_ABT[7:0] VID_DFS VID_DFW VID_XFW VID_SCN VID_OTP VID_OBP VID_PAN[10:8] VID_PAN[7:0] VID_PTH[13:8] VID_PTH[7:0] CKG_PLL CKG_CFG CKG_SMC CKG_LNK CKG_PXC CKG_PCM CKG_MCK CKG_AUX CFG_DRC VID_RSTV CFG_GCF VID_STA1 VID_ITM1 VID_ITS1 VID_OSD VID_LDP PES_CF1 PES_CF2 PES_TM1
Serial R/W R/W R/W R/W Serial R/W Serial R/W R/W R/W R/W R/W R/W R/W Serial R/W Serial R/W Serial R/W Serial R/W Serial R/W Serial R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R
0x0000102A 0x0000102B 0x0000102C 0x0000102D 0x0000102E 0x0000102F 0x00001030 0x00001031 0x00001032 0x00001033 0x00001034 0x00001035 0x00001036 0x00001037 0x00001038 0x00001039 0x0000103A 0x0000103B 0x0000103C 0x0000103D 0x0000103E 0x0000103F 0x00001040 0x00001041 0x00001042
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2 - Register map
Register PES_TM2 CFG_CDR VID_FRZ
PES_TS[7:0]
CO
D I F N
Address
0x00001043 0x00001044
L A I T N E
Bits 2 R 8 1 8 8 8 8 2 19 19 3 8 3 8 5 5 4 8 6 8 6 8 6 8 6 8 8 8 8 8 8 8 16 24 24 W R/W R R R R R
STi5500
Description PES Parser Status. Compressed Data Input. Freeze Display. PES Time Stamps. PES Time Stamps. PES Time Stamps. PES Time Stamps. PES Time Stamps. Sub-picture Read Pointer. Sub-picture Write Pointer. Sub-picture Buffer Begin. Sub-picture Buffer Begin. Sub-picture Buffer End. Sub-picture Buffer End. Luma vertical filter Chroma vertical filter Temporal Reference. Temporal Reference. Displayed Chroma Frame Pointer. Displayed Chroma Frame Pointer. Reconstructed Chroma Frame Pointer. Reconstructed Chroma Frame Pointer. Forward Chroma Frame Pointer. Forward Chroma Frame Pointer. Backward Chroma Pointer. Backward Chroma Pointer. Interrupt Mask. Interrupt Mask. Interrupt Status. Interrupt Status. Status. Status. Header Data FIFO. Bit Buffer Input Counter. Bit Buffer Output Counter.
Access
0x00001045 0x00001049
PES_TS[15:8] PES_TS[23:16] PES_TS[31:24] PES_TS[33:32] VID_SPRead VID_SPWrite VID_SPB[10:8] VID_SPB[7:0] VID_SPE[10:8] VID_SPE[7:0] VID_VFL VID_VFC VID_TRF[11:8] VID_TRF[7:0] VID_DFC[13:8] VID_DFC[7:0] VID_RFC[13:8] VID_RFC[7:0] VID_FFC[13:8] VID_FFC[7:0] VID_BFC[13:8] VID_BFC[7:0] VID_ITM2 VID_ITM3 VID_ITS2 VID_ITS3 VID_STA2 VID_STA3 VID_HDF VID_CDcount VID_SCDcount
0x0000104A 0x0000104B 0x0000104C 0x0000104D 0x0000104E 0x0000104F 0x00001050 0x00001051 0x00001052 0x00001053 0x00001054 0x00001055 0x00001056 0x00001057 0x00001058 0x00001059 0x0000105A 0x0000105B 0x0000105C 0x0000105D 0x0000105E 0x0000105F 0x00001060 0x00001061 0x00001062 0x00001063 0x00001064 0x00001065 0x00001066 0x00001067 0x00001068
Serial R/W Serial R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R Serial R Serial R Serial R
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STi5500
Register VID_HDS VID_LSO VID_LSR
VID_CSO VID_CSR VID_YDO VID_YDS
CO
D I F N
Address
0x00001069
L A I T N E
Bits 4 R/W 8 8 8 8 8 8 2 8 2 8 5 6 8 8 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R R/W R/W R/W
2 - Register map
Description Header Search. SRC Luminance Offset. SRC Luma Resolution. SRC Chrominance Offset. SRC Chrominance Resolution. Display Y Offset. Display Y End. Display X Offset. Display X Offset. Display X End. Display X End. Display Configuration. Display Configuration. Quantization Matrix Data. STi5500 Revision. Audio reset Not-writable-register mode Little endian - big endian conversion
Access
0x0000106A 0x0000106B
0x0000106C 0x0000106D 0x0000106E 0x0000106F 0x00001070 0x00001071 0x00001072 0x00001073 0x00001074 0x00001075 0x00001076 0x00001078 0x0000107A 0x0000107B 0x0000107C
VID_XDO[9:8] VID_XDO[7:0] VID_XDS[9:8] VID_XDS[7:0] VID_DCF[14:7] VID_DCF[6:0] VID_QMW VID_REV VID_RSTA VID_NWM VID_END
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2 - Register map
Register AUD_ANC[7:0]
AUD_ANC[15:8]
AUD_ANC[23:16] AUD_ANC[31:24] AUD_ESC[7:0] AUD_ESC[15:8] AUD_ESC[23:16] AUD_ESC[31:24] AUD_ESC[33:32] AUD_ESCX[7:0] AUD_LRP AUD_FFL[7:0] AUD_FFL[15:8] AUD_P18 AUD_CDI AUD_FOR AUD_ITR[7:0] AUD_ITR[14:8] AUD_ITM[7:0] AUD_ITM[14:8] AUD_LCA AUD_EXT AUD_RCA AUD_SID AUD_SYN AUD_IDE AUD_SCM AUD_SYS AUD_SYE AUD_LCK AUD_CRC AUD_SEM AUD_PLY AUD_MUT
CO
D I F N
Address
L A I T N E
Bits 8 8 8 8 8 8 8 8 2 8 1 8 8 1 8 1 8 7 8 7 6 2 6 5 2 1 1 2 8 2 2 2 1 1 R R R R R R R R R R R/W R/W R/W R/W W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W
STi5500
Access
Description Ancillary Data Buffer. Ancillary Data Buffer. Ancillary Data Buffer. Ancillary Data Buffer. Elementary Stream Clock Reference. Elementary Stream Clock Reference. Elementary Stream Clock Reference. Elementary Stream Clock Reference. Elementary Stream Clock Reference. Elementary Stream Clock Reference. LRCK Polarity. Free-Format Frame Length. Free-Format Frame Length. PCM Output Precision. Compressed Data Input. PCM Output Format. Interrupt Status Request Register. Interrupt Status Request Register. Interrupt Mask Register. Interrupt Mask Register. Left Channel Attenuation. Decoding Mode Extension. Right Channel Attenuation. Audio Stream ID. Packet Sync Mode. Audio Stream ID Enable. Sync Confirmation Mode. Synchronization Status. Sync Word Extension. Sync Words Until Lock. CRC Error Concealment Mode. Sync Error Concealment Mode. Play. Mute.
0x00001206 0x00001207 0x00001208 0x00001209
0x0000120A 0x0000120B 0x0000120C 0x0000120D 0x0000120E 0x0000120F 0x00001211 0x00001214 0x00001215 0x00001216 0x00001218 0x00001219 0x0000121A 0x0000121B 0x0000121C 0x0000121D 0x0000121E 0x0000121F 0x00001220 0x00001222 0x00001223 0x00001224 0x00001225 0x00001226 0x00001227 0x00001228 0x0000122A 0x0000122C 0x0000122E 0x00001230
Table 2.2 MPEG audio decoder registers
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STi5500
Register AUD_SKP AUD_ISS
AUD_ORD AUD_RES AUD_RST AUD_SFR AUD_DEM AUD_IFT AUD_SCP AUD_ITS AUD_IMS
CO
D I F N
Address
0x00001232 0x00001236 0x00001238 0x00001240 0x00001242 0x00001244 0x00001246 0x00001252
L A I T N E
Bits 1 3 1 1 1 2 2 8 1 2 2 8 8 8 8 8 8 8 8 1 6 8 6 1 1 R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R R R R R R R R R R R R/W R/W R/W
2 - Register map
Description Skip Next Frame. Input Stream Selection. PCM Output Bit Order. Audio Decoder Software Reset. Restart. Sampling Frequency. De-Emphasis Mode. Input FIFO Threshold. SCLK Polarity. Audio Interrupt Extension. Audio Interrupt Extension Mask. Frame Header. Frame Header. Frame Header. Frame Header. Presentation Time Stamp. Presentation Time Stamp. Presentation Time Stamp. Presentation Time Stamp. Presentation Time Stamp. Ancillary Data Buffer Size. Audio Decoder Revision. PCM Clock Divider. PCM Output Justification. Bit Buffer Enable.
Access
0x00001253 0x0000125B 0x0000125C 0x0000125E 0x0000125F 0x00001260 0x00001261 0x00001262 0x00001263 0x00001264 0x00001265 0x00001266 0x0000126C 0x0000122D 0x0000126E 0x0000126F 0x00001270
AUD_HDR[7:0] AUD_HDR[15:8] AUD_HDR[23:16] AUD_HDR[31:24] AUD_PTS[7:0] AUD_PTS[15:8] AUD_PTS[23:16] AUD_PTS[31:24] AUD_PTS[32] AUD_ADA AUD_VER AUD_DIV AUD_DIF AUD_BBE
Table 2.2 MPEG audio decoder registers Register SPD_CTL1 SPD_RST SPD_CTL2 SPD_LUT SPD_XD0[9:8] SPD_XD0[7:0] SPD_YD0[9:8] Address 0x00001400 0x00001401 0x00001402 0x00001403 0x00001404 0x00001405 0x00001406 Bits 6 1 2 8 2 8 2 Access R/W R/W R/W R/W R/W R/W R/W Control Register 1. Sub-picture reset Control Register 2. Main Lookup Table. Sub-picture X Offset. Sub-picture X Offset. Sub-picture Y Offset. Description
Table 2.3 Sub-picture decoder registers
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2 - Register map
Register SPD_YD0[7:0] SPD_XD1[9:8] SPD_XD1[7:0] SPD_YD1[9:8] SPD_YD1[7:0] SPD_HLSX[9:8] SPD_HLSX[7:0] SPD_HLSY[9:8] SPD_HLSY[7:0] SPD_HLEX[9:8] SPD_HLEX[7:0] SPD_HLEY[9:8] SPD_HLEY[7:0] SPD_HLRCO1 SPD_HLRCO2 SPD_HLRC1 SPD_HLRC2 SPD_SXD0[9:8] SPD_SXD0[7:0] SPD_SYD0[9:8] SPD_SYD0[7:0] SPD_SXD1[9:8] SPD_SXD1[7:0] SPD_SYD1[9:8] SPD_SYD1[7:0] SPD_SPRead SPD_SPWrite SPD_SPB1[0:8] SPD_SPB[7:0] SPD_SPE[10:8] SPD_SPE[7:0]
CO
D I F N
Address
0x00001407 0x00001408 0x00001409
L A I T N E
Bits 8 2 8 2 8 2 8 2 8 2 8 2 8 8 8 8 8 2 8 2 8 2 8 2 8 19 19 3 8 3 8 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
STi5500
Description Sub-picture Y Offset. Sub-picture X Offset. Sub-picture X Offset. Sub-picture Y Offset. Sub-picture Y Offset. Highlight Region Start X. Highlight Region Start X. Highlight Region Start Y. Highlight Region Start Y. Highlight Region End X. Highlight Region End X. Highlight Region End Y. Highlight Region End Y. Highlight Region Color. Highlight Region Color. Highlight Region Contrast. Highlight Region Contrast. Sub-picture Display Area. Sub-picture Display Area. Sub-picture Display Area. Sub-picture Display Area. Sub-picture Display Area. Sub-picture Display Area. Sub-picture Display Area. Sub-picture Display Area. Sub-picture Read Pointer. Sub-picture Write Pointer. Sub-picture Buffer Begin. Sub-picture Buffer Begin. Sub-picture Buffer End. Sub-picture Buffer End.
Access
0x0000140A 0x0000140B 0x0000140C 0x0000140D 0x0000140E 0x0000140F 0x00001410 0x00001411 0x00001412 0x00001413 0x00001414 0x00001415 0x00001416 0x00001417 0x00001424 0x00001425 0x00001426 0x00001427 0x00001428 0x00001429 0x0000142A 0x0000142B 0x0000144E 0x0000144F 0x00001450 0x00001451 0x00001452 0x00001453
Table 2.3 Sub-picture decoder registers
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configuration0 configuration1 configuration2 configuration3 configuration4 configuration5 configuration6 status
CO
Register
D I F N
Address
L A I T N E
Bits Access 8 8 8 8 8 7 6 8 8 8 8 2 8 8 8 8 8 8 4 8 8 8 8 8 8 8 8 8 8 8 5 5 R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
2 - Register map
Description General configuration. General configuration. General configuration. General configuration. General configuration. General configuration. General configuration. Status. Increment for digital frequency synthesizer. Increment for digital frequency synthesizer. Increment for digital frequency synthesizer. Static phase offset for digital frequency synthesizer. Static phase offset for digital frequency synthesizer. Digital encoder identification number. Digital encoder revision identification number. Line jump. Line jump. Line jump. CGMS data register. CGMS data register. CGMS data register. Teletext block definition. Teletext block definition. Teletext block definition. Teletext block definition. Teletext block mapping. Closed caption characters/extended data for field 1. Closed caption characters/extended data for field 1. Closed caption characters/extended data for field 2. Closed caption characters/extended data for field 2. Closed caption/extended data line insertion for field 1 Closed caption/extended data line insertion for field 2
0x00001600 0x00001601 0x00001602 0x00001603 0x00001604 0x00001605 0x00001606 0x00001609 0x0000160A 0x0000160B 0x0000160C 0x0000160D 0x0000160E 0x00001611 0x00001612 0x00001615 0x00001616 0x00001617 0x0000161F 0x00001620 0x00001621 0x00001622 0x00001623 0x00001624 0x00001625 0x00001626 0x00001627
increment_dfs[23:16] increment_dfs[15:8] increment_dfs[7:0] phase_dfs[23:22] phase_dfs[21:14] chipid revid line_reg line_reg line_reg cgms[1:4] cgms[5:12] cgms[13:20] ttx_block1 ttx_block2 ttx_block3 ttx_block4 ttx_block_map cccf1
0x00001628 0x00001629
cccf2 cclif1 cclif2
0x0000162A 0x0000162B 0x0000162C
Table 2.4 PAL/NTSC encoder (DENC) registers
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2 - Register map
Register
EMIConfigData0Bank0 EMIConfigData1Bank0 EMIConfigData2Bank0 EMIConfigData3Bank0 EMIConfigData0Bank1 EMIConfigData1Bank1 EMIConfigData2Bank1 EMIConfigData3Bank1 EMIConfigData0Bank2 EMIConfigData1Bank2 EMIConfigData2Bank2 EMIConfigData3Bank2 EMIConfigData0Bank3 EMIConfigData1Bank3 EMIConfigData2Bank3 EMIConfigData3Bank3 EMIConfigLockBank0 EMIConfigLockBank1 EMIConfigLockBank2 EMIConfigLockBank3 EMIConfigStatus EMIDRAMInitialize
CO
D I F N
Address
L A I T N E
Bits 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 1 1 1 1 8 1 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W W R W
STi5500
Description EMI bank 0 configuration data register 0. EMI bank 0 configuration data register 1. EMI bank 0 configuration data register 2. EMI bank 0 configuration data register 3. EMI bank 1 configuration data register 0. EMI bank 1 configuration data register 1. EMI bank 1 configuration data register 2. EMI bank 1 configuration data register 3. EMI bank 2 configuration data register 0. EMI bank 2 configuration data register 1. EMI bank 2 configuration data register 2. EMI bank 2 configuration data register 3. EMI bank 3 configuration data register 0. EMI bank 3 configuration data register 1. EMI bank 3 configuration data register 2. EMI bank 3 configuration data register 3. Write protection bit for bank 0. Write protection bit for bank 1. Write protection bit for bank 2. Write protection bit for bank 3. EMI configuration status information. Initialize any DRAM in the system.
0x00002000 0x00002004 0x00002008
0x0000200C 0x00002010 0x00002014 0x00002018 0x0000201C 0x00002020 0x00002024 0x00002028 0x0000202C 0x00002030 0x00002034 0x00002038 0x0000203C 0x00002040 0x00002044 0x00002048 0x0000204C 0x00002050 0x00002060
Table 2.5 EMI configuration registers
Register CacheControl SelectCache InvalidateDCache InvalidateICache FlushDCache CacheControlLock
Address 0x00004000 0x00004100 0x00004200 0x00004300 0x00004400 0x00004500
Bits 8 2 1 1 1 1
Access R/W W W W W R/W
Description Cacheability of memory. Select and enable the caches. Invalidate the data cache. Invalidate the instruction cache. Flush the data cache. Lock the cache configuration.
Table 2.6 Cache control registers
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Register HandlerWptr0 HandlerWptr1 HandlerWptr2 HandlerWptr3 HandlerWptr4 HandlerWptr5 HandlerWptr6 HandlerWptr7 TriggerMode0 TriggerMode1 TriggerMode2 TriggerMode3 TriggerMode4 TriggerMode5 TriggerMode6 TriggerMode7 Mask Set_Mask Clear_Mask Pending Set_Pending Clear_Pending Exec Set_Exec Clear_Exec
CO
D I F N
Address
L A I T N E
Bits 32 32 32 32 32 32 32 32 3 3 3 3 3 3 3 3 17 17 17 8 8 8 8 8 8 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W R/W W W R/W W W
2 - Register map
Description Interrupt handler 0 work space pointer. Interrupt handler 1 work space pointer. Interrupt handler 2 work space pointer. Interrupt handler 3 work space pointer. Interrupt handler 4 work space pointer. Interrupt handler 5 work space pointer. Interrupt handler 6 work space pointer. Interrupt handler 7 work space pointer. Interrupt 0 trigger mode. Interrupt 1 trigger mode. Interrupt 2 trigger mode. Interrupt trigger mode. Interrupt 3 trigger mode. Interrupt 4 trigger mode. Interrupt 5 trigger mode. Interrupt 6 trigger mode. Interrupt enable mask. Set a bit of the interrupt enable mask. Clear a bit of the interrupt enable mask. Interrupt pending. Set a bit of the Pending register. Clear a bit of the Pending register. Interrupts executing. Set a bit of the Exec register. Clear a bit of the Exec register.
0x20000000 0x20000004 0x20000008
0x2000000C 0x20000010 0x20000014 0x20000018 0x2000001C 0x20000040 0x20000044 0x20000048 0x2000004C 0x20000050 0x20000054 0x20000058 0x2000005C 0x200000C0 0x200000C4 0x200000C8 0x20000080 0x20000084 0x20000088 0x20000100 0x20000104 0x20000108
Table 2.7 Interrupt controller registers
Name STREAM_EN_REGn LINK_STAT_REG LINK_STAT_FIFO PACKET_LENGTH TIME_OUT_REG
Address 0x20002F00 +4n 0x20002F80 0x20002F84 0x20002F88 0x20002F8C
Bits 1 21 32 12 6
Access R/W R/W R R/W R/W Stream n enable. Status register. FIFO status word.
Description
Number of bytes per packet. AR threshold to reset the block.
Table 2.8 Transport stream demultiplexor registers
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2 - Register map
Name MODE_REG
PCR_STREAM_REG AF_REG0 AF_REG1
CO
D I F N
Address
0x20002F90
L A I T N E
Bits 10 6 32 32 32 32 32 9 6 27 6 32 1 13 Access R/W R/W R R R R R R R/W R/W R/W R/W R/W R/W
STi5500
Description Mode. PCR stream. Adaptation field bytes 0 to 3. Adaptation field bytes 4 to 7. Video time stamp. Audio time stamp. PCR. PCR extension. AR size. SDAV configuration. SDAV DMA enable. SDAV data. Enable link. Extra bits.
0x20002F94 0x20002F98
0x20002F9C 0x20002FA0 0x20002FA4 0x20002FA8 0x20002FAC 0x20002FB0 0x20002FB4 0x20002FB8 0x20002FBC 0x20002FC0 0x20002FC8
V_PTS_REG A_PTS_REG PCR_REG PCR_EXT_REG AR_SIZE_REG SDAV_CONF_REG SDAV_DMA_EN_REG SDAV_DATA_REG EN_LINK_REG EXTRA_BITS_REG
Table 2.8 Transport stream demultiplexor registers
Register ASC0BaudRate ASC0TxBuffer ASC0RxBuffer ASC0Control ASC0IntEnable ASC0Status ASC0Guardtime ASC0TimeOut ASC0TxReset ASC0RxReset
Address 0x20003000 0x20003004 0x20003008 0x2000300C 0x20003010 0x20003014 0x20003018 0x2000301C 0x20003020 0x20003024
Bits 16 9 9 10 6 6 8 8 0 0
Access R/W W R R/W R/W R R/W R/W W W
Description ASC 0 Baud rate generator/reload. ASC 0 Output buffer. ASC 0 Input buffer. ASC 0 Control register. ASC 0 Enable interrupts. ASC 0 Interrupt status. ASC 0 Guard Time. ASC 0 Time Out. ASC 0 Output Fifo Reset. ASC 0 Input Fifo Reset.
Table 2.9 ASC 0 registers
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Register ASC1BaudRate ASC1TxBuffer
ASC1RxBuffer ASC1Control ASC1IntEnable ASC1Status ASC1Guardtime ASC1TimeOut ASC1TxReset ASC1RxReset
CO
D I F N
Address
L A I T N E
Bits 16 9 9 10 6 6 8 8 0 0 Access R/W W R R/W R/W R R/W R/W W W ASC 1 Output buffer. ASC 1 Input buffer.
2 - Register map
Description ASC 1 Baud rate generator/reload.
0x20004000 0x20004004 0x20004008
0x2000400C 0x20004010 0x20004014 0x20004018 0x2000401C 0x20004020 0x20004024
ASC 1 Control register. ASC 1 Enable interrupts. ASC 1 Interrupt status. ASC 1 Guard Time. ASC 1 Time Out. ASC 1 Output Fifo Reset. ASC 1 Input Fifo Reset.
Table 2.10 ASC 1 registers
Register ASC2BaudRate ASC2TxBuffer ASC2RxBuffer ASC2Control ASC2IntEnable ASC2Status ASC2TimeOut ASC2Guardtime ASC2TimeOut ASC2TxReset ASC2RxReset
Address 0x20005000 0x20005004 0x20005008 0x2000500C 0x20005010 0x20005014 0x2000501C 0x20005018 0x2000501C 0x20005020 0x20005024
Bits 16 9 9 10 6 6 8 8 8 0 0
Access R/W W R R/W R/W R R/W R/W R/W W W
Description ASC 2 Baud rate generator/reload. ASC 2 Output buffer. ASC 2 Input buffer. ASC 2 Control register. ASC 2 Enable interrupts. ASC 2 Interrupt status. ASC 2 Time Out. ASC 2 Guard Time. ASC 2 Time Out. ASC 2 Output Fifo Reset. ASC 2 Input Fifo Reset.
Table 2.11 ASC 2 registers (SmartCard0)
Register ASC3BaudRate ASC3TxBuffer ASC3RxBuffer ASC3Control ASC3IntEnable
Address 0x20006000 0x20006004 0x20006008 0x2000600C 0x20006010
Bits 16 9 9 10 6
Access R/W W R R/W R/W
Description ASC 3 Baud rate generator/reload. ASC 3 Output buffer. ASC 3 Input buffer. ASC 3 Control register. ASC 3 Enable interrupts.
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2 - Register map
Register ASC3Status
ASC3Guardtime ASC3TimeOut ASC3TxReset
CO
D I F N
Address
0x20006014 0x20006018
L A I T N E
Bits 6 8 8 0 0 Access R R/W R/W W W
STi5500
Description ASC 3 Interrupt status. ASC 3 Guard Time. ASC 3 Time Out. ASC 3 Output Fifo Reset. ASC 3 Input Fifo Reset.
0x2000601C 0x20006020 0x20006024
ASC3RxReset
Register Sc0ClkVal Sc0ClkCon
Address 0x20007000 0x20007004
Bits 5 2
Access W W SmartCard 0 clock.
Description
SmartCard 0 clock control.
Table 2.13 SmartCard 0 registers
Register Sc1ClkVal Sc1ClkCon
Address 0x20008000 0x20008004
Bits 5 2
Access W W SmartCard 1 clock.
Description
SmartCard 1 clock control.
Table 2.14 SmartCard 1 registers
Register SSC0BRG SSC0TBuf SSC0RBuf SSC0Con SSC0IEn SSC0Stat SSC0SlAd
Address 0x20009000 0x20009004 0x20009008 0x2000900C 0x20009010 0x20009014 0x2000901C
Bits 10 16 16 11 9 10 16
Access R/W W R R/W R/W R W
Description SSC baud rate generation. SSC transmit buffer. SSC receive buffer. SSC control. SSC interrupt enable. SSC status. SSC slave address.
Table 2.15 SSC registers
Register PWM0Val PWM1Val PWM2Val PWM3Val PWMIntEnable PWMIntStatus
Address 0x2000B000 0x2000B004 0x2000B008 0x2000B00C 0x2000B054 0x2000B058
Bits 9 9 9 9 9 9
Access R/W R/W R/W R/W R/W R PWM 0 pulse width. PWM 1 pulse width. PWM 2 pulse width. PWM 3 pulse width.
Description
PWM interrupt enable. PWM interrupt status.
Table 2.16 PWM/counter module registers
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Register PWMIntAck PWMControl PWMCount
PWM0CaptureEdge PWM1CaptureEdge PWM2CaptureEdge PWM3CaptureEdge PWM0CaptureVal PWM1CaptureVal PWM2CaptureVal PWM3CaptureVal PWM0CompareVal PWM1CompareVal PWM2CompareVal PWM3CompareVal PWM0CompareOutVal PWM1CompareOutVal PWM2CompareOutVal PWM3CompareOutVal PWMCaptureCount
CO
D I F N
Address
0x2000B05C 0x2000B050 0x2000B060 0x2000B030 0x2000B034 0x2000B038 0x2000B03C 0x2000B010 0x2000B014 0x2000B018 0x2000B01C 0x2000B020 0x2000B024 0x2000B028 0x2000B02C 0x2000B040 0x2000B044 0x2000B048 0x2000B04C 0x2000B064
L A I T N E
Bits 9 Access W 11 8 2 2 2 2 32 32 32 32 32 32 32 32 1 1 1 1 32 R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W
2 - Register map
Description PWM interrupt acknowledge. PWM control register. PWM output counter. PWM 0 capture event definition. PWM 1 capture event definition. PWM 2 capture event definition. PWM 3 capture event definition. PWM 0 capture value. PWM 1 capture value. PWM 2 capture value. PWM 3 capture value. PWM 0 compare value. PWM 1 compare value. PWM 2 compare value. PWM 3 compare value. PWM 0 compare output value. PWM 1 compare output value. PWM 2 compare output value. PWM 3 compare output value. PWM capture/compare counter.
Table 2.16 PWM/counter module registers
Register P0Out Set_P0Out Clear_P0Out P0In P0C0 Set_P0C0 Clear_P0C0 P0C1 Set_P0C1 Clear_P0C1 P0C2 Set_P0C2
Address 0x2000C000 0x2000C004 0x2000C008 0x2000C010 0x2000C020 0x2000C024 0x2000C028 0x2000C030 0x2000C034 0x2000C038 0x2000C040 0x2000C044
Bits 8 8 8 8 8 8 8 8 8 8 8 8
Access R/W W W R R/W W W R/W W W R/W W PIO 0 output. Set bits of P0Out. Clear bits of P0Out. PIO 0 input.
Description
PIO 0 configuration 0. Set bits of P0C0. Clear bits of P0C0. PIO 0 configuration 1. Set bits of P0C1. Clear bits of P0C1. PIO 0 configuration 2. Set bits of P0C2.
Table 2.17 Parallel I/O PIO 0 registers
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2 - Register map
Register Clear_P0C2 P0Comp
Set_P0Comp
Clear_P0Comp P0Mask Set_P0Mask Clear_P0Mask
CO
D I F N
Address
0x2000C048
L A I T N E
Bits 8 Access W 8 8 8 8 8 8 R/W W W R/W W W
STi5500
Description Clear bits of P0C2. PIO 0 input comparison. Set bits of P0Comp. Clear bits of P0Comp. PIO 0 input comparison mask. Set bits of P0Mask. Clear bits of P0Mask.
0x2000C050 0x2000C054 0x2000C058 0x2000C060 0x2000C064 0x2000C068
Register P1Out Set_P1Out Clear_P1Out P1In P1C0 Set_P1C0 Clear_P1C0 P1C1 Set_P1C1 Clear_P1C1 P1C2 Set_P1C2 Clear_P1C2 P1Comp Set_P1Comp Clear_P1Comp P1Mask Set_P1Mask Clear_P1Mask
Address 0x2000D000 0x2000D004 0x2000D008 0x2000D010 0x2000D020 0x2000D024 0x2000D028 0x2000D030 0x2000D034 0x2000D038 0x2000D040 0x2000D044 0x2000D048 0x2000D050 0x2000D054 0x2000D058 0x2000D060 0x2000D064 0x2000D068
Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Access R/W W W R R/W W W R/W W W R/W W W R/W W W R/W W W PIO 1 output. Set bits of P1Out. Clear bits of P1Out. PIO 1 input.
Description
PIO 1 configuration 0. Set bits of P1C0. Clear bits of P1C0. PIO 1 configuration 1. Set bits of P1C1. Clear bits of P1C1. PIO 1 configuration 2. Set bits of P1C2. Clear bits of P1C2. PIO 1 input comparison. Set bits of P1Comp. Clear bits of P1Comp. PIO 1 input comparison mask. Set bits of P1Mask. Clear bits of P1Mask.
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Register P2Out
Set_P2Out
Clear_P2Out P2In P2C0 Set_P2C0 Clear_P2C0 P2C1 Set_P2C1 Clear_P2C1 P2C2 Set_P2C2 Clear_P2C2 P2Comp
CO
D I F N
Address
L A I T N E
Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access R/W W W R R/W W W R/W W W R/W W W R/W W W R/W W W PIO 2 output. Set bits of P2Out. Clear bits of P2Out. PIO 2 input.
2 - Register map
Description
0x2000E000 0x2000E004 0x2000E008 0x2000E010 0x2000E020 0x2000E024 0x2000E028 0x2000E030 0x2000E034 0x2000E038 0x2000E040 0x2000E044 0x2000E048 0x2000E050 0x2000E054 0x2000E058 0x2000E060 0x2000E064 0x2000E068
Set_P2Comp Clear_P2Comp P2Mask Set_P2Mask Clear_P2Mask
Register P3Out Set_P3Out Clear_P3Out P3In P3C0 Set_P3C0 Clear_P3C0 P3C1 Set_P3C1 Clear_P3C1 P3C2 Set_P3C2
Address 0x2000F000 0x2000F004 0x2000F008 0x2000F010 0x2000F020 0x2000F024 0x2000F028 0x2000F030 0x2000F034 0x2000F038 0x2000F040 0x2000F044
Bits 8 8 8 8 8 8 8 8 8 8 8 8
Access R/W W W R R/W W W R/W W W R/W W PIO 3 output. Set bits of P3Out. Clear bits of P3Out. PIO 3 input.
Description
PIO 3 configuration 0. Set bits of P3C0. Clear bits of P3C0. PIO 3 configuration 1. Set bits of P3C1. Clear bits of P3C1. PIO 3 configuration 2. Set bits of P3C2.
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2 - Register map
Register Clear_P3C2 P3Comp
Set_P3Comp
Clear_P3Comp P3Mask Set_P3Mask Clear_P3Mask
CO
D I F N
Address
0x2000F048
L A I T N E
Bits 8 Access W 8 8 8 8 8 8 R/W W W R/W W W
STi5500
Description Clear bits of P3C2. PIO 3 input comparison. Set bits of P3Comp. Clear bits of P3Comp. PIO 3 input comparison mask. Set bits of P3Mask. Clear bits of P3Mask.
0x2000F050 0x2000F054 0x2000F058 0x2000F060 0x2000F064 0x2000F068
Register P4Out Set_P4Out Clear_P4Out P4In P4C0 Set_P4C0 Clear_P4C0 P4C1 Set_P4C1 Clear_P4C1 P4C2 Set_P4C2 Clear_P4C2 P4Comp Set_P4Comp Clear_P4Comp P4Mask Set_P4Mask Clear_P4Mask
Address 0x20010000 0x20010004 0x20010008 0x20010010 0x20010020 0x20010024 0x20010028 0x20010030 0x20010034 0x20010038 0x20010040 0x20010044 0x20010048 0x20010050 0x20010054 0x20010058 0x20010060 0x20010064 0x20010068
Bits 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Access R/W W W R R/W W W R/W W W R/W W W R/W W W R/W W W PIO 4 output. Set bits of P4Out. Clear bits of P4Out. PIO 4 input.
Description
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Register Int0Priority Int1Priority Int2Priority Int3Priority Int4Priority Int5Priority Int6Priority Int7Priority Int8Priority Int9Priority Int10Priority Int11Priority Int12Priority Int13Priority Int14Priority Int15Priority Int16Priority Int17Priority Int18Priority Int19Priority Int20Priority InputInterrupts
CO
D I F N
Address
L A I T N E
Bits 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 21 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Interrupt 0 priority. Interrupt 1 priority. Interrupt 2 priority. Interrupt 3 priority. Interrupt 4 priority. Interrupt 5 priority. Interrupt 6 priority. Interrupt 7 priority. Interrupt 8 priority. Interrupt 9 priority. Interrupt 10 priority. Interrupt 11 priority. Interrupt 12 priority. Interrupt 13 priority. Interrupt 14 priority. Interrupt 15 priority. Interrupt 16 priority. Interrupt 17 priority. Interrupt 18 priority. Interrupt 19 priority. Interrupt 20 priority.
2 - Register map
Description
0x20011000 0x20011004 0x20011008
0x2001100C 0x20011010 0x20011014 0x20011018 0x2001101C 0x20011020 0x20011024 0x20011028 0x2001102C 0x20011030 0x20011034 0x20011038 0x2001103C 0x20011040 0x20011044 0x20011048 0x2001104C 0x20011050 0x2001107C
Input interrupt status.
Table 2.22 Interrupt level controller registers
Register MPEG0BurstSize MPEG0Holdoff MPEG0Suspend MPEG0DecoderSelect
Address 0x20020000 0x20020004 0x20020008 0x2002000C
Bits 5 5 1 2
Access W W W W
Description MPEG DMA0 burst size. MPEG DMA0 hold-off time. MPEG DMA0 suspend. MPEG DMA0 decoder select.
Table 2.23 MPEG DMA 0 controller registers
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2 - Register map
Register
MPEG1BurstSize MPEG1Holdoff
MPEG1Suspend
MPEG1DecoderSelect
CO
D I F N
Address
0x20021000
L A I T N E
Bits 5 Access W 5 1 2 W W W
STi5500
0x20021004
0x20021008
0x2002100C
Register MPEG2BurstSize MPEG2Holdoff MPEG2Suspend MPEG2DecoderSelect
Address 0x20022000 0x20022004 0x20022008 0x2002200C
Bits 5 5 1 2
Access W W W W
Register TtxtDmaAddress TtxtDmaCount TtxtOutDelay TtxtMode TtxtIntStatus TtxtIntEnable TtxtAckOddEven TtxAbort
Address 0x20024000 0x20024004 0x20024008 0x20024014 0x20024018 0x2002401C 0x20024020 0x20024024
Bits 32 11 9 2 3 3 1 1
Access R/W R/W R/W R/W R R/W W W
Description Teletext DMA address. Teletext DMA count. Teletext output delay. Teletext mode. Teletext interrupt status. Teletext interrupt enable. Teletext acknowledge odd or even. Teletext abort.
Table 2.26 Teletext interface registers
Register BMDMADestAddress
Address 0x20026000
Bits 32
Access W
Description Block move DMA destination address.
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ASCnBaudRate
0x00 Address: Access: Reset state:
L A I T Asynchronous serial controller (ASC) registers N E D I F N O C

ASCn baud rate generator
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
3 - Asynchronous serial controller (ASC) registers
ReloadVal
ASCnBaseAddress + 0x00 Read/write 1
Description
The ASCnBaudRate register is the dual-function baud rate generator and reload value register. A read from this register returns the content of the 16-bit timer; writing to it updates the 16-bit reload register. If the Run bit of the control register is 1, then any value written in the ASCnBaudRate register is immediately copied to the timer. However, if the Run bit is 0 when the register is written, then the timer will not be reloaded until the first CPU clock cycle after the Run bit is 1. The baud rate and the required reload value for a given baud rate can be determined by the following formulae:
BaudRate =
fCPU 16 x RegisterVal fCPU 16 x BaudRate
RegisterVal =
where: RegisterVal represents the content of the ASCnBaudRate register, taken as an unsigned 16-bit integer, fCPU is the frequency of the CPU. Table 3.1 lists commonly used baud rates with the required reload values and the approximate deviation errors for an example baud rate with a CPU clock of 50 MHz. This does not imply availability of a 50 MHz device. Baud rate 625 K 38.4 K 19.2 K 9600 4800 2400 1200 600 300 75 Reload value (exact) 5 81.380 162.760 325.521 651.042 1302.083 2604.167 5208.33 10416.667 41666.667 Reload value (integer) 5 81 163 325 651 1302 2604 5208 10417 41667 Table 3.1 Baud rates Reload value (hex) 0005 0051 00A3 0145 028B 0516 0A2C 1458 28B1 A2C3 Approximate deviation error 0% 0.1% 0.1% 0.2% 0.01% 0.01% 0.01% 0.01% 0.01% 0.01%
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3 - Asynchronous serial controller (ASC) registers ASCnControl ASCn control register
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
LoopBack
ParityOdd
RxEnable
ScEnable
0x0C
CO
Run
D I F N
L A I T N E
STi5500
10
Stop Bits
Mode
Address: Access: Reset state:
ASCnBaseAddress + 0x0C Read/write 0
Description
The ASCnControl register controls the operating mode of the UART ASCn and contains control bits for mode and error check selection, and status flags for error identification. The format of the register is shown in the ASCn control register bit description table below. Programming the mode control field (Mode) to one of the reserved combinations may result in unpredictable behavior. Serial data transmission or reception is only possible when the baud rate generator run bit (Run) is set to 1. When the Run bit is set to 0, TxD will be 1. Setting the Run bit to 0 will immediately freeze the state of the transmitter and receiver. This should only be done when the ASC is idle. Serial data transmission or reception is only possible when the baud rate generator Run bit is set to 1. A transmission is started by writing to the transmit buffer register ASC nTxBuffer.
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Bit
Bit field
CO
2:0
D I F N
Function
ASC mode control:
L A I T N E
Mode
Mode2:0 Mode 000 RESERVED. 001 8-bit data. 010 RESERVED. 011 7-bit data + parity. 100 9-bit data. 101 8-bit data + wake up bit. 110 RESERVED. 111 8-bit data + parity. Number of stop bits selection: StopBits1:0 Number of stop bits 00 0.5 stop bits. 01 1 stop bits. 10 1.5 stop bits. 11 2 stop bits. Parity selection: 0 1 0 1 0 1 0 1 0 1 Even parity (parity bit set on odd number of 1s in data). Odd parity (parity bit set on even number of 1s in data). Standard transmit/receive mode. Loopback mode enabled. Baudrate generator disabled (ASC inactive). Baudrate generator enabled. Receiver disabled. Receiver enabled. SmartCard mode disabled. SmartCard mode enabled.
4:3
StopBits
ParityOdd
Loopback mode enable bit: 6 LoopBack
Baudrate generator run bit: 7 Run
Receiver enable bit: 8 RxEnable
SmartCard enable bit: 9 ScEnable
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3 - Asynchronous serial controller (ASC) registers ASCnIntEnable ASCn interrupt enable
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0x10
CO
RBE
ASCnBaseAddress + 0x10 Read/write 0
Description
Bit 0 Bit field RxBufFullIE Function Receiver buffer full interrupt enable: 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Receiver buffer full interrupt disable. Receiver buffer full interrupt enable. Transmitter empty interrupt disable. Transmitter empty interrupt enable. Transmitter buffer empty interrupt disable. Transmitter buffer empty interrupt enable. Transmitter buffer half empty interrupt disable. Transmitter buffer half empty interrupt enable. Parity error interrupt disable. Parity error interrupt enable. Framing error interrupt disable. Framing error interrupt enable. Overrun error interrupt disable. Overrun error interrupt enable. Time-out when input FIFO or buffer not empty interrupt disable. Time-out when input FIFO or buffer not empty interrupt enable. Time-out when the input FIFO or buffer is empty interrupt disable. Time-out when the input FIFO or buffer is empty interrupt enable. Receiver FIFO is half full interrupt disable. Receiver FIFO is half full interrupt enable.
Transmitter empty interrupt enable: 1 TE TxEmptyIE
Transmitter buffer empty interrupt enable:+ 2 TBE TxBufEmptyIE
Transmitter buffer half empty interrupt enable: 2 THE TxHalfEmptyIE
Parity error interrupt enable: 3 PE ParityErrorIE
Framing error interrupt enable: 4 FE FrameErrorIE
Overrun error interrupt enable: 5 OE OverrunErrorIE
Time-out when not empty interrupt enable: 6 TNE TimeoutNotEmptyIE
Time-out when the receiver FIFO is empty interrupt enable: 7 TOI TimeoutIdleIE
Receiver FIFO is half full interrupt enable: 8 RHF RxHalfFullIE
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RBE
RHF
TNE
TBE
D I F N
L A I T N E
STi5500
TOI
OE
PE
FE
TE
STi5500 ASCnRxBuffer
0x08
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CO
D I F N
ASCn Rx buffer
L A I T N E
RD
ASCnBaseAddress + 0x08 Read only 0
Description
Serial data reception is only possible when the baud rate generator Run bit in the ASCnControl register is set to 1. ASCnRxBufferASCnBaseAddress + #08Read only Bit 0 1 2 3 4 5 6 7 Bit field RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7/Parity Function Receive buffer data D0. Receive buffer data D1. Receive buffer data D2. Receive buffer data D3. Receive buffer data D4. Receive buffer data D5. Receive buffer data D6. Receive buffer data D7, or parity bit - depending on the operating mode (the setting of the Mode bit of the ASCControl register).
Receive buffer data D8, or parity bit, or wake-up bit - depending on the operating mode (the RD8/Parity/ setting of the Mode field of the ASCControl register) Wake/X If the Mode field selects an 8-bit frame then this bit is undefined. Software should ignore this bit when reading 8-bit frames Reserved. Read back 0.
15:9
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3 - Asynchronous serial controller (ASC) registers ASCnStatus ASCn interrupt status
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0x14
CO
RHF
ASCnBaseAddress + 0x14 Read only 3 (i.e. Rx buffer full and Tx buffer empty)
Description
Bit 0 Bit field RBF RxBufFull Function Receiver buffer full flag: 0 1 0 1 0 1 0 2 THE TxHalfEmpty 1 Receiver buffer is not full. Receiver buffer is full. Transmitter is not empty. Transmitter is empty. Transmitter buffer not empty. Transmitter buffer empty. The FIFOs are enabled and the transmitter FIFO is more than half full or the FIFOs are disabled and the transmit buffer is not empty. The FIFOs are enabled and the transmitter FIFO is at least half empty or the FIFOs are disabled and the transmit buffer is empty. No parity error. Parity error. No framing error. Framing error. No overrun error. Overrun error, i.e. data received when the input buffer is full. No time-out or the receiver FIFO or buffer is empty. Time-out when the receiver FIFO or buffer is not empty. No time-out or the receiver FIFO or buffer is not empty. Time-out when the receiver FIFO or buffer is empty. The receiver FIFO contains less than 8 characters. The receiver FIFO contains at least 8 characters. The FIFOs are enabled and the transmitter FIFO is empty or contains less than 16 characters or the FIFOs are disabled and the transmit buffer is empty. The FIFOs are enabled and the transmitter FIFO contains 16 characters or the FIFOs are disabled and the transmit buffer is full.
Transmitter empty flag: 1 TE TxEmpty
Transmitter buffer empty flag: 2 TBE TxBufEmpty
Transmitter FIFO at least half empty flag or buffer empty:
Input parity error flag: 3 PE ParityError 0 1 0 1 0 1 0 1 0 1 0 1 0 9 TF TxFull 1
Input frame error flag, i.e.stop bits not found: 4 FE FrameError
Overrun error flag: 5 OE OverrunError
Time-out when the receiver FIFO or buffer is not empty: 6 TNE TimeoutNotEmpty
Time-out when the receiver FIFO or buffer is empty: 7 TOI TimeoutIdle
Receiver FIFO is half full: 8 RHF RxHalfFull
Transmitter FIFO or buffer is full:
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RBF
TNE
TBE
D I F N
L A I T N E
STi5500
TOI
OE
PE
FE
TE
TF
STi5500 ASCnTimeout
0x1C
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CO
D I F N
ASCn time out
L A I T N E
Timeout
ASCnBaseAddress + 0x1C Read/write 0
Description The time-out period in baud rate ticks. The ASC contains an 8-bit time-out counter, which reloads from ASCnTimeout whenever one or more of the following is true: ASCnRxBuffer is read; the ASC is in the middle of receiving a character; ASCnTimeout is written to. If none of these conditions hold the counter decrements towards 0 at every baud rate tick. The TimeoutNotEmpty bit of the ASCnStatus register is 1 when the input FIFO is not empty and the time-out counter is zero.The TimeoutIdle bit of the ASCnStatus register is 1 when the input FIFO is empty and the time-out counter is zero. When the software has emptied the input FIFO, the time-out counter will reset and start decrementing. If no more characters arrive, when the counter reaches zero the TimeoutIdle bit of the ASCnStatus register will be set.
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3 - Asynchronous serial controller (ASC) registers ASCnTxBuffer

0x04
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CO
D I F N
ASCn Tx buffer
L A I T N E
STi5500
TD
ASCnBaseAddress + 0x04 Write only 0
Description A transmission is started by writing to the transmit buffer register ASCnTxBuffer. Serial data transmission is only possible when the baud rate generator Run bit in the ASCnControl register is set to 1. Data transmission is double-buffered, so a new character may be written to the transmit buffer register before the transmission of the previous character is complete. This allows characters to be sent back-to-back without gaps.
Bit 0 1 2 3 4 5 6 7 Bit field TD0 TD1 TD2 TD3 TD4 TD5 TD6 TD7/Parity TD8/Parity /Wake/0 Function Transmit buffer data D0. Transmit buffer data D1. Transmit buffer data D2. Transmit buffer data D3. Transmit buffer data D4. Transmit buffer data D5. Transmit buffer data D6. Transmit buffer data D7, or parity bit - depending on the operating mode (the setting of the Mode field of the ASCControl register). Transmit buffer data D8, or parity bit, or wake-up bit or undefined - depending on the operating mode (the setting of the Mode field of the ASCControl register). If the Mode field selects an 8-bit frame then this bit should be written as 0. Reserved. Write 0.
8 15:9
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AUD_ADA
0x6C Address: Access: Reset state:
L A I T Audio MPEG (AUD) registers N E D I F N O C

Ancillary Data Buffer Size
6 5 7
4 - Audio MPEG (AUD) registers
AUD_ADA[5:0]
AudioBaseAddress + 0x6C Read only 0
Description
This register holds the number of bits available in the ancillary data buffer, AUD_ANC [31:0]. It is cleared by reading AUD_ANC [31:24].
AUD_ANC
7 0x06 0x07 0x08 0x09 Address: Access: Reset state:
Ancillary Data Buffer

0 AUD_ANC[7:0] AUD_ANC[15:8] AUD_ANC[23:16] AUD_ANC[31:24]
AudioBaseAddress + 0x06 to 0x09 Read only Undefined
Description
The 4 8-bit ancillary data registers constitute a 32-bit FIFO which holds the ancillary data extracted from audio frames. The first bit of ancillary data received is stored in bit AUD_ANC [0]. The extraction of ancillary data in AUD_ANC is started by enabling interrupt 7. An interrupt 7, i.e. AUD_ITR [7], is generated when 32 bits have been written into AUD_ANC, i.e. when it is full. When AUD_ANC [31:24] is read, AUD_ADA is cleared and the ancillary data buffer is reinitialized.
AUD_BBE
7 0x70 Address: Access: Reset state:
Bit Buffer Enable

0 AUD_BBE
AudioBaseAddress + 0x70 Read/write undefined
Description
This bit must be set in order for audio bit buffer data to be processed by the Audio Decoder. When reset, data may be input through the microcontroller interface via the AUD_CDI register, bypassing the audio bit buffer. 0 Bit buffer disabled, MCU input enabled 1 Bit buffer enabled, MCU input disabled
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4 - Audio MPEG (AUD) registers AUD_CDI

0x18
CO
D I F N
7
Compressed Data Input

0 AUD_CDI[7:0]
L A I T N E
STi5500
AudioBaseAddress + 0x18 Write only Undefined
Description
When AUD_BBE is reset, audio compressed data may be input via the microcontroller by writing the compressed data to this register. Note that as audio data enters the audio decoder directly, the system parser and bit buffer are bypassed. Thus, only elementary or PCM audio data may be entered, and these modes must be correctly programmed in the AUD_ISS register.
AUD_CRC
7 0x2A Address: Access: Reset state:
CRC Error Concealment Mode

1 0 AUD_CRC[1:0]
AudioBaseAddress + 0x2A Read/Write Undefined
Description This register defines the action which will be taken upon detection of a CRC error in an input frame. 00 Disable CRC detection and error concealment 01 Mute on detection of CRC error 10 Illegal 11 Skip invalid frame
AUD_DEM
De-Emphasis Mode
1 0 AUD_DEM[1:0]
AudioBaseAddress + 0x46 Read only Undefined
Description
This register is set with the value of the emphasis field of the frame currently being decoded. If enabled, an interrupt 10, i.e. AUD_ITR [10], is generated on a change in the value. The register is updated and the interrupt generated when the corresponding frame is at the PCM output stage. 00 None 01 50/15 s 10 Reserved. 11 ITU-T J.17
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STi5500 AUD_DIF
0x6F
CO
D I F N
7
PCM Output Justification

0 AUD_DIF
L A I T N E
AudioBaseAddress + 0x6F Read/Write Undefined
Description
DIF stands for Data In Front. This bit selects whether the PCM output data is right or left justified with respect to the 32clock frame when in 18-bit mode (i.e. when AUD_P18 = 1). This bit is has no significance when in 16-bit mode, i.e. when AUD_P18 = 0. 0 18-bit PCM data is right justified, i.e. it occupies the last 18 cycles of each 32-cycle frame. 1 18-bit PCM data is left justified, i.e. it occupies the first 18 cycles of each 32-cycle frame when AUD_FOR = 1, or the next 18 when AUD_FOR = 0.
AUD_DIV
7 0x6E Address: Access: Reset state:
PCM Clock Divider

5 AUD_DIV[5:0] 0
AudioBaseAddress + 0x6E Read/Write Undefined
Description The number loaded into this register, in the range 0 to 63, defines the ratio of the frequency of the PCM bit clock, SCLK, to that of PCMCLK, according to the relationship:
fPCMCLK fSCLK = --------------------------------------------2 ( AUD_DIV + 1 )

For example, AUD_DIV is loaded with 0, the frequency of SCLK is one half of the frequency of PCMCLK, while if AUD_DIV is loaded with 63, the frequency of SCLK is one 128th of the frequency of PCMCLK. The value of AUD_DIV = 16 is reserved. If this number is loaded, the divider is bypassed and the frequency of SCLK is equal to the frequency of PCMCLK. AUD_DIV must be set up before the output of SCLK starts. This can be done by first disabling PCM outputs by deasserting the AUD_MUT and AUD_PLY commands, and then writing to the AUD_DIV register. Once the register is set up, the AUD_MUT and/or AUD_PLY commands can be asserted. AUD_DIV cannot be changed on the fly.
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4 - Audio MPEG (AUD) registers AUD_ESC

0x0A 0x0B
0x0C 0x0D 0x0E 0x0F
CO
D I F N
7
Elementary Stream Clock Reference

0 AUD_ESC[7:0] AUD_ESC[15:8] AUD_ESC[23:16] AUD_ESC[31:24] AUD_ESC[33:32] AUD_ESCX[7:0]
L A I T N E
STi5500
AudioBaseAddress + 0x0A to 0x0F Read only undefined
Description The register contains the value of the last elementary stream clock reference (ESCR) which was detected in the audio bitstream. When a new ESCR is detected an interruption is signalled. See register description AUD_INT, AUD_IMS. AUD_ESC[33] indicates the presence of the extension field AUD_ESCX[7:0] for 27 MHz system clocks.
AUD_EXT
7 0x1F Address: Access: Reset state:
Decoding Mode Extension

1 0 AUD_EXT[1:0]
AudioBaseAddress + 0x1F Read/write undefined
Description This register enables dual-mode decoding and an improved mute. 00 Normal decoding 01 Decode dual-mode bitstream, where only right channel is decoded and is output on both output channels 10 Decode dual-mode bitstream, where only left channel is decoded and is output on both output channels 11 Perform smooth mute by clearing 32 input samples.
AUD_FFL
7 0x14 0x15 Address: Access: Reset state:
Free-Format Frame Length

0 AUD_FFL[7:0] AUD_FFL[15:8]
AudioBaseAddress + 0x14 to 0x15 Read/write undefined
Description When free-format decoding is used (bitrate_index = 0), the frame length, if known, can be loaded into this register, in units of bits. (In free-format, the frame length cannot be determined from bitstream parameters).
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The length loaded into AUD_FFL is used in the internal synchronization algorithm. If the frame length is not known, AUD_FFL must be loaded with zero.
AUD_FOR
CO
D I F N
7
L A I T N E
PCM Output Format

0 AUD_FOR
Description This bit is used to select the I2S-compatible PCM output format when in 18-bit left-justified mode (i.e. when AUD_P18 = 1 and AUD_DIF = 1). In this mode the most-significant bit of the PCM data is output one cycle later than the change of LRCK. AUD_FOR has no significance when AUD_P18 =0. 0 I2S-compatible PCM output 1 Standard format (most-significant bit of data coincident with AOLRCK)
AUD_HDR
7 0x5E 0x5F 0x60 0x61 Address: Access: Reset state:
Frame Header
0 AUD_HDR[7:0] AUD_HDR[15:8] AUD_HDR[23:16] AUD_HDR[31:24]
AudioBaseAddress + 0x5E to 0x61 Read only undefined
Description
This 32-bit register contains the header of the frame currently being decoded. This register is updated after interrupt 1 is enabled. An interrupt 1 is generated, i.e. AUD_ITR[1], when a valid header has been received. The contents are retained until AUD_HDR[31:24] is read.
AUD_IDE
Audio Stream ID Enable

0 AUD_IDE
Description
If this bit is reset, then the contents of AUD_SID are ignored. If it is set, then the register AUD_SID is taken into account. As they have opposite meanings, This bit and bit PES_CF1.IAI must always be forced to opposite values at the same time (beginning with PES_CF1.IAI).
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0 1 Ignore AUD_SID Use AUD_SID
AUD_IFT
0x52
CO
D I F N
7
L A I T N E
AUD_IFT[7:0]
STi5500
Input FIFO Threshold

0
Description
This value loaded into this register defines the input FIFO level at which an interrupt 12 can be generated, i.e. AUD_ITR[12]. The level is defined as a byte address, in the range 0 to 255. An interrupt can be generated each time the FIFO level is equal to AUD_IFT, regardless of whether it was approached from above or below. In addition, an interrupt 13, i.e AUD_ITR[13], is generated whenever the FIFO is full. Those interrupts AUD_ITR[13:12] are useful only when AUD_BBE is reset (i.e. Audio Bit Buffer disabled and data input directly into audio decoder through AUD_CDI register followed by this input FIFO. Note that AUDREQ refers to the input of data into the Bit Buffer (AUD_BBE is set). Thus controlling the direct input of audio data without Bit-Buffer, using AUD_ITR[13:12] is very constrained.
AUD_IMS
7 0x5C Address: Access: Reset state:
Audio Interrupt Extension Mask

1 0 AUD_IMS[1:0]
AudioBaseAddress + 0x5C Read/write undefined
Description
Interrupt status bits indicating new value for ESCR field received in MPEG-2 PES streams. Setting AUD_IMS[0] must always be tied low. Setting AUD_IMS[1] enables ESCR interrupt.
AUD_ISS
Input Stream Selection

2 AUD_ISS[2:0] 0
Description This register defines the type of input bitstream expected by the audio decoder. 000 MPEG audio elementary stream 001 MPEG-1 packet stream 010 reserved 011 PCM data. In this mode, the audio decoder is bypassed and data is sent directly to the audio DAC interface. This bit must be set in CD-DA mode.
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100 MPEG-2 PES Streams 101 Automatic detection MPEG-1/MPEG-2 packet streams
AUD_ITM
0x1C 0x1D Address: Access: Reset state:
CO
D I F N
7 6
L A I T N E
AUD_ITM[7:0]
Interrupt Mask Register

0
AUD_ITM[14:8]
AudioBaseAddress + 0x1C to 0x1D Read/write 0. Also cleared on restart.
Description
A one in any bit position of this register will enable the corresponding bit of the AUD_ITR register. In addition, setting certain bits of this register have additional actions, as specified below: Setting AUD_ITM[7] enables the reading of ancillary data into AUD_ANC. Setting AUD_ITM[2] enables the updating of the AUD_PTS register. Setting AUD_ITM[1] enables the updating of the AUD_HDR register. Setting AUD_ITM[0] enables the updating of the AUD_SYS register.
AUD_ITR
7 0x1A 0x1B Address: Access: Reset state:
Interrupt Status Request Register

6 AUD_ITR[7:0] AUD_ITR[14:8] 0
AudioBaseAddress + 0x1A to 0x1B Read only 0. Also cleared on restart.
Description An interrupt is signalled whenever one of the bits of AUD_ITR becomes set. This can only occur if the corresponding bit is set in the AUD_ITM register. The AUD_ITR register is cleared on reset (assertion of RESET pin or setting of AUD_RES register), or restart (setting the AUD_RST register). Also the most significant byte, and bit 5 of the least significant byte of AUD_ITR can be independently cleared by reading. Bits 0-2 and 7 are cleared by a different method, as indicated in the notes in the table below.
Bit 14 13 12 11 10 9 8 7 Condition Signalled First bit of new frame at PCM output Input FIFO full Input FIFO level = FIFO_THRES not used De-emphasis changed Sampling frequency changed PCM output buffer underflow Ancillary data register full AUD_ANC[31:24] must be read in order to clear bit AUD_ITR[7] and to reinitialize the ancillary data buffer. Note
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Bit 6 5 4 3 2 1 0 Condition Signalled not used
CO
not used not used
CRC error detected
D I F N
L A I T N E
STi5500
Note
Valid PTS registered Valid header registered Change in synchronization status
AUD_PTS[32] must be read in order to clear bit AUD_ITR[2] and to reinitialize the AUD_PTS register. AUD_HDR[31:24] must be read in order to clear bit AUD_ITR[1] and to reinitialize the AUD_HDR register. AUD_SYS must be read in order to clear bit AUD_ITR[0] and to reinitialize the AUD_SYS register.
AUD_ITS
7 0x5B Address: Access: Reset state:
Audio Interrupt Extension

1 0 AUD_ITS[1:0]
AudioBaseAddress + 0x5B Read/write undefined
Description Interrupt status bits indicating new values for ESCR and DTS fields received in MPEG-2 PES streams.
AUD_LCA
Left Channel Attenuation

5 AUD_LCA[5:0] 0
AudioBaseAddress + 0x1E Read/write undefined
Description
This register defines the left channel attenuation in steps of 2dB. The minimum attenuation is 0 dB, the maximum is 2 x 63 = 126 dB.
AUD_LCK
Sync Words Until Lock

1 0 AUD_LCK[1:0]
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Description This register defines how many valid synchronization words after the initial one must be found before locking audio frame synchronization. When AUD_SYE is set to its default value, the audio decoder assumes that AUD_LCK is set to the value 3. Synchronization error concealment is still enabled when AUD_LCK has the value zero.
CO
D I F N
7
L A I T N E
AUD_LRP
LRCK Polarity
0 AUD_LRP
AudioBaseAddress + 0x11 Read/write 0 after assertion of RESET pin only
Description
This bit is used to define the polarity of the output signal LRCK. 0 Left channel when LRCK = 1 1 Left channel when LRCK = 0
AUD_MUT
Mute
0 AUD_MUT
Description
See audio processor description for more details.
AUD_ORD
PCM Output Bit Order

0 AUD_ORD
Description This bit determines the order of PCM data output when in 16-bit mode (i.e. when AUD_P18 = 0). It has no significance when AUD_P18 = 1, when data is always output most-significant bit first. 0 Most-significant bit output first 1 Least-significant bit output first
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4 - Audio MPEG (AUD) registers AUD_P18

0x16
CO
D I F N
7
PCM Output Precision
L A I T N E
STi5500
0 AUD_P18
Description
This bit defines the PCM output precision. 0 16-bit PCM data output 1 18-bit PCM data output
AUD_PLY
Play
0 AUD_PLY
AudioBaseAddress + 0x2E Read/write 0 after assertion of RESET pin only
Description See audio processor section for more details.
AUD_PTS
7 0x62 0x63 0x64 0x65 0x66 Address: Access: Reset state:
Presentation Time Stamp

0 AUD_PTS[7:0] AUD_PTS[15:8] AUD_PTS[23:16] AUD_PTS[31:24] AUD_PTS[32]
AudioBaseAddress + 0x62 to 0x66 Read only undefined
Description
This 33-bit register contains the PTS associated with the frame currently being decoded. This register is updated after interrupt 2 is enabled. An interrupt 2 is generated, i.e. AUD_ITR[2], when a valid PTS has been received. The contents are retained until AUD_PTS[32] is read.
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STi5500 AUD_RCA
0x20
CO
D I F N
7
Right Channel Attenuation

5 0 AUD_RCA[5:0]
L A I T N E
Description
This register defines the right channel attenuation in steps of 2 dB. The minimum attenuation is 0 dB, the maximum is 2 x 63 = 126 dB.
AUD_RES
Audio Decoder Software Reset

0 AUD_RES
AudioBaseAddress + 0x40 Read/write 0 (command)
Description Writing a 0 or 1 to this bit has an equivalent function to audio only hardware reset, except that the following registers are not cleared: AUD_SCP AUD_MUT AUD_PLY This bit is reset automatically after being set.
AUD_RST
Restart
0 AUD_RST
AudioBaseAddress + 0x42 Read/write (command)
Description
When this bit is set, all data buffers are flushed, and then the AUD_RST bit is automatically reset. In addition the AUD_ITR, AUD_ITM, AUD_IMS and AUD_IMT registers are cleared.
AUD_SCM
7 0x25 Address: Access:
Sync Confirmation Mode

0 AUD_SCM
AudioBaseAddress + 0x25 Read/write
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Reset state: undefined
Description This bit selects one of two options in the packet synchronization algorithm. 0 After the first valid packet start code and stream ID are found, the packet length is used to locate the next start code and stream ID before synchronization is confirmed and audio decoding starts. 1 Synchronization is confirmed when the first valid packet start code and stream ID are found.
CO
D I F N
7
L A I T N E
STi5500
AUD_SCP
SCLK Polarity
0 AUD_SCP
Description
This bit defines the polarity of the PCM bit clock output BCK. 0 The LRCK and PCMDATA outputs change on the falling edge of SCLK. The external DAC will sample LRCLK and PCMDATA on the rising edge of SCLK. 1 The LRCK and PCMDATA outputs change on the rising edge of SCLK. The external DAC will sample LRCK and PCMDATA on the falling edge of SCLK.
AUD_SEM
7 0x2C Address: Access: Reset state:
Sync Error Concealment Mode

1 0 AUD_SEM[1:0]
AudioBaseAddress + 0x2C Read/write undefined
Description This register defines the action which will be taken upon detection of a synchronization error. 00 Ignore error 01 Mute on detection of synchronization error 10 Invalid. 11 Skip invalid frame
AUD_SFR
Sampling Frequency
1 0 AUD_SFR[1:0]
AudioBaseAddress + 0x44 Read only 00
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Description This register is loaded with the sampling frequency code extracted from the bit stream. The register is updated synchronously with the first sample out on the PCM data. If enabled, an interrupt 9 is generated, i.e. AUD_ITR[9], at this time if the sampling frequency value has changed. 00 44.1 kHz 01 48 kHz 10 32 kHz 11 reserved
CO
D I F N
7
L A I T N E
AUD_SID
Audio Stream ID
4 AUD_SID[4:0] 0
Description The value stored in this register is only taken into account if AUD_IDE is set. This register specifies the number (between 0 and 31) of the audio stream which is to be decoded. The stream number is defined in the field stream_id of the packet header. All other packets will be discarded. If AUD_IDE is reset, then all audio packets are decoded. Note that these bits are duplicated in register PES_CF1.AUD_ID[4:0] and should be set simultaneously.
AUD_SKP
Skip Next Frame

0 AUD_SKP
AudioBaseAddress + 0x32 Read/write 0 (command)
Description
When this bit is set, the next audio frame is skipped, and then the AUD_SKP bit is automatically reset.
AUD_SYE
Sync Word Extension

0 AUD_SYE[7:0]
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Description This register defines an extension to the frame synchronization word which can be used to increase the reliability of synchronization when the layer number, bit rate or sampling frequency are known. The three fields are defined in the following tables. Programming of this register is mandatory.
CO
D I F N
Bits 7,6 11 10 00
L A I T N E
STi5500
Mode Layer I Layer II This field not used Layer I free format 32 kbit/s 64 kbits 96 kbit/s 128 kbit/s 160 kbit/s 192 kbit/s 224 kbit/s 256 kbit/s 288 kbit/s 320 kbit/s 352 kbit/s 384 kbit/s 416 kbit/s 448 kbit/s This field not used Layer II free format 32 kbit/s 48 kbit/s 56 kbit/s 64 kbit/s 80 kbit/s 96 kbit/s 112 kbit/s 128 kbit/s 160 kbit/s 192 kbit/s 224 kbit/s 256 kbit/s 320 kbit/s 384 kbit/s This field not used Mode 44.1 kHz 48 kHz 32 kHz This field not used
Bits 5-2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits 1,0 00 01 10 11
Examples:1 Layer II, 48 kHz sampling frequency, variable bit rate: AUD_SYE = 101111012 2 Parameters unknown: AUD_SYE = 001111112
AUD_SYN
Packet Sync Mode

1 0 AUD_SYN[1:0]
AudioBaseAddress + 0x23 Read/write
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Reset state: undefined
Description This register defines the packet synchronization mode. 00 Synchronize only on 24-bit packet_start_code_prefix . (Multiplexed audio/video bitstream). 01 Synchronize both on 24-bit packet_start_code_prefix and first 3 bits of stream_id. (Multiplexed audio bitstream). 10 Synchronize both on 24-bit packet_start_code_prefix and all 8 bits of stream_id. (Audio bitstream with unique id).
CO
D I F N
7
L A I T N E
AUD_SYS
Synchronization Status
1 0 AUD_SYS[1:0]
AudioBaseAddress + 0x26 Read only undefined
Description
This register is loaded with the synchronization status on every synchronization cycle. This status values are: 00 Unlocked 01 Attempting to recover lost synchronization 11 Locked If the status changes an interrupt 0 is generated, i.e. AUD_ITR[2]. The status must then be read and the interrupt cleared by reading AUD_SYS.
AUD_VER
7 0x2D 1
Revision
1 AUD_REV[6:0] 0
AudioBaseAddress + 0x2D Read only static
Description
This register holds the chip version number "x.y" where x is represented by bits 6-4 and y by bits 3-0. Bit 7 is always 1.
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5 - Block move DMA (BMDMA) registers
BMDMADestAddress
0x00 Address: Access:
L A I T Block move E DMA (BMDMA) registers N D I F N O C

Block move DMA destination address
DestAddress
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
STi5500
BMBaseAddress + 0x00 Write only
Description
The address of the base of the block move destination area.
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STi5500
CacheControl
7
L A I T Cache control registers N E D I F N CO

Cache control 0
5 6 4
6 - Cache control registers
0x000
Cacheable 7
Cacheable 6
Cacheable 5
Cacheable 4
Cacheable 3
Cacheable 2
Cacheable 1
Cacheable 0
CacheBaseAddress + 0x000 Read/write 0
Description This register defines the cacheability of parts of region 1, i.e. whether cache will be used when accessing addresses in the range 0xC0000000 to 0xC007FFFF and 0xC0200000 to 0xC027FFFF. Each bit in the register defines whether two 64 Kbyte blocks of addresses will be cached, as shown in Table 6.1. If the appropriate bit is set then the blocks will be cached; otherwise they will not be cached.
Lower half of SDRAM Bit Block start Cacheable0 Cacheable1 Cacheable2 Cacheable3 Cacheable4 Cacheable5 Cacheable6 Cacheable7 0xC0000000 0xC0010000 0xC0020000 0xC0030000 0xC0040000 0xC0050000 0xC0060000 0xC0070000 Block end 0xC000FFFF 0xC001FFFF 0xC002FFFF 0xC003FFFF 0xC004FFFF 0xC005FFFF 0xC006FFFF 0xC007FFFF Block start 0xC0200000 0xC0210000 0xC0220000 0xC0230000 0xC0240000 0xC0250000 0xC0260000 0xC0270000 Block end 0xC020FFFF 0xC021FFFF 0xC022FFFF 0xC023FFFF 0xC024FFFF 0xC025FFFF 0xC026FFFF 0xC027FFFF Upper half of SDRAM
Table 6.1 Blocks of memory which may be programmed to be data cacheable
CacheControlLock
7 6
Cache control lock

5 4 3 2 1 0
Lock
CacheBaseAddress + 0x500 Read/write 0
Description
The cache configuration can be locked by writing a 1 to the CacheControlLock register bit. The lock makes CacheControl, SelectCache and CacheControlLock not writable. Reset of this flag is only performed by a hardware reset. This bit should be set to 1 after all the cache configuration registers have been written.
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6 - Cache control registers FlushDCache

7
0x400
CO
D I F N
6
Flush the data cache

5 4
L A I T N E
STi5500
Flush
CacheBaseAddress + 0x400 Write only Undefined
Description
Flushing the cache means forcing a write-back to memory of every dirty line in the cache. A dirty line is a line of cache that has been written to since it was loaded or last written back. To flush the data cache, set the FlushDCache register to 1; It is automatically reset to 0 on completion of the flushing. Any memory accesses that are cacheable which were started before the flush of the data cache is complete, will be blocked until it is completed.
InvalidateDCache
7 6
Invalidate the data cache

5 4 3 2 1 0
Invalidate
Description Invalidating a cache marks every line as not containing valid data. This register is automatically reset to 0 on completion of invalidation. Any memory accesses that are cacheable which are started before the data cache invalidation is complete will be blocked until it is completed.
InvalidateICache
7 6
Invalidate the instruction cache

5 4 3 2 1 0
Invalidate
Description Invalidating a cache marks every line as not containing valid data. This register is automatically reset to 0 on completion of the task. Any instruction fetches that are cacheable and were started before completion of the invalidation of the instruction cache, will be blocked until it is completed. If the instruction cache is enabled, the cache contents will be random and must be invalidated by setting the invalidate bit first before enabling the cache.
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STi5500 SelectCache
7
0x100
CO
D I F N
6
Select cache
5
L A I T N E
4
6 - Cache control registers
EnableICache
DCacheNotSRAM
CacheBaseAddress + 0x100 Write only 0
Description
It is possible to select either data cache or an extra 2 Kbyte of on-chip SRAM. This is done by writing 1 to the DCacheNotSRAM bit. The default is to enable the extra on-chip SRAM. Do not access locations 0x80000800 to 0x80000FFF when using the data cache. The instruction cache is enabled by setting EnableICache to 1. It is not recommended to change these selections other than during booting of the application. The appropriate cache invalidate bit should be set before enabling either cache. Data cache must be flushed before disabling. Bit 0 Bit field DCacheNotSRAM Function Select the configuration for data cache memory. 0 SRAM (default). 1 Data cache. Enable the instruction cache. 0 Disabled. 1 Enabled.
EnableICache
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7 - Configuration and control (CFG) registers
CFG_CCF
0x01
L A I T Configuration and control (CFG) registers N E D I F N O C

Chip Configuration
6 5 PBO 7 4 3 2 EAI EOU EC3 EC2 ECK
STi5500
0 EVI
EDI
Address: Access: Reset state: Synchronization:
VideoBaseAddress + 0x01 Read/write 0 Edge triggered
Description
Field EAI EOU PBO EC3 EC2 ECK EDI Bit 7 6 5 4 3 2 1 Description
Enable audio interface. When this bit is reset the audio interface is put into its high impedance state and the internal PCMCLK is disabled. This bit must be set for normal operation and for reduced power mode (if the display interface is used). It is reset in low power mode. Enable overflow/underflow errors. When this bit is reset overflow and underflow errors are not treated internally. This bit must be set for normal operation. Prevent bit buffer overflow. When this bit is set, bit buffer overflow (and thus the loss of data) is prevented by disabling the transfer of data from the compressed data FIFO to the bit buffer whenever the bit buffer level reaches the threshold defined in the VID_VBT or VID_ABT register. Enable clock 3. When this bit is reset, the internal clock 3 is disabled. This bit must be set for normal operation and for reduced power mode. It is reset in low power mode. Enable clock 2. When this bit is reset, the internal clock 2 is disabled. This bit must be set for normal operation, and reset in reduced and low power modes. Enable clocks. When this bit is reset, all internal clocks are disabled. This bit must be set for normal operation and for reduced power mode. It is reset in low power mode. Enable SDRAM interface. When this bit is reset the SDRAM interface is put into its high impedance state. This bit must be set for normal operation and for reduced power mode. It is reset in low power mode. Enable video interface. When this bit is reset the video interface is put into its high impedance state and the internal PIXCLK disabled. This bit must be set for normal operation and for reduced power mode (if the display interface is used). It is reset in low power mode.
EVI
CFG_CDR
7 0x44 Address: Access: Reset state: Synchronization:
Compressed Data Input

0 CFG_CDR[7:0]
VideoBaseAddress + 0x44 Write only Undefined None
Description
This register is a compressed data input register. It is used to input compressed data using a different path from the usual DMA path. Depending on the value of CFG_GCF.CDR[1:0] the data stored in this register will enter either the audio, video or sub-picture compressed data FIFO.
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STi5500 CFG_DRC
0x38
CO
D I F N
7 6
DRAM Configuration
5 MRS
L A I T N E
4
7 - Configuration and control (CFG) registers
3 P0
2 P1
1 ERQ
0 SDR
VideoBaseAddress + 0x38 Read/write 0 None
Description
Field MRS Bit 5 4 P[1:0] 3:2 Description
Mode Register Set. When this bit is set the special power-on-reset sequence and mode register programming is carried out. When this bit is reset the procedure is inhibited.
Reserved
Clk3 phase to MemClk. The following procedure has to be executed to make sure the SDRAM interface is properly initialized: P[1:0] = 0, write four 32-bit words to SDRAM, read back the four words from SDRAM, if they do not read back correctly, increment the value of P[1:0] until the read is correct. Enable Processes Requests. This bit when reset disables all processes requests to the local memory controller. This bit has to be set for normal operation. Synchronous DRAM mode. This bit must always be written as 1.
ERQ SDR
1 0
CFG_GCF
7 0x3A Address: Access: Reset state: Synchronization:
General Configuration
6 A3Rq 5 A3DI 4 CDR 3 2 SCK 1 A3M 0 ACS
VideoBaseAddress + 0x3A Read/write 0 None
Description
Field A3Rq A3Dl Bits 6 5 Description
External AC3 request polarity. External polarity is reversed if set to 1. External AC3 data strobe mode. This bit, when set, allows MSB data being strobed on the second rising edge of SCLK following a transition of LRCLK. Otherwise, the first rising edge is used.
Compressed data register: 00 Automatic strobe generation when writing to CD FIFOs 10 Sub-picture 01 Audio 11 Video When one internal strobe is chosen, it has to be driven by writing to register CFG_CDR.
CDR[1:0]
4:3
SCK A3M ACS
2 1 0
Audio strobe clock select. This bit, when set, selects clk2 as serial strobe period. Otherwise, clk3 is selected. AC3 / MPEG audio decoder Select. This bit, when set, configures the audio pins to use the external AC3 audio decoder. When reset, the configuration is done for the internal MPEG audio decoder.
This bit has to be reset.
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7 - Configuration and control (CFG) registers CFG_MCF

0x00
CO
D I F N
7 6
Memory Refresh Interval

0 RFI[6:0]
L A I T N E
STi5500
VideoBaseAddress + 0x00 Read/write 0 none
Description This register defines the SDRAM refresh interval in units of 32 SDRAM clock periods. For example if 2048 rows must be refreshed every 32 ms, with an SDRAM clock of 100 MHz, the following value must be stored in MCF.RFI[6:0]:
(32 x 10-3/2048) x (100 x 106/32) = 48 If the register is set to 0 then refresh is disabled.
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STi5500
CKG_AUX
1st cycle 2nd cycle 3rd cycle 4th cycle Address: Access: Reset state:
L A I T Clock generator (CKG) registers N E D I F N O C

7 6 5 4 3 ENA DV2 PR[9:3] PR[2:0] Q[6:0]
8 - Clock generator (CKG) registers
Clock Generator Auxiliary Clock Divider

0 P0[3:0]
Q[10:7]
VideoBaseAddress + 0x37 Serial read/write 0
Description This register controls the fractional divider for the Auxiliary clock. Writing to the highest address (DF) latches the new configuration. The bit significance is given in the CKG_CFG register definition below.
Field Cycle Bits Description
ENA
Enable. Controls whether or not the fractional divider is enabled or disabled for low power.
0 1 fractional divider is disabled fractional divider is enabled
DV2 P0[3:0] PR[9:3] PR[2:0] Q[10:7] Q[6:0]
1 1 2 3 3 4
4 3:0 6:0 6:4 3:0 6:0
Divide-by-2. The output of the fractional divider is divided by two. 0 not divided by 2 1 divided by 2. P0. Defines the value of P0 as described in the STi5500 datasheet. Pr. Contains the value of Pr as described in the STi5500 datasheet. Q. Contains the value of Q as described in the STi5500 datasheet. These bits should be programmed to Q (i.e. ones compliment).
CKG_CFG
Clock Generator Configuration

6 CKG_CFG[6:0] 0
VideoBaseAddress + 0x31 Read/write 0
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Description Controls the input/output modes for MEMCLK and PCMCLK and signal selection for MPEG decoders clocks and test modes. After reset, clock pin PCMCLK is in input mode and clock MEMCLK is in output mode.
Field
CO
Bit
D I F N
L A I T N E
STi5500
Description
Configuration 6. Controls the input/output state of the MEMCLK pin.
CFG[6]
0 the MEMCLK pin is an output from MEMCLKo fractional divider (see bits CKG_MEM.ENA/ DV2) 1 the MEMCLK can be input externally (bypassing PLL) using the A_C_REQ pin.
CFG[5] CFG[4:2] CFG[1]
5 3 1
Configuration 5. Controls the input/output state of the PCMCLK pin. 0 the PCMCLK pin is an input 1 the PCMCLK pin is an output from PCMCLKo fractional divider (see bits CKG_PCM.ENA/DV2)
Reserved Configuration 1. Selects the Link Iinterface clock. 0Select the external link clock 1Select the the internal divided PLL (see CKG_VID.ENA and CKG_VID.DV2 ). Lock bit. This bit is read only. When set to 1, it indicates that the PLL is locked (to be used in PLL init sequence)
CFG[0]
CKG_LNK
7 1st cycle 2nd cycle 3rd cycle 4th cycle Address: Access: Reset state:
Clock Generator Link Interface Clock Divider

6 5 ENA 4 DV2 PR[9:3] PR[2:0] Q[6:0] Q[10:7] 3 P0[3:0] 0
Description
This register controls the fractional divider for the Link Interface clock. Writing to the highest address (DF) latches the new configuration. The bits have the significance given in the CKG_CFG register definition. Field Cycle Bits Description
ENA
Enable. Controls whether or not the fractional divider is enabled or disabled for low power. 0 fractional divider is disabled 1 fractional divider is enabled Divide-by-2. The output of the fractional divider is divided by two.
0 1 not divided by 2 divided by 2.
DV2 P0[3:0] PR[9:3] PR[2:0]
1 1 2 3
4 3:0 6:0 6:4
P0. Defines the value of P0 as described in the STi5500 datasheet. Pr. Contains the value of Pr as described in the STi5500 datasheet.
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STi5500
Field Q[10:7] Q[6:0] Cycle 3 4 Bits 3:0 6:0
CKG_MCK
1st cycle 2nd cycle 3rd cycle 4th cycle Address: Access: Reset state:
CO
D I F N
7 6
L A I T N E
5 ENA 4 DV2

Description
Q. Contains the value of Q as described in the STi5500 datasheet. These bits should be programmed to Q (i.e. ones compliment).
Clock Generator SdramClock Divider

3 P0[3:0] PR[9:3] PR[2:0] Q[6:0] Q[10:7] 0
Description This register controls the fractional divider for the Sdram clock. Writing to the highest address (DF) latches the new configuration. The bits have the significance given in the CKG_CFG register definition.
ENA
Enable. Controls whether or not the fractional divider is enabled or disabled for low power. 0 fractional divider is disabled 1 fractional divider is enabled Divide-by-2. The output of the fractional divider is divided by two. 0 not divided by 2 1 divided by 2. P0. Defines the value of P0 as described in the STi5500 datasheet. Pr. Contains the value of Pr as described in the STi5500 datasheet. Q. Contains the value of Q as described in the STi5500 datasheet. These bits should be programmed to Q (i.e. ones compliment).
DV2 P0[3:0] PR[9:3] PR[2:0] Q[10:7] Q[6:0]
1 1 2 3 3 4
4 3:0 6:0 6:4 3:0 6:0
CKG_PCM
7 1st cycle 2nd cycle 3rd cycle 4th cycle Address: Access: Reset state:
Clock Generator PCM Clock Divider

6 5 ENA 4 DV2 PR[9:3] PR[2:0] Q[6:0] Q[10:7] 3 P0[3:0] 0
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Description This register controls the fractional divider for the PCM clock. Writing to the highest address (DF) latches the new configuration. The bits have the significance given in the CKG_CFG register definition.
Field
CO
Cycle
D I F N
Bits 1 5 1 1 2 3 3 4 4 3:0 6:0 6:4 3:0 6:0
L A I T N E
0 1
STi5500
Description
ENA
fractional divider is disabled fractional divider is enabled
DV2 P0[3:0] PR[9:3] PR[2:0] Q[10:7] Q[6:0]
CKG_PLL
7 0x30 Address: Access: Reset state: PD
Clock Generator PLL Parameters

6 REF[1:0] 5 4 N 3 M[3:0] 0
VideoBaseAddress + 0x30 Read/write 0
Description
Controls the reference frequency input, pre-divider and multiplication factor of the PLL. The bits have the following significance: Field PD Bits 7 Description
Power-Down Mode. When set, the reference input to the PLL is reset. Clock Generator Reference. These bits control the reference frequency input multiplexer to the clock generators PLL. 00 Selects PIXCLK 01 Selects PCMCLK 10 PLL power down mode 11 Selects External Link Clock In Divide-by-N+1. When set, the reference input to the PLL is divided by two. This bit corresponds to N in the STi5500 data sheet. PLL Multiplication Factor, M+7. These bits control the reference frequency input to the PLL of the clock generator. The actual multiplication factor is M + 7. This field corresponds to M in the STi5500 data sheet formulae.
REF[1:0]
6:5
N M[3:0]
4 3:0
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STi5500 CKG_PXC
1st cycle
2nd cycle 3rd cycle 4th cycle
CO
D I F N
7 6
Clock Generator Pixel Clock Divider

5 4 3 P0[3:0] PR[9:3] PR[2:0] Q[6:0] Q[10:7] 0 ENA DV2
L A I T N E
Description This register controls the fractional divider for the Pixel clock. Writing to the highest address (DF) latches the new configuration. The bits have the significance given in the CKG_CFG register definition.
ENA
0 1 fractional divider is disabled fractional divider is enabled
DV2 P0[3:0] PR[9:3] PR[2:0] Q[10:7] Q[6:0]
1 1 2 3 3 4
4 3:0 6:0 6:4 3:0 6:0
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9 - Digital encoder registers
CCCF1
0x27 0x28 Address: Access:
L A I T Digital encoder registers N E D I F N CO

7 6 5 4 opc11 opc12 c117 c127 c116 c126 c115 c125 DENCBaseAddress + 0x27 and 0x28 Read / Write
STi5500
Closed caption characters/extended data for field 1

3 c114 c124 2 c113 c123 1 c112 c122 0 c111 c121
Description
opc11 is the odd-parity bit of US-ASCII 7-bit character c11[7:1]. opc12 is the odd-parity bit of US-ASCII 7-bit character c12[7:1]. There is no default value, but closed captions enabling without loading these registers will issue character NULL. cccf1 is never reset.
CCCF2
7 0x29 0x2A Address: Access: opc21 opc22
Closed caption characters/extended data for field 2

6 c217 c227 5 c216 c226 4 c215 c225 3 c214 c224 2 c213 c223 1 c212 c222 0 c211 c221
DENCBaseAddress + 0x29 and 0x2A Read / Write
Description opc21 is the odd-parity bit of US-ASCII 7-bit character c21[7:1]. opc22 is the odd-parity bit of US-ASCII 7-bit character c22[7:1]. There is no default value, but closed captions enabling without loading these registers will issue character NULL. cccf2 is never reset.
CCLIF1
7 0x2B Address: Access: 0
Closed caption/extended data line insertion for field 1

6 0 5 0 4 l1_4 0 3 l1_3 1 2 l1_2 1 1 l1_1 1 0 l1_0 1
DENCBaseAddress + 0x2B Read / Write
Description TV line number where closed caption/extended data is to be encoded in field 1 is programmable through the following register:
525/60 system (525-SMPTE line number convention) Only lines 10 through 22 should be used for closed caption or extended data services (line 1 through 9 contain the vertical sync pulses with equalizing pulses).
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STi5500
l1(4:0):= 00000 no line selected for closed caption encoding l1(4:0):= 000xx do not use these codes .... ....
l1(4:0):= i code line (i+6) (SMPTE) selected for encoding l1(4:0):= 11111 line 37 (SMPTE) selected 625/50 system (625-CCIR/ITU-R line number convention) Only lines 7 through 23 should be used for closed caption or extended data services. l1(4:0):= 00000 no line selected for closed caption encoding ..... l1(4:0):= i code line (i+6) (CCIR) selected for encoding (i>0) ..... l1(4:0):= 11111 line 37 (CCIR) selected DEFAULT value:= 01111 line 21 (525/60, 525-SMPTE line number convention). This value also corresponds to line 21 in 625/50 system, (625-CCIR line number convention)
CO
D I F N
L A I T N E
CCLIF2
7 0x2C Address: Access: 0
Closed caption/extended data line insertion for field 2

6 0 5 0 4 l2_4 0 3 l2_3 1 2 l2_2 1 1 l2_1 1 0 l2_0 1
DENCBaseAddress + 0x2C Read / Write
Description
TV line number where closed caption/extended data is to be encoded in field 2 is programmable through the following register: 525/60 system: (525-SMPTE line number convention) Only lines 273 through 284 should be used for closed caption or extended data services (preceding lines contain the vertical sync pulses with equalizing pulses), although it is possible to program over a wider range. l2(4:0):= 00000 no line selected for closed caption encoding l2(4:0):= 000xx do not use these codes l2(4:0):= i line (269 +i) (SMPTE) selected for encoding .... l2(4:0):= 01111 line 284 (SMPTE) selected for encoding l2(4:0):= 11111 line 289 (SMPTE) If cgms_bit is allowed on lines 20 and 283 (525/60, 525-SMPTE line number convention), closed captions should not be programmed on these lines. 625/50 system: (625-CCIR line number convention) Only lines 319 through 336 should be used for closed caption or extended data services (preceding lines contain the vertical sync pulses with equalizing pulses), although it is possible to program over a wider range. l2(4:0):= 00000 no line selected for closed caption encoding l2(4:0):= i line (318 +i) (CCIR) selected for encoding
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....
l2(4:0):= 10010 line 336 (CCIR) selected for encoding l2(4:0):= 11111 line 349 (CCIR)
The default value is 01111 line 284 (525/60, 525-SMPTE line number convention). This value also corresponds to line 333 in 625/50 system, (625-CCIR line number convention).
CO
D I F N
7 0x1F 0x20 0x21 b5 b13
L A I T N E
6 b6 b14 5 b7 b15 4 b8 b16 3 b1 b9 b17 2 b2 b10 b18 1 b3 b11 b19
STi5500
CGMS_BIT
cgms_bit1 cgms_bit2 cgms_bit3 Address: Access:
CGMS data registers

0 b4 b12 b20
DENCBaseAddress + 0x1F to 0x21 Read / write
Description
20 bits only. See the STi5500 datasheet for a description of CGMS encoding. These registers are never reset. Field Word0A Word0B Word1 Word2 CRC b1:3 b4:6 b7:10 b11:14 b15:20 Not internally computed. Bits Notes
Table 9.1 CGMS field encoding
CHIPID
Address: Access:
DENC identification number

DENCBaseAddress + 0x11 Read only
Description The value of chipid is 0x0.
CONFIGURATION0
7 0x00 std1 6
DENC configuration 0
5 sync2 4 sync1 3 sync0 2 polh 1 polv 0 freerun std0
Address: DENCBaseAddress + 0x00 Access: Read/write Reset state: 100100102, i.e. NTSC M, ODDEVEN and HSYNC slave mode, synchronized with the rising edge of ODDEV flags or VSYNC is active low.
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STi5500
Description
std1-0
The encoding of std1-0 is shown in Table 9.2. The standard on hardware reset is NTSC; any standard modification selects automatically the right parameters for correct subcarrier generation. If bit secam in register configuration7 is set, std1 and std0 bits are not taken into account.
CO
D I F N
std1 0 0 1 1
L A I T N E
std0 0 1 0 1 Standard selected PAL BDGHI PAL N (see bit set-up) NTSC M PAL M
Notes
Default.
Table 9.2 Encoding of std0-1
sync2-0
See the STi5500 datasheet for details. The encoding is shown in Table 9.3. sync2 sync1 sync0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Configuration ODDEV-only based slave mode (frame locked) F based slave mode (frame locked) ODDEV+HSYNC based slave mode (line locked) Default mode. F+H based slave mode (line locked) VSYNC-only based slave mode (frame locked) VSYNC+HSYNC based slave mode (line locked) Master mode Autotest mode (color bar pattern) Table 9.3 Encoding of sync2-0 HSYNC is needed as an input. See sti5500 datasheet. Notes
polh
Synchronized with the active edge of HSYNC selection (when input) or polarity of HSYNC (when output) 0 1 HSYNC is a negative pulse (128 Tckref wide) or falling edge is active. Default. HSYNC is a positive pulse (128 Tckref wide) or rising edge is active.
polv
Synchronized with the active edge of ODDEV/VSYNC selection (when input). 0 1 Falling edge of ODDEV flags start of field1 (odd field) or VSYNC is active low. Rising edge of ODDEV flags start of field1 (odd field) or VSYNC is active high. Default.
freerun
See the STi5500 datasheet. 0 Disabled. Default.
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1 Enabled
NOTE: This bit is taken into account in ODDEV-only, VSYNC-only or F based slave modes and is irrelevant to other synchronization modes.
CONFIGURATION1
7 blkli 0x01 Address: Access: 0
CO
D I F N
6 flt1 1
L A I T N E
5 flt0 0 4 0
STi5500
3 coki 0 2 setup 1 1 cc2 0 0 cc1 0 syncok
DENCBaseAddress + 0x01 Read / Write
Description
blkli
Vertical Blanking Interval selection for active video lines area. See the STi5500 datasheet for details. 0 Partial blanking. Only the following lines inside Vertical Interval are blanked: NTSC-M lines [1..9], [263(half)..272] (525-SMPTE) PAL-M lines [523..6], [260(half)..269] (525-CCIR) other PALlines [623(half)..5], [311..318] (625-CCIR) This mode allows preservation of VBI data embedded within incoming YCrCb, e.g. Teletext (lines [7..22] and [320..335]), Wide Screen signalling (full line 23), Video Programing Service (line16), etc.) 1 Full blanking. All lines inside VBI are blanked: NTSC-M lines [1..19], [263(half)..282] (525-SMPTE) PAL-M lines [523..16], [260(half)..279] (525-CCIR) other PALlines [623(half)..22], [311..335] (625-CCIR) Note: blkli must be set to 0 when closed captions and are to be encoded on the following lines: 525/60before line 20 (SMPTE) or before line 283 (SMPTE) 625/50before line 23 (CCIR) or before line 336 (CCIR)
flt1-0
U/V Chroma filter bandwidth selection. See the STi5500 datasheet for details. flt1 0 0 1 1 flt0 0 1 0 1 3dB bandwidth 1.1MHz 1.3MHz 1.6MHz 1.9MHz Low def NTSC filter. Low def PAL filter. High def. NTSC filter (ATSC compliant) and PAL M/N (ITU-R 624.4 compliant). Default. High def. PAL filter: Rec 624 - 4 for PAL BDG/I compliant. Table 9.4 Encoding of filt0-1 Typical application
syncok
Availability of sync signals (analog and digital) in case of input synchronization loss with no free-run active (i.e. freerun=0). See the STi5500 datasheet for details.
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0 1
No synchro output signals. Default.
Output synchros available on YS, CVBS and, when applicable, HSYNC (if output port), ODDEV (if output port), i.e. same behavior as freerun except that video outputs are blanked in the active portion of the line
coki
Color killer. See the STi5500 datasheet for details. For color suppression on chroma DAC C, see register configuration5 bit bkg_c. 0 1 Color ON. Default. Color suppressed on CVBS output signal (CVBS=YS) but color still present on C output.
CO
D I F N
L A I T N E
setup
Pedestal enable. See the STi5500 datasheet for details. In all cases, the gain factor is adjusted to obtain the required levels for chrominance. 0 1 Blanking level and black level are identical on all lines (ex: Argentinian PAL-N, Japan NTSC-M, PAL-BDGHI). Black level is 7.5 IRE above blanking level on all lines outside VBI (ex: Paraguayan and Uruguayan PAL-N). Default.
cc2, cc1
Closed caption encoding mode. See the STi5500 datasheet for details. cc2 0 0 1 1 cc1 0 1 0 1 Encoding mode No closed caption/extended data encoding. Default. Closed caption/extended data encoding enabled in field 1 (odd) Closed caption/extended data encoding enabled in field 2 (even) Closed caption/extended data encoding enabled in both fields Table 9.5 Encoding of cc2-1
CONFIGURATION2
7 0x02 Address: Access: Reset state: nintrl 6 enrst
5 bursten 4 3 selrst 2 rstosc 1 valrst1 0 valrst0
DENCBaseAddress + 0x02 Read / Write 001000002, i.e. burst enabled, and all other bits zero.
Description
nintrl
Non-interlaced mode select. See the STi5500 datasheet for details. nintrl update is internally taken into account on the start of next frame. 0 1 Interlaced mode (625/50 or 525/60 system). Default. Non-interlaced mode (2x312/50 or 2x262/60 system). Not available in SECAM mode.
enrst
Cyclic update of DDFS phase.
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0 1
No cyclic subcarrier phase reset. Default.
Cyclic subcarrier phase reset depending of valrst1 and valrst0 (see below).
bursten
0 1
Chrominance burst control. Burst is turned off on CVBS, chrominance output is not affected. Burst is enabled. Default.
CO
D I F N
L A I T N E
STi5500
selrst
Selects set of reset values for Direct Digital Frequency Synthesizer. 0 1 Hardware reset values for phase and increment of subcarrier oscillator (see description of registers increment_dfs and phase_dfs for values). Default. Loaded reset values selected (see contents of registers increment_dfs and phase_dfs)
rstosc
Software phase reset of DDFS (Direct Digital Frequency Synthesizer). 0 1 Default. A 0-to-1 transition resets the phase of the subcarrier to either the hard-wired default phase value or the value loaded in register phase_dfs (according to bit selrst).
Bit rstosc is automatically set back to 0 after the oscillator reset has been performed.
valrst
Note: valrst[1:0] is taken into account only if bit enrst is set. valrst1 0 0 1 1 valrst0 0 1 0 1 Selection Automatic reset of the oscillator every line. Default. Automatic reset of the oscillator every 2nd field. Automatic reset of the oscillator every 4th field. Automatic reset of the oscillator every 8th field. Table 9.6 Encoding of valrst Resetting the oscillator means here forcing the value of the phase accumulator to its nominal value to avoid accumulating errors due to the finite number of bits used internally. The value to which the accumulator is reset is either the hardwired default phase value or the value loaded in registers phase_dfs (according to bit selrst), to which a 00, 900, 1800, or 2700 correction is applied according to the field and line on which the reset is performed. Note: If SECAM is performed the oscillator is reset every line.
CONFIGURATION3
7 0x03 Address: Access: Reset state: entrap
6 trap_pal 5 encgms 4 nosd 3 del2 2 del1 1 del0 0
DENCBaseAddress + 0x03 Read / Write 0
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Description
entrap
0 1
Enable trap filter.
Trap filter disabled. Default. Trap filter enabled.
CO
D I F N
L A I T N E
Note: When SECAM is performed trap filter is always enabled (entrap = 1).
trap_pal
Refer to the STi5500 datasheet for details. trap_pal is taken into account only if bit entrap is set. 0 1 To select the NTSC trap filter (centered around 3.58 MHz) (See Fig14a). Default. To select the PAL trap filter (centered around 4.43 MHz) (see Fig.14b).
encgms
CGMS encoding enable. (Refer to the STi5500 datasheet for details). 0 1 Disabled. Default. Enabled.
When encgms is set to 1 Closed-Captions/Extended Data Services should not be programmed on lines 20 and 283. (525/60, SMPTE line number convention).
nosd
Choice of active edge of ckref masterclock that samples incoming YCrCb data. See the STi5500 datasheet. 0 1 ckref rising edge. Default. ckref falling edge.
del(2:0)
Delay on luma path with reference to chroma path. Table 9.7 shows the encoding, where one pixel at 13.5 MHz corresponds to 74.04 ns. Refer to the STi5500 datasheet for details. del2 0 0 0 1 1 del1 1 0 0 1 1 Others del0 0 1 0 1 0 Delay on luma path with reference to chroma path + 2 pixel delay on luma. + 1 pixel delay on luma. + 0 pixel delay on luma. Default. - 1 pixel delay on luma. - 2 pixel delay on luma. + 0 pixel delay on luma. Table 9.7 Encoding of del
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9 - Digital encoder registers CONFIGURATION4

7 0x04
CO
syncin_ad1 syncin_ad0 syncout_ad1 syncout_ad0 DENCBaseAddress + 0x04 Read / Write 0
D I F N
6
5
L A I T N E
STi5500
3 aline
2 ttxdel2
1 ttxdel1
0 ttxdel0
Description
syncin_ad[1:0]
Adjustment of incoming sync signals. See the STi5500 datasheet for details. Used to insure correct interpretation of incoming video samples as Y, Cr or Cb when the encoder is slaved to incoming SYNC signals (including F/H flags stripped off ITU-R656/D1 data). syncin_ad1 0 0 1 1 syncin_ad0 0 1 0 1 Internal delay undergone by incoming SYNC Nominal*. Default. +1 external 27 MHz clock cycle +2 external 27 MHz clock cycles +3 external 27 MHz clock cycles Table 9.8 Encoding of syncin_ad
syncout_ad[1:0]
Adjustment of outgoing sync signals. See the STi5500 datasheet for details. Used to insure correct interpretation of incoming video samples as Y, Cr or Cb when the encoder is master and supplies SYNC signals. syncout_ad1 0 0 1 1 syncout_ad0 0 1 0 1 Delay added to sync signals before they are output Nominal*. Default. +1 external 27 MHz clock cycle +2 external 27 MHz clock cycles +3 external 27 MHz clock cycles Table 9.9 Encoding of syncout_ad
aline
Video active line duration control. See the STi5500 datasheet for details. 0 1 Full digital video line encoding (720 pixels - 1440 clock cycles) Active line duration follows ITU-R/SMPTE analog standard requirements
ttxdel[2:0]
Teletext data latency. The default value is 000. See the STi5500 datasheet for details. The encoder will clock in the first Teletext data sample on the (2 + ttxdel[2:0])th rising edge of the master clock following the rising edge of TTXS (Teletext Synchro signal, supplied by the encoder).
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STi5500 CONFIGURATION5
7 0x05
CO
D I F N
6
5 4 bkys
L A I T N E
bkc
3 bkr
2 bkg
1 bkb
0 dacinv
bkcvbs
DENCBaseAddress + 0x05 Read / Write 001100002, i.e. C and Y DACS at neutral.
Description
bkcvbs
Blanking of DAC CVBS 0 1 DAC N in normal operation. Default. DAC N input code forced to blanking level.
bkys
Blanking of DACY 0 1 DAC G/Y in normal operation. DAC G/Y input code forced to blanking level. Default.
bkc
Blanking of DAC C 0 1 DAC R/C in normal operation. DAC R/C input code forced to neutral level, i.e. no color. Default.
bkr
Blanking of DAC R 0 1 DAC R in normal operation. DAC R input code forced to black level.
bkg
Blanking of DAC G 0 1 DAC G in normal operation. DAC G input code forced to black level.
bkb
Blanking of DAC B 0 1 DAC B/CVBS in normal operation. Default. DAC B/CVBS input code forced to black level.
dacinv
Inverts DAC codes to compensate for an inverting output stage in the application. 0 1 DAC non-inverted inputs. Default. DAC inverted inputs.
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9 - Digital encoder registers CONFIGURATION6

7 0x06
CO
softreset
D I F N
6
5 4 dec_ninc
L A I T N E
free_jump
STi5500
3 cfc1
2 cfc0
1 -
0 maxdyn
jump
DENCBaseAddress + 0x06 Read / Write 000100002
Description
softreset
Software reset 0 1 No reset. Default. Software reset.
Note: Bit softreset is automatically reset after internal reset generation. Software reset is active during 4 CKREF periods. When softreset is activated, all the device is reset as with hardware reset except for the first eight user registers (configuration0-7) and for registers increment_dfs, phase_dfs (increment and phase of oscillator), cgms_bit, ttx_blockn and ccf1-2.
jump, dec_ninc and free_jump

See the description of line insertion and line skipping in the STi5500 datasheet. jump dec_ninc free_jump 0 0 0 Update mode Normal mode (no line skip or insert capability). ITU-R (CCIR): 313/312 or 263/262. Non-interlaced: 312/312 or 262/262. Manual mode for line insert (dec_ninc = 0) or skip (dec_ninc = 1) capability. This is the default mode. Both fields of all the frames following the writing of this value are modified according to Iref and Itarg bits of registers line_reg. By default Iref=0 and Itarg=1 which leads to the normal mode above. Automatic line insert mode. The second field of the frame following the writing of this value is increased. In 525/60, two lines are inserted after line 245. In 625/50, four lines are inserted after line 290. Iref and Itarg are ignored. Automatic line skip mode. The second field of the frame following the writing of this value is decreased. In 525/60, two lines are skipped after line 245. In 625/50, four lines are skipped after line 290. Iref and Itarg are ignored. Two lines are skipped (inserted) in 525/60 and four in 625/50 mode. Reserved. Do not use.
Bit jump is automatically reset after use.
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STi5500 cfc1-0
Color frequency control via CFC line.
CO
cfc2 0 0 1 1
D I F N
cfc1 0 1 0 1
L A I T N E
Update mode
Disabled. Update is done by loading the increment_dfs registers. Default.
Update of increment for DDFS just after serial loading via CFC. Update of increment for DDFS on next active edge of HSYNC. Update of increment for DDFS just before next color burst. Table 9.10 Encoding of cfc
maxdyn
Maximum dynamic magnitude allowed on YCrCb inputs for encoding. (Refer to the STi5500 datasheet for details.) 0 1 0x10 to 0xEB for Y, 0x10 to 0xE0 for chrominance (Cr, Cb). Default. 0x01 to 0xFE for Y, Cr and Cb
Note: in any case, EAV and SAV words are replaced by blanking values before being fed to the luminance and chrominance processors.
INCREMENT_DFS
7 0x0A 0x0B 0x0C Address: Access: d23 d15 d7
DENC Increment for Digital Frequency Synthesizer

6 d22 d14 d6 5 d21 d13 d5 4 d20 d12 d4 3 d19 d11 d3 2 d18 d10 d2 1 d17 d9 d1 0 d16 d8 d0
DENCBaseAddress + 0x0A, 0x0B, 0x0C Read / Write
Description
These registers contain the 24-bit increment used by the DDFS if bit selrst equals 1 to generate the phase of the subcarrier i.e. the address that is supplied to the sine ROM. It therefore allows to customize the subcarrier frequency synthesized. Refer to the STi5500 datasheet for details. 1 LSB ~ 1.6 Hz The procedure to validate usage of these registers instead of the hard-wired values is the following: Load the registers with the required value; Set bit selrst in configuration2 to 1; Perform a software reset using configuration6. Notes: 1 2 3 The values loaded in increment_dfs are taken into account after a software reset, and ONLY IF bit selrst =1. These registers are never reset and must be explicitly written into to contain sensible information. On hardware reset (selrst = 0) or on soft reset with selrst=0, the DDFS is initialized with a hard wired increment, independent of increment_dfs. These hard wired values being out of any user register these cannot be read out of the DENC. These values are given in Table 9.11.
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CO
LINE_REG
0x15 0x16 0x17 Address: Access:
0x21F07C
0x2A098B 0x21F694 0x21E6F0
D I F N
Value of d[23:0] 7 ltarg8 ltarg0 lref1 6
L A I T N E
Standard NTSC M PAL BGHIN PAL N PAL M
STi5500
Frequency synthesized 3.5795452 MHz 4.43361875MHz 3.5820558 MHz 3.57561149 MHz
Ref. Clock 27 MHz 27 MHz 27 MHz 27 MHz
Table 9.11 Hard wired increment after hardware reset
Line jump
5 ltarg6 lref7 4 ltarg5 lref6 3 ltarg4 lref5 2 ltarg3 lref4 1 ltarg2 lref3 0 ltarg1 lref2 ltarg7 lref8 lref0
DENCBaseAddress + 0x15, 0x16, 0x17 Read / write
Description These registers may be used to jump from a reference line (end of that line) to a target line of the SAME FIELD. However, not all lines can be skipped or repeated with no problems and, if needed, this functionality should BE USED WITH CAUTION. lref[8:0] contains in binary format the reference line from which a jump is required. ltarg[8:0] contains the target line binary number. Default values: lref[8:0]:= 000000000 and ltarg[8:0]:= 000000001
PHASE_DFS
phase_dfs1 phase_dfs2 Address: Access: 0x0D 0x0E
Static phase offset for digital frequency synthesizer

7 o21 6 o20 5 o19 4 o18 3 o17 2 o16 1 o23 o15 0 o22 o14
DENCBaseAddress + 0x0D, 0x0E Read / write
Description
Under certain circumstances (detailed below), these registers contain the 10 most significant bits of the value with which the phase accumulator of the DDFS is initialized after a 0-to-1 transition of bit rstosc (configuration2), or after a standard change, or when cyclic phase readjustment has been programmed (see bits valrst[1:0] of configuration2). The 14 remaining bits loaded into the accumulator in these cases are all 0s. This allows the definition of the phase reset value to within a 0.35o accuracy. The procedure to validate usage of these registers instead of the hard-wired values is: Load the registers with the required value Set bit selrst to 1 in configuration2 Perform a software reset (in configuration6) Notes: 1 Registers phase_dfs are never reset and must be explicitly written to before they contain sensible information.
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2
If bit selrst = 0 (e.g. after a hardware reset) the phase offset used every time the DDFS is reinitialized is a hardwired value. The hard-wired values being out of any register, they cannot be read out of the DENC. These are: 0xD9C000 for PAL BDGHI, N, M, 0x1FC000 for NTSC-M.
revid
CO
D I F N
L A I T N E
Digital encoder revision number

Address: Access:
Description
The value of revid is 0x0.
STATUS
7 0x09 Address: Access: hok
DENC Status
6 atfr 5 buf2_free 4 buf1_free 3 fieldct2 2 fieldct1 1 fieldct0 0 jump
Description
hok
Hamming decoding of frame sync flag embedded within ITU-R656 / D1 compliant YCrCb streams 0 1 Consecutive errors. A single or no error. Default.
Note: signal quality detector is issued from Hamming decoding of EAV,SAV from YCrCb
atfr
Frame synchronization flag 0 1 Encoder not synchronized. Default. In slave mode: encoder synchronized.
buf2_free
Closed caption registers access condition for field 2. (Refer to the STi5500 datasheet for details.) Closed caption data for field 2 is buffered before being output on the relevant TV line; buf2_free is reset if the buffer is temporarily unavailable. If the microcontroller can guarantee that register cccf2 is never written more than once between two frame reference signals, then bit buf2_free will always be true (set). Otherwise, closed caption field 2 registers access might be temporarily forbidden by resetting bit buf2_free until the next field 2 closed caption line occurs. Note that this bit is false (reset) when 2 pairs of data bytes are awaiting to be encoded, and is set back immediately after one of these pairs has been encoded (so at that time, encoding of the last pair of bytes is still pending). The default value is 1 (access authorized).
buf1_free
Closed caption registers access condition for field 1 Same as buf2_free but concerns field 1.
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The default value is 1 (access authorized).
fieldct[2:0]
Digital field identification number 000 Indicates field 1 ...
CO
D I F N
L A I T N E
STi5500
111 Indicates field 8 fieldct[0] also represents the odd/even information (odd=0, even=1).
jump
Indicates whether a frame length modification has been programmed at 1 from programming of bit jump to the end of any frames concerned The default value is 0. Refer to registers configuration6 and line_reg.
ttx_block1-4
7 ttx_block1 ttx_block2 ttx_block3 ttx_block4 Address: Access: 0x22 0x23 0x24 0x25
Teletext block definition

6 txbs1.2 txbs2.2 txbs3.2 txbs4.2 5 txbs1.1 txbs2.1 txbs3.1 txbs4.1 4 txbs1.0 txbs2.0 txbs3.0 txbs4.0 3 txbe1.3 txbe2.3 txbe3.3 txbe4.3 2 txbe1.2 txbe2.2 txbe3.2 txbe4.2 1 txbe1.1 txbe2.1 txbe3.1 txbe4.1 0 txbe1.0 txbe2.0 txbe3.0 txbe4.0 txbs1.3 txbs2.3 txbs3.3 txbs4.3
DENCBaseAddress + 0x22 (block1) to 0x25 (block4) Read / Write
Description
The use of these registers is described in the STi5500 datasheet These four Teletext Block Definition registers are used in conjunction with the Teletext Block Mapping register ttx_block_map . Refer to the STi5500 datasheet for details. Each of these registers defines a start line (txbsn[3:0]) and an end line (txben[3:0]). txbsn is the Teletext Block Start for block n, and txben is the Teletext Block End for block n. For n = 1, 2, 3 and 4: txbsn[3:0] = i codes line (7 + i) when applying to field1, txbsn[3:0] = i codes line (320 + i) when applying to field2. The end lines are coded in a similar manner. Line numbering is according to ITU-R601/625. There is no default value; registers ttx_block1-4 are never reset.
ttx_block_map
7 0x26 Address: Access: txmf1.1
Teletext Block Mapping

6 txmf1.2 5 txmf1.3 4 txmf1.4 3 txmf2.1 2 txmf2.2 1 txmf2.3 0 txmf2.4
DENCBaseAddress + 0x26 Read / write
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Description txmf1 stands for Teletext blocks mapping to field1 and txmf2 stands for Teletext blocks Mapping to field 2. This register allows the mapping of the blocks of Teletext lines defined by registers 34 to 37 to either field1, field 2 or both. Its default value is 0. txmf1.N defines whether txbdN applies to field 1, where txbdN means the Nth teletext block, as described under registers ttx_block1-4. Similarly txmf2.N defines whether txbdN applies to field 2. In other words, if txmf1.N = 1 then Teletext will be encoded in field 1 from the line defined by txbsN.[3:0] (see above) to the line defined by txbeN.[3:0]. Similarly, if txmf2.N = 1 then Teletext will be encoded in field 2 from the line defined txbsN.[3:0] (see above) to the line defined by txbeN.[3:0].
CO
D I F N
L A I T N E
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L A I T 10 External memory interface (EMI) registers N E D I F N O C

10 - External memory interface (EMI) registers EMIConfigData0
DRAM format
15 14 13 12 11 10 9 8 7 6 5 4 3 2
STi5500
EMI configuration data register 0
Bank0 0x00 Bank1 0x10 Bank2 0x20 Bank3 0x30
DataDrive BusRelease Delay Time DataDrive BusRelease Delay Time DataDrive BusRelease Delay Time DataDrive BusRelease Delay Time
Sub Banks Sub Banks Sub Banks Sub Banks
SubBank ShiftAmount Size SubBank ShiftAmount Size SubBank ShiftAmount Size SubBank ShiftAmount Size
DeviceType DeviceType DeviceType DeviceType
SRAM/peripheral format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bank0 Bank1 Bank2 Bank3
0x00 0x10 0x20 0x30
DataDriveDelay DataDriveDelay DataDriveDelay DataDriveDelay
BusRelease CSActive Time BusRelease CSActive Time BusRelease CSActive Time BusRelease CSActive Time
OEActive OEActive OEActive OEActive
WEActive WEActive WEActive WEActive
DeviceType DeviceType DeviceType DeviceType
EMIBaseAddress + 0x00, 0x10, 0x20 and 0x30 Read/write See Table 10.2.
Description EMI configuration data register 0 for banks 0 to 3. There is one of these configuration registers for each bank. For safe configuration, each of the four banks should be configured after reset and then have their configuration locked by writing to the EMIConfigLock register before any access to an external bank is made. The format of the configuration registers for a bank depends on the memory device type, i.e. whether the bank is configured for DRAM or for SRAM and peripherals. The type is defined by the DeviceType field in this register.
Bit 15:14 13 12 Bit field Reserved DataDriveDelay BusReleaseTime Function Write 0. Data drive delay; 0-1 phases Bus release time; 0 means 1 cycle, 1 means 2 cycles
Table 10.1 EMI configuration data register 0 format for DRAM
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Bit Bit field
11:10
CO
SubBanks
D I F N
L A I T N E
Function 00 01 10 11 00 01 10 11 no sub-banks 2 sub-banks 4 sub-banks reserved 256k words 1M words 4M words 16M words
10 - External memory interface (EMI) registers
9:8
SubBankSize
7:5 4:3 2:0
ShiftAmount Reserved DeviceType
Column address width (0 means 7 bits, 1 means 8 bits etc.) Write 0. 000 = DRAM. Sets the format of the configuration registers for the bank.
Bit 15:13 12:11 10:9 8:7 6:5 4:3 2:0
Bit field DataDriveDelay BusReleaseTime CSactive OEactive WEactive Reserved DeviceType
Function Data drive delay; 0-7 phases Bus release time; 0-3 cycles See Table 10.3 See Table 10.3 See Table 10.3 Write 0 1 = SRAM/peripheral. Sets the format of the configuration registers for the bank.
Reset 5 2 01 01 00
Table 10.2 EMI configuration data register 0 format for SRAM/Peripherals
Active bit settings 00 01 10 11 Strobe inactive.
Strobe activity
Strobe active during read accesses only. Strobe active during write accesses only. Strobe active during read and write accesses. Table 10.3 Active bit settings
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10 - External memory interface (EMI) registers EMIConfigData1

DRAM format
CO
0x04 0x14 0x24 0x34
D I F N
15 14 13
L A I T N E
12 11 10 9
STi5500
RASbits[22:7] RASbits[22:7] RASbits[22:7] RASbits[22:7]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x04 0x14 0x24 0x34
AccessTimeRead AccessTimeRead AccessTimeRead AccessTimeRead
CSe1Time CSe2Time OEe1Time OEe2Time WEe1Time WEe2Time Read Read Read Read Read Read CSe1Time CSe2Time OEe1Time OEe2Time WEe1Time WEe2Time Read Read Read Read Read Read CSe1Time CSe2Time OEe1Time OEe2Time WEe1Time WEe2Time Read Read Read Read Read Read CSe1Time CSe2Time OEe1Time OEe2Time WEe1Time WEe2Time Read Read Read Read Read Read
Description
EMI configuration data register 1 for banks 0 to 3. There is one of these configuration registers for each bank. For safe configuration, each of the four banks should be configured after reset and then have their configuration locked by writing to the EMIConfigLock register before any access to an external bank is made. The format of the configuration registers for a bank depends on the memory device type, i.e. whether the bank is configured for DRAM or for SRAM and peripherals. The type is defined by the DeviceType field in register EMIConfigData0. Bit 15:0 Bit field RASbits[22:7] Function Page address mask for address bits 22:7
Bit 15:12 11:10 9:8 7:6
Bit field AccessTimeRead CSe1TimeRead CSe2TimeRead OEe1TimeRead
Function 2 cycles + 0-15 cycles Delay of falling edge of CS in3 phases after start of access cycle Delay from rising edge of CS in phases before end of access cycle Delay of falling edge of OE in phases after start of access cycle
Reset 8 0 0 0
Table 10.5 EMI configuration data register 1 format for SRAM
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Bit 5:4 3:2 1:0 Bit field
OEe2TimeRead
CO
WEe1TimeRead
WEe2TimeRead
D I F N
L A I T N E
Function

Reset 0 0 0
Delay from rising edge of OE in phases before end of access cycle
Delay of falling edge of WE in phases after start of access cycle Delay from rising edge of WE in phases before end of access cycle
Table 10.5 EMI configuration data register 1 format for SRAM
EMIConfigData2
DRAM format
15 14
13
12
11
10
Bank0 0x08 Bank1 0x18 Bank2 0x28 Bank3 0x38
RASbits[29:23] RASbits[29:23] RASbits[29:23] RASbits[29:23]
PrechargeTime PrechargeTime PrechargeTime PrechargeTime
RefreshInterval RefreshInterval RefreshInterval RefreshInterval
Refresh RASedge Refresh RASedge Refresh RASedge Refresh RASedge
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bank0 0x08 Bank1 0x18 Bank2 0x28 Bank3 0x38 Address: Access: Reset state:
AccessTimeWrite AccessTimeWrite AccessTimeWrite AccessTimeWrite
CSe1Time CSe2Time OEe1Time OEe2Time WEe1Time WEe2Time Write Write Write Write Write Write CSe1Time CSe2Time OEe1Time OEe2Time WEe1Time WEe2Time Write Write Write Write Write Write CSe1Time CSe2Time OEe1Time OEe2Time WEe1Time WEe2Time Write Write Write Write Write Write CSe1Time CSe2Time OEe1Time OEe2Time WEe1Time WEe2Time Write Write Write Write Write Write
Description EMI configuration data register 2 for banks 0 to 3. There is one of these configuration registers for each bank. For safe configuration, each of the four banks should be configured after reset and then have their configuration locked by writing to the EMIConfigLock register before any access to an external bank is made. The format of the configuration registers for a bank depends on the memory device type, i.e. whether the bank is configured for DRAM or for SRAM and peripherals. The type is defined by the DeviceType field in register EMIConfigData0.
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Bit 15
Bit field
14:8 7:5 4:1 0
CO
Reserved
RASBits[29:23] PrechargeTime
D I F N
L A I T N E
Function Write 0 Page address mask for address bits 29:23 1 to 8 cycles 1 to 16 periods of 128 cycles 0 means 1 cycle or 1 means 2 cycles after start of refresh
STi5500
RefreshInterval RefreshRASedge
Table 10.6 EMI configuration data register 2 register format for DRAM
Bit 15:12 11:10 9:8 7:6 5:4 3:2 1:0
Bit field AccessTimeWrite CSe1TimeWrite CSe2TimeWrite OEe1TimeWrite OEe2TimeWrite WEe1TimeWrite WEe2TimeWrite
Function 2 cycles + 0-15 cycles Delay of falling edge of CS in phases after start of access cycle Delay from rising edge of CS in phases before end of access cycle Delay of falling edge of OE in phases after start of access cycle Delay from rising edge of OE in phases before end of access cycle Delay of falling edge of WE in phases after start of access cycle Delay from rising edge of WE in phases before end of access cycle
Table 10.7 EMI configuration data register 2 register format for SRAM
EMIConfigData3
DRAM format
15 14 13
12
11
10
0x0C 0x1C 0x2C 0x3C
Multi Latch RAS RAS RASe2Time CASe1Time CASe2Time CAStime byte Point e1Time time Multi Latch RAS RAS RASe2Time CASe1Time CASe2Time CAStime byte Point e1Time time Multi Latch RAS RAS RASe2Time CASe1Time CASe2Time CAStime byte Point e1Time time Multi Latch RAS RAS RASe2Time CASe1Time CASe2Time CAStime byte Point e1Time time
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x0C 0x1C 0x2C 0x3C
LatchPoint LatchPoint LatchPoint LatchPoint
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STi5500
Description
EMI configuration data register 3 for banks 0 to 3. There is one of these configuration registers for each bank. For safe configuration, each of the four banks should be configured after reset and then have their configuration locked by writing to the EMIConfigLock register before any access to an external bank is made. The format of the configuration registers for a bank depends on the memory device type, i.e. whether the bank is configured for DRAM or for SRAM and peripherals. The type is defined by the DeviceType field in register EMIConfigData0. Bit 15:12 11 10:9 8 7:6 5:4 3:2 1 0 Bit field Reserved RAStime CAStime RASe1Time RASe2Time CASe1Time CASe2Time Multibyte LatchPoint Function Write 0 1 or 2 cycles 2 cycles + 0-3 cycles Falling edge of RAS. 1-2 phases after start of RASTime Rising edge of RAS. 0-3 phases before end of CASTime Falling edge of CAS. 1-4 phases after start of CASTime Rising edge of CAS. 0-3 phases before end of CASTime When set, enables byte addressing using CAS strobes (byte mode) 0 end of CASTime 1 1 cycle before end of CASTime Table 10.8 EMI configuration data register 3 format for DRAM
CO
D I F N
EMIBaseAddress + 0x0C, 0x1C, 0x2C and 0x3C Read/write 0
L A I T N E
Bit 15:2 1:0
Bit field Reserved LatchPoint
Function Write 0 0 end of access cycle 1 1 cycle before end of access cycle 2 2 cycles before end of access cycle
Reset
Table 10.9 EMI configuration data register 3 format for SRAM and peripherals
EMIConfigLockBank3-0 EMI configuration lock

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x40 0x44 0x48 0x4C Address: Access: Reset state:
Lock0 Lock1 Lock2 Lock3
EMIBaseAddress + 0x40 to 0x4C Write only 0
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EMI configuration write protection locks. When the EMI for a bank has been configured, the configuration should be locked by setting the corresponding lock register to 1. When Lockn is set, EMIConfigData3:0Bankn become read only.
EMIConfigStatus
15 14
CO
D I F N
13 12 11
L A I T N E
10 9 8 7
STi5500
EMI configuration status

6 5 4 3 2 1 0
Bank3 Bank2 Bank1 Bank0 Bank3 Bank2 Bank1 Bank0 Config Config Config Config Config Config Config Config Lock Lock Lock Lock
EMIBaseAddress + 0x50 Read only 0
Description The ConfigStatus register is a read only register which contains information on whether the ConfigData registers have been written to and locked.
Bit 15:8 7 6 5 4 3 2 1 0 Bit field Reserved Bank3ConfigLock Bank2ConfigLock Bank1ConfigLock Bank0ConfigLock Bank3Config Bank2Config Bank1Config Bank0Config Function Write 0 Bank 3 configuration has been locked. Bank 2 configuration has been locked. Bank 1 configuration has been locked. Bank 0 configuration has been locked. When set all the four configuration registers for bank3 have been written at least once. When set all the four configuration registers for bank2 have been written at least once. When set all the four configuration registers for bank1 have been written at least once. When set all the four configuration registers for bank0 have been written at least once. Table 10.10 EMI configuration status register format
EMIDRAMInitialize
15 14 13 12
EMI initialize DRAM

11 10 9 8 7 6 5 4 3 2 1 0
DRAMInit
EMIBaseAddress + 0x60 Write only
Description
A write to this address initializes any DRAM in the system and enables refreshes to take place. The EMIDRAMInitialize register should only be written to when there is DRAM in the system.
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L A I T 11 Interrupt controller registers N E D I F N O C

STi5500 Clear_Exec
0x108 Address: Access: Clr
11 - Interrupt controller registers
Clear a bit of the Exec register

9 8 7 6 5 4 3 2 1 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Clr
Clr
Clr
Clr
Clr
Clr
2
Clr
1
IntControllerBase + 0x108 Write only
Description
Clear_Exec allows bits of Exec to be cleared individually. Writing a 1 in this register resets the corresponding bit in the Exec register, a 0 leaves the bit unchanged.
Clear_Mask
0xC8 Address: Access:
Clear a bit of the interrupt enable mask

9 8 7 6 5 4 3 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Clr
Clr
Clr
Clr
Clr
Clr
Clr
2
Clr
1
IntControllerBase + 0xC8 Write only
Description
Clear_Mask allows bits of Mask to be cleared individually. Writing a 1 in this register resets the corresponding bit in the Mask register, a 0 leaves the bit unchanged.
Clear_Pending
Clear a bit of the Pending register

9 8 7 6 5 4 3 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Clr
Clr
Clr
Clr
Clr
Clr
Clr
2
Clr
1
Description
Clear_Pending allows bits of Pending to be cleared individually. Writing a 1 in this register resets the corresponding bit in the Pending register, a 0 leaves the bit unchanged.
Exec
Interrupts executing
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0
IntEx7
IntEx6
IntEx5
IntEx4
IntEx3
IntEx2
IntEx1
0x10 0 Address: Access: Reset state:
IntControllerBase + 0x100 Read/write 0
Description
The Exec register keeps track of the currently executing and preempted interrupts. A bit is set when the CPU starts running code for that interrupt. The highest priority interrupt bit is reset once the interrupt handler executes a return
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IntEx0
Clr
Clr
Clr
from interrupt (iret). The Exec register is mapped onto two additional addresses Set_Exec and Clear_Exec so that bits can be set or cleared individually.
HandlerWptrn
0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C Address: Access: Reset state:
CO
D I F N
L A I T N E
STi5500
Interrupt handler work space pointer

9 8 7 6 5 4 3 2 1 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
HandlerWptr0[31:2] HandlerWptr1[31:2] HandlerWptr2[31:2] HandlerWptr3[31:2] HandlerWptr4[31:2] HandlerWptr5[31:2] HandlerWptr6[31:2] HandlerWptr7[31:2]
P P P P P P P P
IntControllerBase + 0x00 to 0x1C Read/write Undefined
Description
The HandlerWptr registers (1 per interrupt level) each contain a pointer to the work space of the corresponding interrupt handler. The base of the work space is 32-bit word aligned, so the two least significant bits of the 32-bit address are always zero, and are not held. Each register also contains a priority bit P which determines whether the interrupt is at a higher or lower priority than the high priority process queue. Before the interrupt is enabled by writing a 1 in the Mask register, the software must ensure that there is a valid HandlerWptr in the register. Bit field Bit Function The 30 most significant bits of the address of the work space of the interrupt handler. Reserved, write 0. Sets the priority of the interrupt. If this bit is set to 0, the interrupt is a higher priority than the high priority process queue; if this bit is 1, the interrupt is a lower priority than the high priority process queue. 0 1 high priority low priority
HandlerWptr[31:2] 31:2 1
Table 11.1 HandlerWptrn register format, one register per input
Mask
Interrupt enable mask

31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IntEn7
IntEn6
IntEn5
IntEn4
IntEn3
IntEn2
IntEn1
IntControllerBase + 0xC0 Read/write
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IntEn0
GloEn
STi5500
Reset state: 0
Description An interrupt mask register is provided in the interrupt controller to selectively enable or disable external interrupts. This mask register also includes a global interrupt disable bit to disable all external interrupts whatever the state of the individual interrupt mask bits. To complement this the interrupt controller also includes an interrupt pending register which contains a pending flag for each interrupt channel. The Mask register performs a masking function on the Pending register to give control over what is allowed to interrupt the CPU while retaining the ability to continually monitor external interrupts. On start-up, the Mask register is initialized to zeros, so all interrupts are disabled, both globally and individually. When a 1 is written to the GlobalEnable bit, the individual interrupt channels are still disabled. To enable an interrupt channel, a 1 must also be written to the corresponding InterruptEnable bit.
CO
D I F N
L A I T N E
Bit 7:0 15:8 16
Bit field IntEn[7:0]
Function When set to 1, the corresponding interrupt is enabled. When 0, interrupt is disabled. Reserved, write 0.
GloEn
When set to 1, the setting of the interrupt is determined by the specific InterruptEnable bit. When 0, all interrupts are disabled. Table 11.2 Mask register format
The Mask register is mapped onto two additional addresses Set_Mask and Clear_Mask so that bits can be set or cleared individually.
Pending
7 6
Interrupt pending
5 4 3 2 1 0
0x80
PendInt7
PendInt6
PendInt5
PendInt4
PendInt3
PendInt2
PendInt1
PendInt0
IntControllerBase + 0x80 Read/write 0
Description
The Pending register contains one bit per interrupt level with each bit controlled by the corresponding interrupt. A read can be used to examine the state of the interrupt controller while a write can be used to explicitly trigger an interrupt. A bit is set when the triggering condition for an interrupt is met. All bits are independent so that several bits can be set in the same cycle. Once a bit is set, a further triggering condition will have no effect. The triggering condition is independent of the Mask register. The highest priority interrupt bit is reset once the interrupt controller has made an interrupt request to the CPU. The interrupt controller receives external interrupt requests and makes an interrupt request to the CPU when it has a pending interrupt request of higher priority than the currently executing interrupt handler. If the software needs to write or clear some bits of the Pending register, the interrupts should be masked (by writing or clearing the Mask register) before writing or clearing the Pending register. The interrupts can then be unmasked. The Pending register is mapped onto two additional addresses Set_Pending and Clear_Pending so that bits can be set or cleared individually.
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11 - Interrupt controller registers Set_Exec
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0x104
Address: Access:
CO
D I F N
Set a bit of the Exec register

9 8 7 6 5 4 3 2 1 0
L A I T N E
STi5500
Set
Set
Set
Set
Set
Set
Set
2
Set
1
Description Set_Exec allows bits of Exec to be set individually. Writing a 1 in this register sets the corresponding bit in the Exec register, a 0 leaves the bit unchanged.
Set_Mask
Set a bit of the interrupt enable mask

9 8 7 6 5 4 3 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Set
Set
Set
Set
Set
Set
Set
2
Set
1
IntControllerBase + 0xC4 Write only
Description Set_Mask allows bits of Mask to be set individually. Writing a 1 in this register sets the corresponding bit in the Mask register, a 0 leaves the bit unchanged.
Set_Pending
Set a bit of the Pending register

9 8 7 6 5 4 3 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Set
Set
Set
Set
Set
Set
Set
Set
Description
Set_Pending allows bits of Pending to be set individually. Writing a 1 in this register sets the corresponding bit in the Pending register, a 0 leaves the bit unchanged.
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Set
Set
Set
STi5500 TriggerMode
0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C Address: Access: Reset state:
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CO
D I F N
Interrupt trigger mode
L A I T N E
Trigger0 Trigger1 Trigger2 Trigger3 Trigger4 Trigger5 Trigger6 Trigger7
IntControllerBase + 0x40 to 0x5C Read/write Undefined
Description These registers control the triggering conditions of the interrupts. Each interrupt channel can be programmed to trigger on rising or falling edges or high or low levels on the incoming interrupt signal, as shown in Table 11.3.
Trigger2:0 000 001 010 011 100 101 110 111 No trigger mode High level - triggered while input high Low level - triggered while input low Rising edge - low to high transition Falling edge - high to low transition Any edge - triggered on rising and falling edges No trigger mode No trigger mode Table 11.3 Interrupt trigger modes Level triggering is different from edge triggering in that if the input is held at the triggering level, a continuous stream of interrupts is generated. Interrupt triggers on
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IntIn20
IntIn19
IntIn18
IntIn17
IntIn16
IntIn15
IntIn14
IntIn13
IntIn12
IntIn10
IntIn11
L A I T 12 Interrupt level controller registers N E D I F N O C

12 - Interrupt level controller registers InputInterrupts Input interrupt status
STi5500
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IntIn9
IntIn8
IntIn7
IntIn6
IntIn5
IntIn4
IntIn3
IntIn2
2
IntIn1
1
InterruptLevelBase + 0x7C Read only Undefined
Description
The InputInterrupts register contains a vector which shows the state of each input interrupt signal. This allows the interrupt handler to determine the source of the interrupt, even when several sources are mapped onto the same level. Bit 0 of the read data corresponds to Interrupt0, bit 1 corresponds to Interrupt1 in sequence up to the maximum interrupt. Each bit is 1 when the corresponding interrupt signal is high and 0 when the signal is low. The STi5500 data sheet gives the assignment of interrupt signals and therefore the bits in this register to the peripherals and external pins.
IntnPriority
0x00 ... 0x50 Address: Access: Reset state:
Interrupt priority
9 8 7 6 5 4 3 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Int0Pri ... Int20Pri
InterruptLevelBase + 0x00 to 0x50 Read/write Undefined
Description The priority assigned to each of the input interrupts is programmable via the IntnPriority registers. There is one register for each source of interrupts. Each register has 3 bits and is word aligned. The value in the register is the priority of the interrupt, as shown in Table 12.1.
IntnPri[2:0] 000 001 010 011 100 101 110 111 Assert output interrupt 0 (lowest priority) 1 2 3 4 5 6 7 (highest priority) Table 12.1 Output interrupt coding
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IntIn0
L A I T registers 13 MPEG DMA E controller N D I F N O C

STi5500 MPEGnBurstSize
7
13 - MPEG DMA controller registers
MPEG DMAn burst size

5 4
BurstSize
MPEGDMAnBaseAddress + 0x00 Write only
Description The DMA transfer burst size in response to notCDREQ0-3. A non-zero 5-bit value written to the register is the burst size in bytes; a zero value means a burst size of 32 bytes.
MPEGnDecoderSelect
7 6
MPEG DMAn decoder select

5 4 3 2 1 0
Select
MPEGDMAnBaseAddress + 0x0C Write only
Description
Select the destination for the DMA transfer. The meaning of the MPEGDecoderSel register differs between the MPEGDMA controllers, since the outputs are connected to different destinations. For MPEG DMA0-1, the 2-bit value selects one of the four MPEG CD FIFOs, of which three are connected to modules, as shown in Table 13.1. For MPEG DMA2, a value of 3 must be written, which selects the SDAV as destination for the DMA transfer. Select 0 1 2 3 Video Audio Sub-picture Not defined Module Request signal notCDREQ0 notCDREQ1 notCDREQ2 notCDREQ3 FIFO buffer address #00001800 #00001A00 #00001C00 #00001E00
Table 13.1 MPEG modules and write addresses
MPEGnHoldoff
7 6
MPEG DMAn hold-off time

5 4 3 2 1 0
Holdoff
Description
DMA transfer hold-off time from the end of one burst to re-sampling notCDREQ0-3. A non-zero 5-bit value written to the register is the hold-off time in cycles; a zero value means a hold-off time of 32 cycles.
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13 - MPEG DMA controller registers MPEGnSuspend

7
0x04
CO
D I F N
6
MPEG DMAnsuspend
5 4
L A I T N E
STi5500
Suspend
Description
Zero written to this register suspends DMA operations. When a 1 is written, normal DMA operation is enabled.
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L A I T 14 PES parser (PES) registers N E D I F N O C

STi5500 PES_CF1
0x40 Address: Access: Reset state: Synchronization: 7 6 5 4 SDT FAD IAI
14 - PES parser (PES) registers
PES Audio Decoding Control

0 AUD_ID[4:0]
Description This register controls the audio stream decoding and some miscellaneous parser functions.
Field SDT FAD IAI AUD_ID Bits 7 6 5 4:0 Description Store DTS not PTS. This bit, when set, causes the DTS stamps to be stored instead of the PTS stamps for the video parser. When set to 1, audio compressed data are taken directly from the audio DMA and not from the MPEG2 PES parser/MPEG1 system parser (independent of the parser mode). Ignore Audio Stream id. Audio Stream id. Table 14.1 PES_CF1 register fields
PES_CF2
7 0x41 Address: Access: Reset state: Synchronization: MOD[1:0]
PES Video Parser Control

6 5 SS 4 IVI 3 VID_ID[3:0] 0
Description This register controls the video stream parser.

Field MOD[1:0] SS IVI VID_ID[3:0] Bits 7:6 5 4 3:0 Mode. See Table 14.3. System Stream. This bit, when set, indicates that the stream sent to the parser is a system stream. To decode a pure video or audio stream this bit should be set to zero. Ignore Video Stream i.d. Video Stream i.d. Table 14.2 PES_CF2 register fields Description
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Table 14.3 shows the coding of the modes in MOD[1:0]. MOD[1:0]
CO
00 01 10 11
Automatic configuration. The parser will configure itself to decode the incoming stream.
MPEG-1 system stream with one data strobe input format MPEG-2 PES separate data strobes input format (standard mode).
D I F N
L A I T N E
STi5500
Description
MPEG-2 whole PES video and whole PES audio one after the other with single data strobe input format. Table 14.3 Coding of modes
PES_TM1
DSM Trick Mode

0 PES_TM1[7:0]
VideoBaseAddress + 0x42 Read only 0 None
Description This register stores the DSM trick mode bits. This register may be used only if the ES rate flag of the bit stream is set to zero.
PES_TM2
PES Parser Status

1 M2 0 DSA
VideoBaseAddress + 0x43 Read only 0 None
Description
PES parser status register. M2 MPEG-2 not MPEG-1. This bit indicates, in automatic mode, if the current stream being decoded is an MPEG-2 or an MPEG-1 stream. DSA DSM association flag. This bit, when set indicates that the picture header present in the start code detector is associated to DSM values present in the PES_TM1 register.
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STi5500 PES_TS
0x49
0x4A 0x4B
CO
D I F N
7
PES Time Stamps
L A I T N E
PES_TS [7:0] PES_TS [15:8] PES_TS [23:16] PES_TS [31:24]
0x4C 0x4D Address: Access: Reset state: Synchronization:
TSA
PES_TS [32]
VideoBaseAddress + 0x49 to 0x4D Read only 0 None
Description
These registers store the time stamps selected using the control bit in PES_CF1. TSA Time stamp association. When this bit is set it indicates that the picture to be decoded next (from which the header is available in the start code detector) has an associated time stamp available in PES_TS.
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The STi5500 has 34 bits of parallel I/O, arranged as four 8-bit ports (PIO0-3) and one 2-bit port (PIO4). Each eight-bit PIO port has a set of eight-bit registers, and the 2-bit port has a set of 2-bit registers. Each of the bits of each register refers to the corresponding pin in the corresponding port. The registers listed here are all 8-bit; for PIO4 the registers are similar, but with only two bits, i.e. only bits 0 and 1 are connected.
L A I T 15 Parallel input/output (PIO) registers N E D I F N O C

15 - Parallel input/output (PIO) registers Clear_PnC2:0
Clear_PnC0 Clear_PnC1 Clear_PnC2 Address: Access: 0x28 0x38 0x48
STi5500
Clear bits of PnC2:0

7 6 5 4 3 2 1 0 Clear_PC0[7:0] Clear_PC1[7:0] Clear_PC2[7:0]
PIOnBaseAddress + 0x28, 0x38 and 0x48 Write only
Description
Clear_PnC2:0 allow the bits of registers PnC2:0 to be cleared individually. Writing a 1 in one of these register clears the corresponding bit in the corresponding PnC2:0 register, while a 0 leaves the bit unchanged.
Clear_PnComp
Clear bits of PnComp

6 5 4 3 2 1 0 Clear_PComp[7:0]
PIOnBaseAddress + 0x58 Write only
Description Clear_PnComp allows bits of PnComp to be cleared individually. Writing a 1 in this register clears the corresponding bit in the PnComp register, while a 0 leaves the bit unchanged.
Clear_PnMask
Clear bits of PnMask

6 5 4 3 2 1 0 Clear_PMask[7:0]
Description
Clear_PnMask allows bits of PnMask to be cleared individually. Writing a 1 in this register clears the corresponding bit in the PnMask register, while a 0 leaves the bit unchanged.
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STi5500 Clear_PnOut
0x08
Address: Access:
CO
D I F N
7 6
Clear bits of PnOut

5
L A I T N E
4
15 - Parallel input/output (PIO) registers
Clear_POut[7:0]
Description
Clear_PnOut allows bits of PnOut to be cleared individually. Writing a 1 in this register clears the corresponding bit in the PnOut register, while a 0 leaves the bit unchanged.
PnC2:0
PnC0 PnC1 PnC2 Address: Access: Reset state: 0x20 0x30 0x40
PIO configuration
7 6 5 4 3 2 1 0 ConfigData0[7:0] ConfigData1[7:0] ConfigData2[7:0]
PIOnBaseAddress + 0x20, 0x30 and 0x40 Read/write 0
Description
There are three configuration registers (PnC0, PnC1 and PnC2) for each port, which are used to configure the PIO port pins. Each pin can be configured as an input, output, bidirectional, or alternative function pin (if any), with options for the output driver configuration. Three bits, one bit from each of the three registers, configure the corresponding bit of the port. The configuration of the corresponding I/O pin for each valid bit setting is given in Table 15.1. PnC2[y] 0 0 0 0 1 1 1 1 PnC1[y] 0 0 1 1 0 0 1 1 PnC0[y] 0 1 0 1 0 1 0 1 Bit y configuration Input Bidirectional Output Bidirectional Input Input Alternative function output Alternative function bidirectional Bit y output Hi-Z. Open drain. Push-pull. Open drain. Hi-Z. Hi-Z. Push-pull. Open drain.
Table 15.1 PIO bit configuration encoding The PnC registers are each mapped onto two additional addresses Set_PnC and Clear_PnC so that bits can be set or cleared individually.
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15 - Parallel input/output (PIO) registers PnComp

0x50
CO
D I F N
7 6
PIO input comparison

5 4
L A I T N E
STi5500
PComp[7:0]
PIOnBaseAddress + 0x50 Read/write 0
Description The input compare register PnComp can be used to cause an interrupt if the input value differs from a fixed value. The input data from the PIO ports pins will be compared with the value held in PnComp. If any of the input bits is different from the corresponding bit in the PnComp register and the corresponding bit position in PnMask is set to 1, then the internal interrupt signal for the port will be set to 1. The compare function is sensitive to changes in levels on the pins. For the comparison to be seen as a valid interrupt by an interrupt handler, the change in state on the input pin must be longer in duration than the interrupt response time. The compare function is operational in all configurations for each PIO bit, including the alternative function modes. The PnOut register is mapped onto two additional addresses Set_PnOut and Clear_PnOut so that bits can be set or cleared individually.
PnIn
PIO input
6 5 4 PIn[7:0] 3 2 1 0
PIOnBaseAddress + 0x10 Read only 0
Description The data read from this register will give the logic level present on the input pins of the port at the start of the read cycle to this register. Each bit reflects the input value of the corresponding bit of the port. The read data will be the last value written to the register regardless of the pin configuration selected.
PnMask
PIO input comparison mask

6 5 4 3 PMask[7:0] 2 1 0
Description
When a bit is set to 1, the compare function for the internal interrupt for the port is enabled for that bit. If the respective bit (7 to 0) of the input is different from the corresponding bit in the PnComp register, then an interrupt is generated. The PnMask register is mapped onto two additional addresses Set_PnMask and Clear_PnMask so that bits can be set or cleared individually.
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STi5500 PnOut
0x00
CO
D I F N
7 6
PIO output
L A I T N E
5 4
15 - Parallel input/output (PIO) registers
POut[7:0]
Description This register holds output data for the port. Each bit defines the output value of the corresponding bit of the port. The PnOut register is mapped onto two additional addresses Set_PnOut and Clear_PnOut so that bits can be set or cleared individually.
Set_PnC2:0
Set_PnC0 Set_PnC1 Set_PnC2 Address: Access: 0x24 0x34 0x44
Set bits of PnC2:0

7 6 5 4 3 2 1 0 Set_PC0[7:0] Set_PC1[7:0] Set_PC2[7:0]
PIOnBaseAddress + 0x24, 0x34 and 0x44 Write only
Description Set_PnC2:0 allow the bits of registers PnC2:0 to be set individually. Writing a 1 in one of these registers sets the corresponding bit in the corresponding PnC 2:0 register, while a 0 leaves the bit unchanged.
Set_PnComp
Set bits of PnComp

6 5 4 3 2 1 0 Set_PComp[7:0]
Description
Set_PnComp allows bits of PnComp to be set individually. Writing a 1 in this register sets the corresponding bit in the PnComp register, while a 0 leaves the bit unchanged.
Set_PnMask
Set bits of PnMask

6 5 4 3 2 1 0 Set_PMask[7:0]
Description
Set_PnMask allows bits of PnMask to be set individually. Writing a 1 in this register sets the corresponding bit in the PnMask register, while a 0 leaves the bit unchanged.
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15 - Parallel input/output (PIO) registers Set_PnOut

0x04
Address: Access:
CO
D I F N
7 6
Set bits of PnOut

5
L A I T N E
4
STi5500
Set_POut[7:0]
Description
Set_PnOut allows bits of PnOut to be set individually. Writing a 1 in this register sets the corresponding bit in the PnOut register, while a 0 leaves the bit unchanged.
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L A I T 16 PWM and counter module registers N E D I F N O C

STi5500 PWMnCaptureEdge
16 - PWM and counter module registers
PWM n Capture event definition
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
PWM0CaptureEdge PWM1CaptureEdge PWM2CaptureEdge PWM3CaptureEdge
PWMBaseAddress + 0x30 to 0x3C Read/write ?
Description
The code in register PWMnCaptureEdge defines what constitutes an event on input pin CaptureInn. Possible events are rising edge, falling edge, both or neither (in other words, disabled). CaptureEdge 01 10 11 00 Capture on rising edge Capture on falling edge Capture on rising or falling edge Capture disabled Table 16.1 Encoding of CaptureEdge Meaning
PWMnCaptureVal
PWM n capture value

9 8 7 6 5 4 3 2 1 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PWM0CaptureVal PWM1CaptureVal PWM2CaptureVal PWM3CaptureVal
PWMBaseAddress + 0x10 to 0x1C Read only ?
Description
Each of the four capture value registers holds the 32-bit counter value at the time of the last event occurring at the corresponding CaptureIn pin. When an input event occurs on input CaptureInn, the value of the counter in register PWMCaptureCount at that time is captured in register PWMnCaptureVal. The value can be any 32-bit value. When an input event occurs, an interrupt is generated provided the CapturenIntEn bit of the PWMIntEnable register is set to 1. Bit CaptureIntn of register PWMIntStatus becomes 1, and can be reset by writing 1 to bit CaptureIntAckn of register PWMIntAck. The counter is not stopped nor reset by any of these events.
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16 - PWM and counter module registers PWMnCompareOutVal
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0x40
0x44
CO
D I F N
PWM n compare output value

8 7 6 5 4 3 2 1 0
L A I T N E
STi5500
Compare OutVal0 Compare OutVal1 Compare OutVal2 Compare OutVal3
0x48 0x4C Address: Access: Reset state:
Description Register PWMCompareOutValN holds the value which will be written to the PWMCompareOutN pin when the compare value in PWMCompareValN matches the counter value PWMCaptureCount.
PWMnCompareVal
PWM n compare value

9 8 7 6 5 4 3 2 1 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PWM0CompareVal PWM1CompareVal PWM2CompareVal PWM3CompareVal
Description
Each of the four compare registers PWMnCompareVal in the module can be set to any 32-bit value. When the counter in register PWMCaptureCount reaches the value of register PWMnCompareVal, two things happen: 1 An interrupt is generated provided the PWMnCompareIntEn bit of the PWMIntEnable register is set to 1. Bit PWMCompareIntN of register PWMIntStatus becomes 1, and can be reset by writing 1 to bit PWMnCompareIntAck of register PWMIntAck. 2 Pin PWMnCompareOut takes on the value set in register PWMnCompareOutVal. The counter is not stopped nor reset by any of these events.
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STi5500 PWMnVal
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CO
D I F N
PWM n pulse width
L A I T N E
PWM0Val PWM1Val PWM2Val PWM3Val
Description
These registers hold the counter values, which are used to determine the width of the pulse generated on the PWMOut pin. PWMOut pulse width = (PWMVal + 1) x prescaled clock period If PWMVal is 255 then PWMOut does not go low.
Comment: Should this say 9-bit? Or is the diagram wrong? TP2 says 8-bit 7:0. TP3 says 8-bit 8:0 PWMCaptureCount
PWM capture/compare counter

9 8 7 6 5 4 3 2 1 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CaptureCount
PWMBaseAddress + 0x64 Read/write ?
Description This register holds the shared capture/compare counter used by all the capture and compare functions. The capture/compare counter is clocked from the prescaled system clock. The prescaling factor, and therefore the period represented by one count, is determined by the value of field CaptureClkValue in register PWMControl. The factor can be from 1 to 32. The counter is enabled by setting the PWMCaptureEnable bit of the PWMControl register to 1. When it is disabled (PWMCaptureEnable is 0), none of the capture or compare functions work. PWMCaptureCount can be read or written at any time. When the capture/compare counter reaches its maximum count of #FFFFFFFF, it wraps round to count up from zero again.
PWMControl
PWM control register

10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
Capture PWM Enable Enable
Capture ClkValue
PWM ClkValue
PWMBaseAddress + 0x50 Read/write ?
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Description
Bit 10 9 8:4 3:0
CO
Bit field
CaptureEnable PWMEnable
D I F N
L A I T N E
Function Enables capture/compare counter when = 1 Enables PWM counter when = 1 Capture/compare clock prescale factor 0-31 (divide clock by value + 1) PWM clock prescale factor 0-15 (divide clock by value + 1)
STi5500
CaptureClkValue PWMClkValue
PWMCount
PWM output counter

8 7 6 5 4 3 2 1 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Count
PWMBaseAddress + 0x60 Read/write (but see text) ?
Description
PWM output counter. The counter (in register PWMCount) is enabled by setting the PWMEnable bit of the PWMControl register to 1. When it is disabled (PWMEnable is 0), pin PWMOut is forced low. PWMCount is writable at any time but can have a synchronization latency.
PWMIntAck
PWM interrupt acknowledge

9 8 7 6 5 4 3 2 1 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
CmpIA3
CmpIA2
CmpIA1
CmpIA0
CptIA3
CptIA2
CptIA1
CptIA0
0x5C
Address: Access:
PWMBaseAddress + 0x5C Write only
Description
Bit 8 7 6 5 4 3 2 1 0 CmpIA3 CmpIA2 CmpIA1 CmpIA0 CptIA3 CptIA2 CptIA1 CptIA0 IntAck Bit field CompareIntAck3 CompareIntAck2 CompareIntAck1 CompareIntAck0 CaptureIntAck3 CaptureIntAck2 CaptureIntAck1 CaptureIntAck0 PWMIntAck Function Compare 3 interrupt acknowledge: write 1 to reset status bit Compare 2 interrupt acknowledge: write 1 to reset status bit Compare 1 interrupt acknowledge: write 1 to reset status bit Compare 0 interrupt acknowledge: write 1 to reset status bit Capture 3 interrupt acknowledge: write 1 to reset status bit Capture 2 interrupt acknowledge: write 1 to reset status bit Capture 1 interrupt acknowledge: write 1 to reset status bit Capture 0 interrupt acknowledge: write 1 to reset status bit. Interrupt acknowledge: write 1 to reset PWMInt to 0
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IntAck
STi5500 PWMIntEnable
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0x54
CO
CmpIE3
CmpIE2
CmpIE1
CmpIE0
CptIE3
CptIE2
CptIE1
2
CptIE0
1
PWMBaseAddress + 0x54 Read/write
Description
Bit 8 7 6 5 4 3 2 1 0 CmpIE3 CmpIE2 CmpIE1 CmpIE0 CptIE3 CptIE2 CptIE1 CptIE0 IntEn Bit field CompareIntEn3 CompareIntEn2 CompareIntEn1 CompareIntEn0 CaptureIntEn3 CaptureIntEn2 CaptureIntEn1 CaptureIntEn0 PWMIntEn Function Compare 3 interrupt enable: 1 = enabled Compare 2 interrupt enable: 1 = enabled Compare 1 interrupt enable: 1 = enabled Compare 0 interrupt enable: 1 = enabled Capture 3 interrupt enable: 1 = enabled Capture 2 interrupt enable: 1 = enabled Capture 1 interrupt enable: 1 = enabled Capture 0 interrupt enable: 1 = enabled PWM counter overflow interrupt enable
PWMIntStatus
PWM interrupt status

9 8 7 6 5 4 3 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Cmp3
Cmp2
Cmp1
Cmp0
Cpt3
Cpt2
Cpt1
Cpt0
PWMBaseAddress + 0x58 Read only
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Int
IntEn
D I F N
PWM interrupt enable
L A I T N E

Description
Bit 8 7 6 5 4 3 2 1 0
CO
Cpt3 Cpt2 Cpt1 Cpt0 Int
Cmp3 Cmp2 Cmp1 Cmp0
D I F N
Bit field
L A I T N E
Function Compare 3 interrupt: 1 = interrupt Compare 2 interrupt: 1 = interrupt Compare 1 interrupt: 1 = interrupt Compare 0 interrupt: 1 = interrupt Capture 3 interrupt: 1 = interrupt Capture 2 interrupt: 1 = interrupt Capture 1 interrupt: 1 = interrupt Capture 0 interrupt: 1 = interrupt 1 means PWM counter overflow
STi5500
CompareInt3 CompareInt2 CompareInt1 CompareInt0 CaptureInt3 CaptureInt2 CaptureInt1 CaptureInt0 PWMInt
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L A I T 17 SmartCard interface (Sc) registers N E D I F N O C

STi5500 ScnClkCon
17 - SmartCard interface (Sc) registers
SmartCard n clock control
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Enable Source
SmartCardnBaseAddress + 0x04 Write only 0
Description
The ScnClkCon register controls the source of the clock and determines whether the SmartCard clock output is enabled. The programmable divider and the output are reset when the enable bit is set to 0. Bit 7:2 1 Enable Bit field Function Reserved. Write 0. SmartCard clock generator enable bit. 0 1 0 1 Stop clock, set output low and reset divider. Enable clock generator. Selects global clock. Selects external pin.
Selects source of SmartCard clock. 0 Source
ScnClkVal
SmartCard n clock
9 8 7 6 5 4 3 2 1 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ScClkVal
SmartCardnBaseAddress + 0x00 Write only 0
Comment: ...but 0 is an illegal value!

Description The ScnClkVal register determines the SmartCard clock frequency. The 5-bit value given in the register is multiplied by 2 to give the division factor of the input clock frequency. For example, if ScnSlkVal is 8 then the input clock frequency is divided by 16. The value zero must not be written into this register. The divider is updated with the new value for the divider ratio on the next rising or falling edge of the output clock.
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L A I T (SPD) registers 18 Sub-picture E decoder N D I F N O C

18 - Sub-picture decoder (SPD) registers SPD_CTL1
0x00 Address: Access: Reset state: Synchronization:
STi5500
Control Register 1
6 5 SPP
1 D
0 S
SubPictureBaseAddress + 0x00 Read/write 0 VSYNC (field)
Description This register contains control bits for the subpicture decoder.
Field SPP B H V Bit 5 4 3 2 Description Sub-picture pause mode. When this bit is set the 90 KHz clock in the sub-picture decoder is paused.
Bypass. This bit when set puts the run-length decoder into transparent mode. This allows standard 2-bit-per-pixel bitmaps to be fed into the sub-picture decoder. Highlight Enable. This bit, when set, turns on highlighting inside the sub-picture display area. Display Active. This bit, when reset, turns off the sub-picture display, however, decoding still goes on even when the display is disabled. When decoding is disabled using the Decoder active bit then the display is automatically disabled. Decoder Active. This bit is set by the decoder when, at shadow register update, the Subpicture start bit is sampled high. When the decoder active bit is reset decoding is disabled and can only be re-enabled by the decoder start bit. Sub-Picture Decoder Start command. When this bit is set it indicates the start of a new subpicture unit. The subpicture decoder will then reset the local time reference counter. The state is sampled on each VSYNC.
Table 18.1 Register fields
SPD_CTL2
Control Register 2
1 Ri 0 Rc
SubPictureBaseAddress + 0x02 Read/write 0 None
Description
This register contains control bits for the subpicture decoder. Ri Reset Input Fifo. This bit, when set, resets the bit-buffer input FIFO. Rc Reset Lut #2. This bit, when set, resets the auto-increment address counter.
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STi5500 SPD_HLRC
0x16 0x17
CO
D I F N
7
Highlight Region Contrast

4 3 e1[3:0] b[3:0] 0 e2[3:0] p[3:0]
L A I T N E
18 - Sub-picture decoder (SPD) registers
SubPictureBaseAddress + 0x16 and 0x17 Read/write 0 VSYNC
Description
These registers contain the highlight contrast map values.
SPD_HLRCO
7 0x14 0x15 Address: Access: Reset state: Synchronization:
Highlight Region Color

4 e2[3:0] p[3:0] 3 e1[3:0] b[3:0] 0
Description These registers contain the highlight color map values.
SPD_HLEX
Highlight Region End X

2 1 0
SPD_HLEX[9:8] SPD_HLEX[7:0]
Description Highlight region end position X-coordinate.
SPD_HLEY
7 0x12 0x13
Highlight Region End Y

2 1 0
SPD_HLEY[9:8] SPD_HLEY[7:0]
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Description
Highlight region end position Y-coordinate.
CO
D I F N
7
L A I T N E
STi5500
SPD_HLSX
Highlight Region Start X

2 0 SPD_HLSX[9:8] SPD_HLSX[7:0]
0x0C 0x0D Address: Access: Reset state: Synchronization:
SubPictureBaseAddress + 0x0C and 0x0D Read/write 0 VSYNC
Description
Highlight region start position X-coordinate.
SPD_HLSY
7 0x0E 0x0F Address: Access: Reset state: Synchronization:
Highlight Region Start Y

6 5 4 3 2 1 0 SPD_HLSY[9:8] SPD_HLSY[7:0]
SubPictureBaseAddress + 0x0E and 0x0F Read/write 0 VSYNC
Description Highlight region start position Y-coordinate.
SPD_LUT
Main Lookup Table

0 SPD_LUT[7:0]
SubPictureBaseAddress + 0x03 Read/write 0 None
Description
This register allows input of the main lookup table. Writing to this register auto-increments the address in the lookup table. For each color, starting with color 0, the Y component (8-bit) is written first followed by U and V. The process continues for each color up to 16 colors.
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STi5500 SPD_RST
0x01
CO
D I F N
7
Sub-picture reset
L A I T N E
0 SPR
SubPictureBaseAddress + 0x01 Read/write 0 Edge triggered
Description This register contains the subpicture reset, SPR. When this bit is set to 1 the subpicture decoder is reset. ( The subpicture decoder is also reset by a hard reset.)
SPD_SPB
Sub-picture buffer begin

6 5 4 3 2 1 SPD_SPB[10:8] SPD_SPB[7:0] 0
SubPictureBaseAddress + 0x50 and 0x51 Read/write 0 None
Description This register gives the start address of the sub-picture circular buffer as an offset from the base of SDRAM in units of 64 bytes. The buffer should be aligned on a 1 Kbyte boundary.
SPD_SPE
Sub-picture buffer end

6 5 4 3 2 1 SPD_SPE[10:8] SPD_SPE[7:0] 0
SubPictureBaseAddress + 0x52 and 0x53 Read/write 0 None
Description
This register holds the stop address of the sub-picture circular buffer as an offset from the base of SDRAM in units of 64bytes. The buffer should be aligned on a 1 Kbyte boundary.
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18 - Sub-picture decoder (SPD) registers SPD_SPRead
1st cycle
2nd cycle 3rd cycle
CO
D I F N
7
SubPicture Read Pointer

2 SPD_SPRead[18:16] SPD_SPRead[15:8] SPD_SPRead[7:0] 0
L A I T N E
STi5500
SubPictureBaseAddress + 0x4E Read/write 0 VSYNC
Description
These three registers are accessed serially. The byte pointer is reset by a hardware reset. This register is used when the software needs to set the read address of the sub-picture decoder and is programmed in units of 64-bit words. This value is taken into account after a VSYNC. This register holds the absolute address in the memory.
SPD_SPWrite
7 1st cycle 2nd cycle 3rd cycle Address: Access: Reset state: Synchronization:
SubPicture Write Pointer

2 SPD_SPWrite[18:16] SPD_SPWrite[15:8] SPD_SPWrite[7:0] 0
SubPictureBaseAddress + 0x4F Read/write 0 None
Description These three registers are accessed serially. The byte pointer is reset by a hardware reset. This register is used when the software needs to set the write address of the sub-picture decoder and is programmed in units of 64-bit words. It is recommended to stop loading Sub-picture data to the sub-picture decoder FIFO before changing the value of this register. This register holds the absolute address in the memory.
SPD_SXD0
Sub-picture display area

6 5 4 3 2 1 0 SPD_SXD0[9:8] SPD_SXD0[7:0]
Description
These registers contain the parameters which define the subpicture display area within the subpicture decode area. The value represents an offset from the corresponding parameter used to define the subpicture decode area. For example: The true horizontal start position of the subpicture display will be equal to XDO + SXDO.
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STi5500 SPD_SXD1
0x28 0x29
CO
D I F N
7 6
Subpicture Display Area

5 4 3 2 1 0 SPD_SXD1[9:8] SPD_SXD1[7:0]
L A I T N E
Description
These registers contain the parameters which define the subpicture display area within the subpicture decode area. The value represents an offset from the corresponding parameter used to define the subpicture decode area.
SPD_SYD0

6 5 4 3 2 1 0 SPD_SYD0[9:8] SPD_SYD0[7:0]
Description These registers contain the parameters which define the subpicture display area within the subpicture decode area. The value represents an offset from the corresponding parameter used to define the subpicture decode area.
SPD_SYD1
7 0x2A 0x2B Address: Access: Reset state: Synchronization:

6 5 4 3 2 1 0 SPD_SYD1[9:8] SPD_SYD1[7:0]
SubPictureBaseAddress + 0x2A and 0x2B Read/write 0 VSYNC
Description
These registers contain the parameters which define the subpicture display area within the subpicture decode area. The value represents an offset from the corresponding parameter used to define the subpicture decode area.
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18 - Sub-picture decoder (SPD) registers SPD_XD0

0x04 0x05
CO
D I F N
7 6
Sub-picture X Offset
5
L A I T N E
4
STi5500
SPD_XD0[9:8] SPD_XD0[7:0]
Description
This register value sets the horizontal position of the left hand side of the active subpicture decode region. The position is measured in number of pixels from the left hand edge of the screen.
SPD_XD1
Horizontal Position of Active Area

6 5 4 3 2 1 0 SPD_XD1[9:8] SPD_XD1[7:0]
Description This register value sets the horizontal position of the right side of the active subpicture decode region. The position is measured in units of pixels from the left hand edge of the screen.
SPD_YD0
Sub-picture Y Offset
6 5 4 3 2 1 0 SPD_YD0[9:8] SPD_YD0[7:0]
Description
This register value sets the vertical position of the top of the active subpicture decode region. The position is measured in number of pixels from the top edge of the screen.
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STi5500 SPD_YD1
0x0A 0x0B
CO
D I F N
7 6
Vertical Position of Active Area

5 4 3 2 1 0 SPD_YD1[9:8] SPD_YD1[7:0]
L A I T N E
SubPictureBaseAddress + 0x0A and 0x0B Read/write 0 VSYNC
Description
This register value sets the vertical position of the bottom of the active subpicture decode region. The position is measured in units of pixels from the top edge of the screen.
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L A I T 19 Synchronous serial controller (SSC) registers N E D I F N O C

19 - Synchronous serial controller (SSC) registers SSC0BRG
STi5500
SSC 0 baud rate generation

11 10 9 8 7
15
14
13
12
BRG
SSC0BaseAddress + 0x00 Read/write 1
Description This address is dual purpose. When reading, the current 16-bit counter value is returned. When a value is to this address, the 16-bit reload register is loaded with that value.
SSC0Con
15 14 13
SSC 0 control
12 11 10 9 8 7 6 5 4 3 2 1 0
LPB
EN
MS
SR
PO
PH
HB
BM
SSC0BaseAddress + 0x0C Read/write 0
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STi5500
Description
Bit
15:11 10
CO
LPB EN MS
Bit Field
D I F N
0 0
Reset State
L A I T N E
Reserved SSC Loopback Bit 0 1 0 1 0 1 0 1 SSC Enable Bit
19 - Synchronous serial controller (SSC) registers
Function
disabled shift register output is connected to shift register input transmission and reception disabled transmission and reception enabled slave mode master mode device is not reset all functions are reset while this bit is set clock idles at logic 0 clock idles at logic 1 pulse in second half cycle pulse in first half cycle LSB first MSB first
SSC Master Select Bit 8 0
SSC Software Reset 7 SR
SSC Clock Polarity Control Bit 6 PO 0 0 1 0 1 0 1
SSC Clock Phase Control Bit 5 PH 0
SSC Heading Control Bit 4 HB 0
SSC Data Width Selection BM[3:0] Data Width 0000 Reserved. Do not use this combination. 0001 2 bits 0010 3 bits ... ... 1111 16 bits
3:0
BM
0000
Comment: Reset value for BM is illegal. SSC0IEn

15 14 13
SSC 0 interrupt enable

12 11 10 9 8 7 6 5 4 3 2 1 0
ARBLEN
STOPEN
AASEN
REEN
PEEN
TEEN
0x10
SSC0BaseAddress + 0x10 Read/write 0
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RIEN
TIEN

Description This register holds the interrupt enable bits, which can be used to mask the interrupts.
Bit 15:9 8
CO
Bit Field
D I F N
0 0
L A I T N E
Reserved 1
STi5500
Reset State
Function
ARBLEN
I2C Arbitration Lost Interrupt Enable arbitration lost interrupt enabled I2C Stop Condition Interrupt Enable 1 stop condition interrupt enabled I2C Addressed As Slave Interrupt Enable 1 addressed as slave interrupt enabled Reserved
STOPEN
6 5 4 3 2 1 0
AASEN
PEEN REEN TEEN TIEN RIEN
0 0 0 0 0
Phase Error Interrupt Enable 1 1 1 1 1 phase error interrupt enabled receive error interrupt enabled transmit error interrupt enabled transmitter buffer empty interrupt enabled receiver buffer interrupt enabled Receive Error Interrupt Enable Transmit Error Interrupt Enable Transmitter Buffer Empty Interrupt Enable Receiver Buffer Full Interrupt Enable
SSC0RBuf
15 14 13
SSC 0 receive buffer

12 11 10 9 8 7 6 5 4 3 2 1 0
RD[15:0]
SSC0BaseAddress + 0x08 Read only 0
Description
Receive buffer data D15 to D0.
SSC0SlAd
15 14 13
SSC 0 slave address

12 11 10 9 8 7 6 5 4 3 2 1 0
SL[9:7]
SL[6:0]
SSC0BaseAddress + 0x1C Write only 0
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STi5500
Description The slave address is written into this register. If the address is a 10-bit address it is written into bits 9:0. If the address is a 7-bit address then it is written into bits 6:0.
SSC0Stat
0x14
CO
15
D I F N
13 12
L A I T N E
11 10 9 8
SSC 0 status
7 6 5 4 3 2 1 0
14
BUSY ARBL STOP AAS CLST
PE
RE
TE
TIR
RIR
SSC0BaseAddress + 0x14 Read only 2, i.e. all active bits clear except TIR.
Description
Bit 15:10 9 BUSY 0 Bit Field Reset State Reserved I2C bus busy flag 1 ARBL 0 I2C bus busy I2C arbitration lost flag 1 STOP 0 arbitration lost I2C stop condition flag 1 AAS CLST PE RE TE TIR RIR 0 0 0 1 0 0 stop condition detected I2C addressed as slave flag 1 addressed as slave device I2C clock stretch flag 1clock stretching in operation Phase error flag 1 1 phase error set receive error set Receive error flag Transmit error flag 1transmit error set Transmitter buffer empty flag 1transmitter buffer empty Receiver buffer full flag 1receiver buffer full Function
6 5 4 3 2 1 0
SSC0TBuf
15 14 13
SSC 0 transmit buffer

12 11 10 9 8 7 6 5 4 3 2 1 0
TD[15:0]
SSC0BaseAddress + 0x04 Write only
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Reset state: 0
Description Transmit buffer data D15 to D0.
CO
D I F N
L A I T N E
STi5500
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L A I T 20 Transport stream demultiplexor registers N E D I F N O C

STi5500 STREAM n configuration1
stream_conf_1n @ 0x2002580+4n
20 - Transport stream demultiplexor registers
STREAM n configuration2
STREAM n configuration3
A_PTS_REG
0xFA4 Address: Access:
Audio time stamp

9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
A_PTS
TransportDemuxBaseAddress + 0xFA4 Read only
Description
Bit 31:0 A_PTS Signal Name Actual audio PTS (90 kHz) Table 20.1 Contents of register A_PTS_REG Comment R Type
AF_REG1-0
Adaptation field
9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0xF9C 0xF98 Address: Access:
AF_7 AF_3
AF_6 AF_2
AF_5 AF_1
AF_4 AF_0
TransportDemuxBaseAddress + 0xF98 - 0xF9C Read only
Description
Table 20.2 defines the AF_REG registers, which hold the first eight bytes of the adaptation field. The interrupt is generated if mask = 1.
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Register
AF_REG1
CO
D I F N
0xF9C 0xF98
Address
L A I T N E
Bit 31:24 23:16 15:8 7:0 31:24 23:16 15:8 7:0
STi5500
Signal Name
Comment AF Byte #7 AF Byte #6 AF Byte #5 AF Byte #4 AF Byte #3 AF Byte #2 AF Byte #1 AF Byte #0 R R R R R R R R
Type
AF_7 AF_6
AF_5 AF_4 AF_3 AF_2 AF_1 AF_0
AF_REG0
Table 20.2 Contents of registers AF_REG[1:0]
AR_SIZE_REG
AR size
9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0xFB0 Address: Access: Reset state:
AR_SIZE
TransportDemuxBaseAddress + 0xFB0 Read/write 0x3E
Description
Bit 31:6 5:0
Signal Name Not used AR_SIZE Programmable AR size.
Comment
Type
Reset
R/W
0x3E
Table 20.3 Contents of register AR_SIZE_REG
EN_LINK_REG
0xFC0 Address: Access: Reset state:
Enable link
9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TransportDemuxBaseAddress + 0xFC0 Read/write 0
Description
Bit 31:1 0:0 Field Not used EL ENABLE_LINK Enable Transport Stream Demultiplexor R/W 0 Signal Name Comment Type Res
Table 20.4 Contents of register EN_LINK_REG
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EL
STi5500 EXTRA_BITS_REG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0xFC8
CO
Field
EBI
EBI
TransportDemuxBaseAddress + 0xFC8 Read/write Undefined except bit 0 reset to 0.
Description
Bit 31:13 12:5 4:1 Signal Name Comment Type Res
Not used EBI EBI EXTRA_BITS_INPUT EXTRA_BITS_INPUT Incoming EXTRA_BYTES Playback rate control Incoming EXTRA_BYTES Copy guard information Interrupt mask for the extra bits 1 Enable interrupt on change of extra bits 0 Disable interrupt R R X X
EBM
EXTRA_BITS_IRQ_MASK
R/W
Table 20.5 Contents of register EXTRA_BITS_REG
LINK_STAT_FIFO
EOS EOF
FIFO status
9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PCR
IF
0xF84 Address: Access:
SN
CC
PT
OM
AO
DO
SO
BS
SU
AF
TM
TransportDemuxBaseAddress + 0xF84 Read only
Description The LINK_STAT_FIFO register is the FIFO status word. For DVB, if bit AF is 1 then LINK_STAT_FIFO(15:0) is set to the first 2 bytes of the AF. For bit EOS, the delay between the Interrupt generation and the actual transfer of the last byte of the section to memory can be up to 4 s.
Bits 31 30 29 28 27 26 25 Field EOF EOS IF AF AO DO BS Full field name END_OF_FILTER END_OF_SECTION INCOMPLETE_FILTER AF AR_OVERFLOW BUF_OVERFLOW BAD_SEC 1 End of section filtering 1 End of section transfer 1 Filtering not complete at end of pack 1 Adaptation field received 1 Acquisition RAM overflow 1 Storage buffer overflow 1 Bad section received Table 20.6 Contents of register LINK_STAT_FIFO Meaning Type R R R R R R R
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EBM
D I F N
Extra bits
L A I T N E

Bits 24 23 22 21 20:16 15:12 Field SU Full field name
CO
SO PCR SN CC
D I F N
PCR
SDAV_UNDERFLOW
L A I T N E
STi5500
Meaning Type R R R
1 SDAV Underflow if SDAV_overflow = 0
Else interrupt for EXTRA_BITS 1 SDAV overflow if SDAV_underflow = 0 Else interrupt for EXTRA_BITS 1 PCR has been latched
SDAV_OVERFLOW
Not used STREAM_NUMBER Continuity counter Stream number of packet Continuity counter If DVB: Bit 11 PAYLOAD_UNIT_START_INDICATOR Bit 10 SCRAMBLING_INDICATOR Bit 9 KEY_INDICATOR (0: even; 1: odd) If DSS: Bit 11 HD(3) Bit 10 HD(2) Bit 9 KEY_INDICATOR (0: odd; 1: even) At least 1 match in the top 24 targets Shows the 8 lowest target matches R R
11:9
PT
Packet type
8 7:0
OM TM
OTHER_MATCH TARGET_MATCH
R R
Table 20.6 Contents of register LINK_STAT_FIFO
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STi5500 LINK_STAT_REG
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0xF80
CO
Field
D I F N
Status
L A I T N E
FRA
FWA
TransportDemuxBaseAddress + 0xF80 Read only except bit 2, which is read/write Undefined except bit 2, which is reset to 0
Description
LINK_STAT_REG is the status register. Bits 31:21 20:16 15 14 13 12:8 7:3 2 1 0 Full field name Comment Type Reset
Not used FRA FIFO_RD_ADD Actual read pointer position of IRQ FIFO R x
Not used TE FE FWA TRANSPORT_ERROR F_Error FIFO_WR_ADDR 1 Error specified in the TP header 1 Error specified by the FEC interface Actual write pointer position of IRQ FIFO R R R x x x
Not used FR FO FNE FIFO_RESET FIFO_OVERFLOW FIFO_NOT_EMPTY 1 FIFO pointers are reset 1 FIFO has overflowed 1 FIFO is not empty R/W R R 0 x x
Table 20.7 Contents of register LINK_STAT_REG
MODE_REG
Mode
9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DVD_M
0xF90 Address: Access: Reset state:
TransportDemuxBaseAddress + 0xF90 Read/write 0x001
Description Table 20.8 defines the mode register. DVB_MODE, DSS_MODE and DVD_MODE are mutually exclusive, so exactly one of them must be set to 1.
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DVB_M
DSS_M
DFB
BO
PM
NC
LS
FNE
FO
FR
TE
FE
Bits 31:8 7 6 5 4 3 2 1 0
Field
CO
DFB PM BO NC LS DVD_ M
Not used
D I F N
PCM_MODE BIT_ORDER NRSS_CARD LINK_SDAV DVD_MODE
Signal name
L A I T N E
1 MSB First 0 LSB First
STi5500
Comment
Type
Reset
DISABLE_FINAL_BURST
1 No Full Burst for the Last Transfer 0 The Last Transfer Can Be a Full Burst 1 PCM Mode is Enabled 0 PCM Mode is Disabled
R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 1
1 NRSS Card is Used 0 No NRSS Card 1 Input From SDAV 0 Input From Link/Channel 1 DVD Mode 1 DSS Mode 1 DVB Mode Table 20.8 Contents of register MODE_REG
DSS_M DSS_MODE DVB_ M DVB_MODE
PACKET_LENGTH
Packet length
9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PACKET_LENGTH
TransportDemuxBaseAddress + 0xF88 Read/write 0xBC
Description
Bits 31:12 11:0 Signal name Not used PACKET_LENGTH Number of bytes per packet Table 20.9 Contents of register PACKET_LENGTH_REG R/W 0xBC Comment Type Reset
PCR_EXT_REG
0xFA C Address: Access:
PCR extension
9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PCR_EXT
TransportDemuxBaseAddress + 0xFAC Read only
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Description
Bit 31:9 8:0
CO
Not used
D I F N
Signal Name
L A I T N E
Comment
Type
PCR_EXT
Actual PCR extension (27 MHz) Table 20.10 Contents of register PCR_EXT_REG
PCR_REG
PCR
9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PCR
Description
Bit 31:0 PCR Signal Name Actual PCR (90 kHz) Table 20.11 Contents of register PCR_REG Comment R Type
PCR_STREAM_REG
PCR stream
9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PIM
PSN
TransportDemuxBaseAddress + 0xF94 Read/write 0x0
Description
Bits 31:6 5 4:0 Field Not used PIM PSN PCR_IRQ_MASK PCR_STREAM_NB Interrupt mask on PCR_IRQ Stream which contains PCR R/W R/W 0 0 Signal name Comment Type Reset
Table 20.12 Contents of register PCR_STREAM_REG
SDAV_CONF_REG
SDAV configuration
9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DAM
SDC
SDH
SDE
IS
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0xFB4
THRESHOLD
EC
SE
EXTRA_BITS
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Description
Bit
CO
Field SE SDC
D I F N
TransportDemuxBaseAddress + 0xFB4 Read/write Undefined except bits 12, 14, 15 and 22 reset to 0.
L A I T N E
STi5500
Signal Name
Comment
Type Reset
31:27 26
Not used STUFFING_ENABLE ONLY in P1394 and DSS, active high: 1 Packet has 10 bytes of stuffing appended 0 Packet has no stuffing For the SDAV clock switch Mechanism: 1 Before setting PCM_CLK_SWITCH to 1 0 Before resetting PCM_CLK_SWITCH to 0 R/W X
25
AD_SDAV_CLK_SWITCH
R/W
24
SDH
In IEEE 1394 mode enable the header: SDAV_HEADER_ENABLE 1 Packet has a STi5500 header 0 Packet has no STi5500 header 1394_IS_SLOW SDAV_ENABLE THRESHOLD 1 0MHz < 1394_CLK < 40MHz 0 40MHz < 1394_CLK < 60MHz 1 SDAV enabled 0 SDAV disabled - x SDAV buffer threshold to start output transfer 1 IEEE 1394 0 SDAV (osc_in: 49.152MHz) 1 Output mode 0 Input mode Active only when PCM_MODE = 0 1 Input from descrambler 0 Input from acq. RAM (scrambled) 1 External clock (osc_in pin) 0 Internal clock (SYS_CLK) Inserted into the SDAV packet headers Table 20.13 Contents of register SDAV_CONF_REG
R/W
23 22 21:16 15 14
IS SDE
R/W R/W R/W R/W R/W
X 0 X 0 0
S D
SDAV_1394 DIRECTION
13
DAM
DES_AR_MODE
R/W
12 11:0
EC
EXT_CLK EXTRA_BITS
R/W R/W
0 X
SDAV_DATA_REG
0xFBC Address: Access: Reset state:
SDAV data
9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SDAV_DATA
TransportDemuxBaseAddress + 0xFBC Read/write Undefined
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Description
Bit 31:0
CO
SDAV_DATA
D I F N
Signal Name
L A I T N E
SDAV data write port
Comment
Type R/W x
Res
Table 20.14 Contents of register SDAV_DATA_REG
SDAV_DMA_EN_REG
0xFB8 Address: Access: Reset state: Bit Field
SDAV DMA enable

9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LBP
FBP
TransportDemuxBaseAddress + 0xFB8 Read only Undefined except bit 0 reset to 0

Signal Name Comment Type Reset
31:6 Not used 5 IIF INSERT_IF_EMPTY 1 Insertion of CPU packets only if no transfer from the R Transport Stream Demultiplexor to the STi5500 x
4:3
LBP
LAST_BYTE_POSIT
Defines which bytes are active in the last word of the DMA 11 DMA_DATA[31:0] 10 DMA_DATA[23:0] 01 DMA_DATA[15:0] 00 DMA_DATA[7:0]
2:1
FBP
Defines which bytes are active in the first word of the DMA 00 DMA_DATA[31:0] FIRST_BYTE_POSIT 01 DMA_DATA[31:8] 10 DMA_DATA[31:16] 11 DMA_DATA[31:24] DMA_EN Enable insertion at next opportunity Table 20.15 Contents of register SDAV_DMA_EN_REG
DE
STREAM_EN_REGn
0xF00+ 4n Address: Access: Reset state:
Stream enable
8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
TransportDemuxBaseAddress + 0xF00 + 4n Read/write 0
Description
The stream enable registers enable and disable the streams. Each of the 32 streams has one register, and stream n is enabled by STREAM_EN_REGn which is at the address given by:
TransportDemuxBase + 0xF00 + 4n
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SE
DE
IIF
Bits 31:1 0
Field
CO
SE
Not used
D I F N
STREAM_EN
Signal name
L A I T N E
STi5500
Comment
Type
Reset
1 Enables the stream n 0 Disables the stream n
R/W
Table 20.16 Contents of register STREAM_EN_REGn
TIME_OUT_REG
0xF8C Address: Access: Reset state:
Time out
9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
TIME_OUT
TransportDemuxBaseAddress + 0xF8C Read/write 0x38
Description
Bits 31:6 5:0 Signal name Not used TIME_OUT AR threshold to reset the block Table 20.17 Contents of register TIME_OUT_REG R/W 0x38 Comment Type Reset
V_PTS_REG
Video time stamp

9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
V_PTS
Description
Bit 31:0 V_PTS Signal Name Actual video PTS (90 kHz) Table 20.18 Contents of register V_PTS_REG Comment R Type
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Address: Access:
L A I T 21 Teletext interface (Ttxt) registers N E D I F N O C

STi5500 TtxtAbort Teletext Abort
TtxtBaseAddress + 0x24 Write only Description
21 - Teletext interface (Ttxt) registers
The TtxtAbort register is write only. Any write to this address causes the teletext interface to abort the current operation. The state of the teletext output operation is reset, and the teletext data transfer is interrupted. The DMA engine is reset only after the current word read or write is complete.
TtxtAckOddEven
Address: Access:
Teletext Acknowledge odd or even
TtxtBaseAddress + 0x20 Write only
Description
This register acknowledges the odd/even toggle interrupt. Any write to the TtxtAckOddEven register clears the Odd and Even bits of the TtxtIntStatus register.
TtxtDmaAddress
Teletext DMA address

9 8 7 6 5 4 3 2 1 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DmaAddress
TtxtBaseAddress + 0x00 Read/write ?
Description The TtxtDmaAddress register is a 32-bit register, which specifies the base address in memory for the DMA transfer from memory.
Bit 31:0 Bit field DmaAddress Function The base address for DMA transfer of data from memory.
TtxtDmaCount
Teletext DMA count

9 8 7 6 5 4 3 2 1 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DmaCount
Description
The TtxtDmaCount register specifies the number of bytes to be transferred from memory during the DMA operation. A write to this register also starts the teletext output operation. This value must be: 46 bytes x number_of_teletext_lines_to_send
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TtxtIntEnable
0x1C
CO
D I F N
6
L A I T N E
5 4 3 2 1
STi5500
Teletext Interrupt enable

0
EvenEnable OddEnable
OutCompleteEn
TtxtBaseAddress + 0x1C Read/write ?
Description The TtxtIntEnable register allows masking of the TtxtIntStatus register.

Bit 2 1 0 Bit field EvenEnable OddEnable OutCompleteEn Function Enable even field interrupt. Enable odd field interrupt. Enable teletext output operation completed interrupt.
TtxtIntStatus
3 1 3 0 2 9 2 8 2 8 2 6 2 5 2 4
Teletext Interrupt status

2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 1 11 2 0 9 8 7 6 5 4 3 2 1 0
Even Odd
Out Complete
TtxtBaseAddress + 0x18 Read only ?
Description
The TtxtIntStatus register gives the current state of the teletext operations. If the appropriate bits in the interrupt enable register are set then interrupts can be driven by the state of this register. Bit 2 1 0 Bit field Even Odd OutComplete Function Current (video encoder) field is EVEN. Current (video encoder) field is ODD. Teletext output operation completed.
TtxtMode
Teletext Mode
8 7 6 5 4 3 2 1 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Odd Even
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Description The TtxtMode register sets the mode of the teletext interface. It specifies whether teletext data input memory is for odd or even fields.
Bit 1
CO
Bit field
D I F N
L A I T N E
Function 0 1
Specify odd or even fields of teletext data. Teletext data to or from memory is for EVEN fields. Teletext data to or from memory is for ODD fields.
OddEven
TtxtOutDelay
Teletext Output delay

9 8 7 6 5 4 3 2 1 0
31 30 29 28 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Delay
Description The TtxtOutDelay register is used to program the delay, in 27 MHz clock periods, from the rising edge of TtxtRequest to the first valid teletext data bit, i.e. TtxtData starting to transmit.
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L A I T 22 SDRAM block move (USD) registers N E D I F N O C

22 - SDRAM block move (USD) registers USD_BMS
1st cycle 2nd cycle Address: Access: Reset state:
STi5500
Block Move Size
USD_BMS[15:8] USD_BMS[7:0]
Description
This register holds the number of words to be moved in a block move operation. The second write to the register with USD_BMS non-zero enables (but does not launch) the block move mode. This register must be written before the associated USD_BRP. The register is reset by a hardware reset.
USD_BRP
7 1st cycle 2nd cycle 3rd cycle Address: Access: Reset state:
Memory Read Pointer

5 4 USD_BRP[18:16] USD_BRP[15:8] USD_BRP[7:0] 0
VideoBaseAddress + 0x0A Serial read/write Undefined
Description This register holds the source address of the block to be moved. USD_BRP[18:0] is an offset from the base of SDRAM in units of 16-bit words. It points to the base of the block to be copied. The address must be 64-bit aligned, so the two least significant bits are always zeros. When USD_BMS is non-zero, the third write to USD_BRP launches the block move process, taking into account the values in USD_BMS and USD_BWP. The pointer is reset by a hardware reset.
USD_BWP
Memory Write Pointer

5 4 USD_BWP[20:16] USD_BWP[15:8] USD_BWP[7:0] 0
VideoBaseAddress + 0x0B Serial read/write Undefined
Description When a block move is to be executed (i.e. USD_BMS is non-zero), this register holds the destination address where the block is to be copied. USD_BWP[18:0] defines an offset from the base of SDRAM in units of 16-bit words. It points to the base of the area to be written. The address must be 64-bit aligned, so the two least significant bits are always zeros. The pointer is reset by a hardware reset.
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L A I T 23 Video decoder (VID) registers N E D I F N O C

STi5500 VID_ABG
0x1C 0x1D Address: Access: Reset state: ABG[7:0]
23 - Video decoder (VID) registers
Start of audio bit buffer
0 ABG[13:8]
VideoBaseAddress + 0x1C and 0x1D Read/write 0
Description
The register holds the starting address of the audio bitstream buffer, defined in units of 2 Kbits. If the audio bit buffer starts at address 0, then this register does not need to be set up, since its reset state is 0. A soft reset must be done immediately after the loading of this register in order for the value to be taken into account. In other words it must only be changed before the first compressed data of a new sequence is input, and never during the decoding of a sequence.
VID_ABL
7 0x1E 0x1F Address: Access: Reset state:
Audio Bit Buffer Level

0 ABL[13:8] ABL[7:0]
VideoBaseAddress + 0x1E and 0x1F Read only 0
Description This register holds the current level of occupation of the audio bit buffer, defined in units of 2 Kbits. It can be read at any time for the monitoring of the audio bit buffer level. When VID_ABL is greater than or equal to the value held in the VID_ABT register, the status bit VID_STA.ABF (audio bit buffer full) becomes set. When VID_ABL is zero, the status bit VID_STA.ABE (audio bit buffer empty) becomes set.
VID_ABS
Audio Bit Buffer Stop

0 ABS[13:8] ABS[7:0]
VideoBaseAddress + 0x20 and 0x21 Read/write 0
Description
This register holds the address of the top of the audio bit buffer, defined in units of 2 Kbits. The space allocated to the audio bit buffer starts at the address defined by the VID_ABG register, or, by default, 0. The end address of the audio bit buffer is: (128 x ABS) + 127
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VID_ABS must only be changed before the first compressed data of a new sequence is input, and never during the decoding of a sequence.
VID_ABT
0x22 0x23
CO
D I F N
7
L A I T N E
STi5500
Audio Bit Buffer Threshold

0 ABT [13:8] ABT [7:0]
VideoBaseAddress + 0x22 and 0x23 Read/write 0 Edge Triggered
Description This register holds the level of occupancy of the audio bit buffer, in units of 2 Kbits, which when reached causes the status bit VID_STA.ABF to become set. If the bit CFG_CCF.PBO is set, then transfer of data to the audio bit buffer is prevented if the bit buffer level is at or above the level defined in the VID_ABT register. If VID_ABT is set to a value equal to the top of the bit buffer, then this automatic mechanism will ensure that overflow never occurs.
VID_BFC
Backward Chroma Pointer

0 BFC [13:8] BFC [7:0]
VideoBaseAddress + 0x5E and 0x5F Read/write 0 DSYNC
Description
This register holds the start address of the chrominance buffer of the backward prediction frame picture, defined in units of 256 bytes.
VID_BFP
Backward Frame Pointer

0 BFP [13:8] BFP [7:0]
VideoBaseAddress + 0x12 and 0x13 Read/write 0 DSYNC
Description This register holds the start address of the luminance buffer of the backward prediction frame picture, defined in units of 256 bytes.
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STi5500 VID_CDcount
1st cycle
2nd cycle 3rd cycle
CO
D I F N
7
Bit Buffer Input Counter

0 CDcount [23:16] CDcount [15:8] CDcount [7:0]
L A I T N E
VideoBaseAddress + 0x67 Serial read only 0
Description These three registers are accessed serially. They hold the number of bytes input to the bit buffer. The byte pointer is reset by a hardware reset, a global soft reset or a video soft reset.
VID_CSO
7 0x6C Address: Access: Reset state: Synchronization:
SRC Chrominance Offset

0 CSO[7:0]
VideoBaseAddress + 0x6C Read/write 0 VSYNC
Description This register is set up with a value calculated from the fractional part of the pan vector. If no pan vector is defined, this register can be left in its reset (default) state. The method of calculation of the CSO value is given in the VID_PAN register description.
VID_CSR
7 0x6B Address: Access: Reset state: Synchronization:
SRC Chrominance Resolution

0 LSR[7:0]
VideoBaseAddress + 0x6D Read/write 0 VSYNC
Description This register holds the upsampling factor of the luminance SRC (sample rate converter). The upsampling factor is equal to 256/CSR. Table 23.7 gives some examples of upsampling factors, where in each case the displayed picture has a nominal width of 720 pels. Also shown are the numbers of valid pels generated, N, calculated as shown in the STi5500 datasheet. Displayed picture widths other than 720 are supported.
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Decoded Picture Width
CO
D I F N
640 640 544 544 480 480 352 352 704 704
L A I T N E
228 227 193 192 170 169 125 124 250 249
STi5500
CSR
N 715 718 717 721 717 722 713 719 717 720
Table 23.1 Example upsampling factors
VID_CTL
7 0x02 Address: Access: Synchronization: ERU
Decoding Control
6 ERS 5 4 3 2 PRS 1 SRS 0 EDC
VideoBaseAddress + 0x02 Read/write Edge triggered
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Description
Field ERU ERS
Bit 7 6 5
CO
D I F N
L A I T N E
Description
Enable pipeline reset on picture decode error. When this bit is set, a pipeline reset is automatically generated in case of Picture Decode Error (less than DFS macroblocks decoded). Enable pipeline reset on severe error. When this bit is set, a pipeline reset is automatically generated in case of Severe Error (more than DFS macroblocks decoded).
Reserved. Write 0. Reserved. Write 0. Pipeline reset. In order to generate a pipeline reset, this bit must be kept set for a duration of at least 4 SDRAM clock cycles (40 ns with a 100 MHz SDRAM clock). Soft reset. In order to generate a soft reset, this bit must be kept set for a duration of at least 54 SDRAM clock cycles (540 ns with a 100 MHz primary clock). Enable decoding. This bit must be set to allow decoding. Table 23.2 Bit fields in register VID_CTL
4:3 PRS SRS EDC 2 1 0
VID_DCF
Display Configuration
6 5 BLL PXD EVD 4 BFL EOS 3 FNF DSR 2 FLY 1 ORF LFB CFB 0
VideoBaseAddress + 0x74 and 0x75 Read/write 0 VSYNC
Description
Field BLL BFL Bit 13 12 Description Blank Last Line. If this bit is set, the last active line of a picture is blanked. (Used in letter box format display). Blank First Line. If this bit is set the first active line of a picture is blanked. (Used in letter box format display). Frame not Field. This bit is only used during on-the-fly decoding. The bit must be set if a frame picture is going to be displayed, or reset if field picture are to be decoded on-the-fly. For classical decoding (field or frame) the bit is always 1. On The Fly. When this bit is set, the current picture is displayed directly from the pipeline. Otherwise, it is loaded from the external memory. One Row per Frame. This bit is only active when bit VID_DCF.FNF is set. It defines the number of rows to be stored in the block to row RAM during a frame picture display. If it is set, one field macroblock line is stored (8 video lines). Otherwise, two field macroblock lines are stored (16 video lines). This bit is for test purposes. This bit must be reset for normal operation. Set to 1. Table 23.3 Fields of register VID_DCF
FNF
11
FLY
10
ORF
PXD
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Field EVD Bit 5
EOS
CO
4 3 1
Enable video display. When this bit is reset, the video output has a constant value of Y=16, CB=CR=128. OSD is still displayed. Enable OSD. When this bit is set, the on-screen display (OSD) bitmap defined in the top and bottom field OSD buffers is displayed over the picture. Disable SRC. When this bit is set, both luminance and chrominance SRCs (sample rate converters) are disabled. In this case no horizontal filtering can occur, as would be required when the horizontal resolution of the decoded picture is equal to the horizontal resolution of the display.
D I F N
L A I T N E
STi5500
Description
DSR
LFB
0 AND bit CFB = 0: field based filtering mode 1: frame based luma filtering mode see datasheet Chapter Display, section Block-to-row converter for detailed information. 0 AND bit LFB = 0: field based filtering mode 1: frame based chroma filtering mode see datasheet Chapter Display, section Block-to-row converter for detailed information. Table 23.3 Fields of register VID_DCF
CFB
VID_DFC
Displayed Chroma Frame Pointer

0 VID_DFC[13:8] VID_DFC[7:0]
VideoBaseAddress + 0x58 and 0x59 Read/write 0 VSYNC
Description
This register holds the start address, defined in units of 256 bytes, of the chroma frame which is currently being displayed. When a new value is written this is used at the start of the next field. When VID_DFC is set to same value as VID_RFC (i.e. the decoder is writing the reconstructed picture into the buffer which is being displayed), bit VID_TIS.OVW must be set.
VID_DFP
7 0x0C 0x0D Address: Access: Reset state: Synchronization:
Displayed Luma Frame Pointer

0 VID_DFP[13:8] VID_DFP[7:0]
VideoBaseAddress + 0x0C and 0x0D Read/write 0 VSYNC
Description This register holds the start address, defined in units of 256 bytes, of the luma frame which is currently being displayed. When a new value is written this is used at the start of the next field. When VID_DFP is set to the same value as VID_RFP (i.e. the decoder is writing the reconstructed picture into the buffer which is being displayed), bit VID_TIS.OVW must be set.
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STi5500 VID_DFS
1st cycle
2nd cycle
CO
D I F N
7 6
Decoded Frame Size

5
L A I T N E
DFS[7:0]
0 DFS[13:8]
VideoBaseAddress + 0x24 Serial read/write 0 DSYNC
Description
The circularity is reset by a software reset. Field DFS Bits 13:0 Description This register field is set up with a value equal to the number of macroblocks in the decoded picture. This is derived from the horizontal_size and vertical_size values transmitted in the sequence header. Table 23.4 Bit fields in register VID_DFS
VID_DFW
Decoded Frame Width

0 DFW[7:0]
VideoBaseAddress + 0x25 Read/write 0 DSYNC
Description
This register is set up with the width in macroblocks of the decoded picture. This is derived from the horizontal_size value transmitted in the sequence header.
VID_END
7 0x7C Address: Access: Reset state: Synchronization:
Little endian - big endian conversion

6 5 4 reserved 3 2 1 0 END
VideoBaseAddress + 0x7C Read/write 0 None
Description This register contains only the bit END, When set to 1, there is a hardware byte-swapping on the SMI which converts data from little endian to big endian formats (ST20 -> SDRAM) and vice versa (SDRAM -> ST20). This mode affects only the data which is written by the ST20 (little endian) into SDRAM memory and which are read by the MPEG decoder (big endian). It is used for OSD transfer.
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23 - Video decoder (VID) registers VID_FFC

0x5C 0x5D
CO
D I F N
7
Forward Chroma Frame Pointer

0 FFC[13:8] FFC[7:0]
L A I T N E
STi5500
VideoBaseAddress + 0x5C and 0x5D Read/write 0 DSYNC
Description This register holds the start address of the forward prediction chroma frame picture buffer, defined in units of 256 bytes.
VID_FFP
Forward Luma Frame Pointer

0 FFP[13:8] FFP[7:0]
Description
This register holds the start address of the forward prediction luma frame picture buffer, defined in units of 256 bytes.
VID_FRZ
Freeze display
0 FRZ
Description This register is used to freeze the display. When bit 0 is set, the current decoded field is displayed continuously on both fields until this bit is reset by the software. The effect of this bit is to freeze the current polarity of the internal B/notT signal. This bit is also used to control three-to-two pull-down operation.
VID_HDF
7 1st cycle 2nd cycle Address: Access:
Header Data FIFO

0 HDF[15:8] HDF[7:0]
VideoBaseAddress + 0x66 Serial read only
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STi5500
Reset state: Undefined
Description When the start code detector has found a start code, the header data FIFO must be read in order to identify the start code and if required to obtain the header data. The start code identification procedure is described in the STi5500 datasheet. Before reading the header FIFO, status bit VID_STA.HFE should be checked to ensure that it is not empty. If bit VID_STA.HFF is set then the header FIFO contains at least 66 bytes of data. As the start code detection is managed with 16-bit words, two successive reads are needed to access the whole 16-bit word; you must always perform an even number of reads before start code search restart (by software or with DSYNC signal). The byte pointer is reset by a hardware reset, a global soft reset or a video reset.
CO
D I F N
L A I T N E
VID_HDS
7 Read cycle Write cycle Address: Access: Reset state: Synchronization:
Header Search
3 SCM SOS QMI HDS 2 1 0
VideoBaseAddress + 0x69 Read only bit SCM, write only HDS, QMI and SOS. 0 None
Description This register controls the header search when it is written to, and returns the location of the start code when read.
Field SCM Bit 3 Description Start Code on MSB. This bit indicates in which byte the start code is located. If this bit is set then VID_HDF[15:8] contains the start code; otherwise VID_HDF[7:0] contains the start code. Table 23.5 Fields of register VID_HDS when reading Field SOS Bit 2 Description Stop on First Slice. This bit when set allows the start code detector to stop on the first slice start code of a picture (0x00000101). To allow mismatches, this bit must be used in conjunction with VID_HDS.SCM. This bit is used to control access to the inverse quantize tables. QMI 1 1 0 select the intra table select the non-intra table.
For example, to write a new intra table, write VID_HDS.QMI = 1 then write 64 weights to VID_QMW. HDS 0 Writing a 1 to this bit starts a header search. Completion of the header search is indicated by the setting of bit VID_STA.SCH. Table 23.6 Fields of register VID_HDS when writing
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23 - Video decoder (VID) registers VID_ITM

0x3C 0x60 0x61
CO
D I F N
7 6 NDP PDE PSD
Interrupt Mask
5
L A I T N E
4 BMI VSB HFF BBE
STi5500
3 ABF PNC BBF
2 SFF ERC HFE
1 AFF PID CFF
0 ABE RPID SCH
ERR SER VST
VideoBaseAddress + 0x3C, 0x60 and 0x61 Read/write 0 (all interrupts disabled) None
Description Any bit set in this register will enable the corresponding interrupt. An interrupt is generated whenever a bit in the VID_STA register changes from 0 to 1 and the corresponding mask bit is set.
VID_ITS
7 0x3D 0x62 0x63 NDP PDE PSD
Interrupt Status
6 ERR SER VST BMI VSB HFF BBE 5 4 3 ABF PNC BBF 2 SFF ERC HFE 1 AFF PID CFF 0 ABE RPID SCH
Address: VideoBaseAddress + 0x3D, 0x62 and 0x63 Access: Read only Reset state: 0 After the clocks have been enabled, the state changes to be the same as that of VID_STA.
Description
When a bit in the VID_STA register changes from 0 to 1, the corresponding bit in the VID_ITS register is set, irrespective of the state of VID_ITM. If the corresponding bit of VID_ITM is set, the interrupt is asserted. Reading the most significant byte of VID_ITS clears it, leaving IRQ in its de-asserted (high) state. See the STi5500 datasheet for more information on interrupt handling.
VID_LDP
7 0x3F Address: Access: Reset state: Synchronization:
Load Pointer
0 LDP
VideoBaseAddress + 0x3F Read/write 0 None
Description
When this bit is set, the current start code detector pointer is stored in an internal register. When a PSC hit occurs, the current start code detector pointer has to be stored for further use by the VLD (if a B frame is to be processed on the fly). This bit has to be set then reset before the PSD interrupt corresponding to the picture which has to be decoded on the fly (i.e. during the SCH interrupt).
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STi5500 VID_LSO
0x6A
CO
D I F N
7
SRC Luminance Offset

0 LSO[7:0]
L A I T N E
VideoBaseAddress + 0x6A Read/write 0 VSYNC
Description This register is set up with a value calculated from the fractional part of the pan vector. If no pan vector is defined, this register can be left in its reset (default) state. The method of calculation of the LSO value is given in the VID_PAN register description.
VID_LSR
7 0x6B Address: Access: Reset state: Synchronization:
SRC Luma Resolution

0 LSR[7:0]
VideoBaseAddress + 0x6B Read/write 0 VSYNC
Description This register holds the upsampling factor of the luminance SRC (sample rate converter). The upsampling factor is equal to 256/LSR. Table 23.7 gives some examples of upsampling factors, where in each case the displayed picture has a nominal width of 720 pels. Also shown are the numbers of valid pels generated, N, calculated as shown in the STi5500 datasheet. Displayed picture widths other than 720 are supported.
Decoded Picture Width 640 640 544 544 480 480 352 352 704 704 LSR 228 227 193 192 170 169 125 124 250 249 Table 23.7 Example upsampling factors N 715 718 717 721 717 722 713 719 717 720
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23 - Video decoder (VID) registers VID_NWM

0x7B
CO
D I F N
7 6
Not writable register mode

5 4 3 2 1 0 NWM reserved
L A I T N E
STi5500
VideoBaseAddress + 0x7B Read/write 0 None
Description This register contains only the bit NWM, which, when set to 1, puts the registers CFG_MCF, CFG_CCF and CFG_DRC into a non-writable mode. The bit can be reset either by writing 0 or by a software reset.
VID_OBP
7 1st cycle 2nd cycle Address: Access: Reset state: Synchronization:
OSD Bottom Field Pointer

5 OBP[13:8] OBP[7:0] 0
VideoBaseAddress + 0x2B Serial read/write 0 VSYNC bottom
Description This register is written or read in two cycles: first cycle: OBP[13:8] second cycle: OBP[7:0] The circularity is reset by a hardware reset or a bottom field VSYNC. The register holds the start address, in units of 256 bytes of the current OSD specification buffer for the bottom field. This specification will be decoded during bottom fields when OSD is enabled.
VID_OSD
On-screen Display Configuration

6 OAM OAD[5:0] 0
VideoBaseAddress + 0x3E Read/write 0
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Description .
Field OAM
CO
Bits 6
D I F N
L A I T N E
Description
OSD active signal mode. When this bit is set, the OSD active signal is an input. When it is reset, the OSD active signal is an output. The OSD active signal must never be driven when VID_CTL.EVI=1 and VID_OSD.OAM=0.
OAD
5:0
OSD active signal delay. These bits are used to define the delay of the OSD active signal corresponding to output OSD pixels. Table 23.8 Bit fields of register VID_OSD
Comment: There is no such bit as VID_CTL.EVI. VID_OTP

7 1st cycle 2nd cycle Address: Access: Reset state: Synchronization: OTP[7:0]
OSD Top Field Pointer

5 OTP[13:8] 0
VideoBaseAddress + 0x2A Serial read/write 0 VSYNC top
Description
This register is written or read in two cycles: first cycle: OTP[13:8] second cycle: OTP[7:0] The circularity is reset by a hardware reset or a top VSYNC. The register holds the start address, in units of 256 bytes, of the current OSD specification buffer for the top field. This specification will be decoded during top fields when OSD is enabled.
VID_PAN
7 0x2C 0x2D Address: Access: Reset state: Synchronization:
Pan/Scan Horizontal Vector Integer Part

2 PAN[10:8] PAN[7:0] 0
VideoBaseAddress + 0x2C and 0x2D Read/write 0 VSYNC
Description
This register is set up with the integer part of the horizontal pan/scan vector. The horizontal pan/scan vector defines, in the decoded picture, the location of the first displayed luminance sample relative to the first luminance sample in the line. The VID_LSO and VID_CSO registers are set up with the fractional part of the horizontal pan/scan vector, as follows: PSV = horizontal pan/scan vector where x indicates the integer part of x.
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VID_LSO = 256 x (horizontal pan/scan vector - PSV) VID_CSO = VID_LSO / 2 (+ 1 if PSV is odd)
VID_PFH
0x04
CO
D I F N
7
L A I T N E
4 BFH[3:0] 3 FFH[3:0]
STi5500
Picture F-parameters Horizontal

0
Description
This register contains parameters of the picture to be decoded. These parameters are extracted from the bit stream. Field BFH 6:4 3 FFH 2:0 Bits 7 MPEG-1 MPEG-2
Set to full_pel_backward_vector of the picture headSet to backward_horizontal_f_code of er. the picture coding extension. Set to backward_f_code of the picture header. Set to full_pel_forward_vector of the picture header. Set to forward_f_code of the picture header. Set to forward_horizontal_f_code of the picture coding extension.
Table 23.9 Bit fields of register VID_PFH
VID_PFV
Picture F-parameters Vertical

4 BFV[3:0] 3 FFV[3:0] 0
Description
This register contains parameters of the picture to be decoded. These parameters are extracted from the bitstream. In MPEG-1 mode (i.e. when VID_PPR2.MP2 is reset), VID_PFV is not used. Field BFV FFV Bits 7:4 3:0 Description The backward_vertical_f_code of the picture coding extension. The forward_vertical_f_code of the picture coding extension. Table 23.10 Bit fields of register VID_PFV
VID_PPR1
7 0x06 Address:
Picture Parameters 1
6 OTF 5 PCT[1:0] 4 3 DCP[1:0] 2 1 PST[1:0] 0
VideoBaseAddress + 0x06
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STi5500
Access: Reset state: Synchronization: Read/write 0 DSYNC
Description
This register contains parameters of the picture to be decoded. These parameters are extracted from the bit stream. In MPEG-1 mode (i.e. when VID_PPR2.MP2 is reset), only PCT has to be set; the other bits must be reset. Field OTF PCT DCP Bits 6 5:4 3:2 Description When set this bit directs the decoded data in the block-to-row memory to be displayed directly. The picture data is not reconstructed in memory. Set to the two least significant bits of picture_coding_type in the picture header. Set equal to intra_dc_precision of the picture coding extension. The value 11, defining a precision of 3 bits, is not allowed. Set to the picture_structure bits of the MPEG-2 picture coding extension. PST 1:0 00 01 10 11 Frame picture. This value is illegal in the MPEG-2 variable. Top field. Bottom field. Frame picture. Table 23.11 Bit fields of register VID_PPR1
CO
D I F N
L A I T N E
VID_PPR2
Picture Parameters 2
6 MP2 5 TFF 4 FRM 3 CMV 2 QST 1 IVF 0 AZZ
Description This register contains parameters of the picture to be decoded. These parameters are extracted from the bitstream. In MPEG-1 mode, all bits must be reset to 0.
Field MP2 TFF FRM CMV QST IVF AZZ Bits 6 5 4 3 2 1 0 Description
MPEG-2 mode. When this bit is set, the STi5500 expects an MPEG-2 video bitstream. If it is reset, then an MPEG-1 bitstream is expected.
This bit is set equal to the top_field_first bit of the MPEG-2 picture coding extension. This bit is set equal to the frame_pred_frame_dct bit of the picture coding extension. This bit is set equal to the concealment_motion_vectors bit of the MPEG-2 picture coding extension. It indicates that motion vectors are coded for intra macroblocks. This bit is set equal to the q_scale_type bit of the picture coding extension. This bit is set equal to the intra_vlc_format bit of the picture coding extension. This bit is set equal to the alternate_scan bit of the picture coding extension. Table 23.12 Bit fields of register VID_PPR2
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23 - Video decoder (VID) registers VID_PTH

0x2E 0x2F
CO
D I F N
7
Panic threshold
5 FPAN
L A I T N E
4 PEN PTH[7:0]
STi5500
3 NFW
2 PTH[10:8]
VideoBaseAddress + 0x2E and 0x2F Read/write 0 VSYNC
Description
The panic threshold defines a block-to-row DRAM fullness level. In the block-to-row converter, there are two counters indicating the number of luma and chroma words stored. If the luma counter pointer is less than PTH or the chroma counter pointer is less than PTH divided by 2, a PANIC flag is set. The panic threshold is programmed in units of DRAM cells. Field FPAN PEN NFW PTH 13 12 11 10:0 Bits Description Force Panic Mode. This bit, when set, forces panic mode while decoding. For test purposes only. Panic mode enable. When set this bit allows the decoding to set the panic flag and enter the panic mode. Near Forward. This bit allows the user to select which prediction direction will be retained for bidirectional macroblocks in panic mode. Forward if set, backward otherwise. Panic mode threshold. Table 23.13 Bit fields of register VID_PTH
VID_QMW
Quantization Matrix Data

0 QMW[7:0]
VideoBaseAddress + 0x76 Write only Undefined None
Description This address is used to load the quantization coefficients in the order in which they appear in the bit stream, i.e. zig-zag order. The bit VID_HDS.QMI defines which matrix (Intra or Inter) is written. For example, to write a new intra table, write VID_HDS.QMI = 1, and then write 64 weights to VID_QMW.
VID_REV
STi5500 Revision
0 REV[7:0]
VideoBaseAddress + 0x78 Read only
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Description This register holds the version number of the device. The contents of this register match the marking on the package.
VID_RFC
0x5A 0x5B
CO
D I F N
7
L A I T N E
5
Reconstructed Chroma Frame Pointer

0 RFC[13:8] RFC[7:0]
VideoBaseAddress + 0x5A and 0x5B Read/write 0 DSYNC
Description
This register holds the start address of the reconstructed (decoded) chroma frame picture buffer, defined in units of 256 bytes.
VID_RFP
Reconstructed Frame Pointer

5 RFP[13:8] RFP[7:0] 0
VideoBaseAddress + 0x0E and 0x0F Read/write 0 DSYNC
Description
This register holds the start address of the reconstructed (decoded) luma frame picture buffer, defined in units of 256 bytes.
VID_RSTA
7 0x7A Address: Access: Reset state: Synchronization:
Audio reset
6 5 4 reserved 3 2 1 0 RSTA
VideoBaseAddress + 0x7A Read/write 0 None
Description
This register contains only the bit RSTA, which, when set to 1, flushes the audio bit buffer and software resets the audio decoder (the video is not affected). In order to generate an audio software reset, this bit must be kept set for a duration of at least 54 SDRAM clock cycles.
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23 - Video decoder (VID) registers VID_RSTV

0x39
CO
D I F N
7 6
Video reset
5
L A I T N E
4 reserved
STi5500
0 RSTV
Description This register contains only the bit RSTV, which, when set to 1, flushes the video bit buffer and software resets the video decoder (the audio is not affected). In order to generate a video software reset, this bit must be kept set for a duration of at least 54 SDRAM clock cycles.
VID_SCDcount
Bit Buffer Output Counter

0 SCDcount [23:16] SCDcount [15:8] SCDcount [7:0]
VideoBaseAddress + 0x68 Serial read only 0
Description These three registers are accessed serially. This register holds the number of 16-bit words output from the bit buffer into the Start Code Detector. The byte pointer is reset by a hardware reset, a global soft reset or a video reset.
VID_SCN
7 0x29 Address: Access: Reset state: Synchronization: reservsd
SCAN vector
6 5 4 3 2 1 0 VID_SCN[5:0]
VideoBaseAddress + 0x29
None
Description This register holds the scan vector in units of macroblock rows.
VID_SPB
7 0x50 0x51 Address:
Sub-picture Buffer Begin

2 SPB[10:8] SPB[7:0] 0
VideoBaseAddress + 0x50 and 0x51
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STi5500
Access: Reset state: Synchronization: Read/write 0 none
Description
This register holds the start address of the sub-picture circular buffer and is programmed in units of 64 bytes. The buffer should be aligned on a 1 Kbyte boundary.
CO
D I F N
7
L A I T N E
VID_SPE
0x52 0x53 Address: Access: Reset state: Synchronization:
Sub-picture Buffer End

2 SPE[10:8] SPE[7:0] 0
VideoBaseAddress + 0x52 and 0x53 Read/write 0 none
Description This register holds the stop address of the sub-picture circular buffer and is programmed in units of 64 bytes. The buffer should be aligned on a 1 Kbyte boundary.
VID_SPRead
7 1st cycle 2nd cycle 3rd cycle Address: Access: Reset state: Synchronization:
SubPicture Read Pointer

2 SPR[18:16] SPR[15:8] SPR[7:0] 0
VideoBaseAddress + 0x4E Serial read/write 0 VSYNC
Description These three registers are accessed serially. The byte pointer is reset by a hardware reset. This is the absolute address in the memory. This register is used when the software needs to set the read address of the sub-picture decoder and is programmed in units of 64-bit words. This value is taken into account after a VSYNC.
VID_SPWrite
SubPicture Write Pointer

2 SPW[18:16] SPW[15:8] SPW[7:0] 0
VideoBaseAddress + 0x4F Serial read/write 0
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Synchronization: None
Description These three registers are accessed serially. The byte pointer is reset by a hardware reset. This is the absolute address in the memory. This register is used when the software needs to set the write address of the sub-picture decoder and is programmed in units of 64-bit words. It is recommended to stop loading sub-picture data to the sub-picture decoder FIFO before changing the value of this register.
CO
D I F N
7 6
L A I T N E
STi5500
VID_STA
0x3B 0x64 0x65 NDP PDE PSD
Status
5 4 3 ABF BMI VSB HFF BBE PNC BBF 2 SFF ERC HFE 1 AFF PID BFF 0 ABE RPID SCH ERR SER VST
Address: VideoBaseAddress + 0x3B (VID_STA1), 0x64 (VID_STA2) and 0x65 (VID_STA3) Access: Read only Reset state: See Table 23.14 This register contains a set of bits which represent the status of the decoder at any instant. Any change from 0 to 1 of any of these bits sets the corresponding bit of the VID_ITS register, and can thus potentially cause an interrupt. The status vector is sampled internally at the start of the read cycle accessing the most significant byte of VID_STA (address 0x3B). VST, VSB and PSD are pulses and are unlikely ever to be read as a 1. The status bits are described in Table 23.14. The reset column shows the state after clocks have been enabled. Field NDP ERR SFF AFF ABF ABE Bit 23 22 18 17 19 16 New discarded packet. Inconsistency error in PES parser. Sub-picture Compressed Data (bitstream) FIFO full. This bit is set when the sub-picture CD FIFO is full. Audio Compressed Data (bitstream) FIFO full. This bit is set when the audio CD FIFO is full. Audio bit-buffer full. Audio bit-buffer empty. This bit is set when the audio bit buffer contains no data. Picture Decoding Error or underflow error. This bit is set when less than the programmed number of macroblocks (defined by DFS) have been decoded, either due to a data or a programming error. Decoding is halted automatically when this error condition is detected. This bit is reset by all three types of reset. Severe Error or overflow error. This bit is set when more than the programmed number of macroblocks (defined by DFS) have been decoded, either due to a data or a programming error. Decoding is halted automatically when this error condition is detected. This bit is reset by all three types of reset. Block Move Idle. This bit is set when a block move operation has terminated. It is automatically reset at the start of a block move. Header FIFO Full. This bit is set when the header FIFO contains at least 66 bytes. Panic. This bit is set when decoding is in late compare to display. Table 23.14 VID_STA register fields 0 0 Description Reset 0 0
PDE
15
SER
14
BMI HFF PNC
13 12 11
1 0 0
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Field ERC Bit 10
PID
CO
9 8 7 6 5 4 3 2 1
D I F N
Error Concealment. This bit is set when an error is detected in the bit stream and the mechanism of error concealment is active. Pipeline Idle. This bit is set when the STi5500 is not in the course of decoding a picture, i.e. when the pipeline is inactive. It becomes low when the decoding of a picture starts and high when picture decoding is complete. Real Pipeline Idle. As bit PID above but without the condition "VLD found a new PSC". After clocks have been enabled, the state changes. Pipeline Starting to Decode. This bit is set for a short period at the instant the pipeline starts decoding a picture. VSYNC Top. This bit is set for a short time at the beginning of the top field, corresponding to the falling edge of the B/T signal. VSYNC Bottom. This bit is set for a short time at the beginning of the bottom field, corresponding to the rising edge of the B/T signal. Video bit buffer empty. This bit is set when the bit buffer contains no data. Video bit buffer full. This bit is set when the bit buffer level (= VID_VBL) is greater than or equal to the value loaded into the VID_VBT register. Header FIFO Empty. This bit is set when the header FIFO is empty. Video Compressed Data (bit stream) FIFO Full. This bit is set when the video CD FIFO is full. This bit is equivalent to the signal CDREQ. Start Code Hit. This bit is set whenever the first 16-bit word available in the header FIFO contains one of the start codes recognized (see the STi5500 datasheet). While data is being read from the header FIFO, this bit can be tested to determine whether the next word contains a start code. Table 23.14 VID_STA register fields
L A I T N E

Reset 0
Description
RPID PSD VST VSB BBE BBF HFE BFF
1 0 0 0 1 1 1 0
SCH
VID_TIS
Task Instruction
6 5 SKP[1:0] 4 3 OVW 2 FIS 1 RPT 0 EXE
VideoBaseAddress + 0x03 Write only 0 VSYNC
Description
This register contains 5 bitfields of the decoding task instruction.
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Field
Bits
CO
SKP OVW 3
D I F N
00 01 10 11
L A I T N E
STi5500
Description
These bits are part of the instruction register, and are thus synchronized with VSYNC. They define the skipping of one or two pictures. If skipping is required, then these bits must be set up as part of the instruction for the picture which will be decoded immediately after the skipped pictures. No skip (default) Skip one picture, decode next Skip two pictures, decode next Skip one picture then stop
5:4
This bit must be set when the displayed picture and the reconstructed picture share the same buffer (i.e. VID_DFP = VID_RFP). It enables the overwrite mode which ensures that the reconstructed picture does not overwrite data which has not yet been displayed. Force instruction: if this bit is set, the task described by this register will be launch immediately. This bit is reset after its action. Its effect is the same as the effect of a VSYNC. When this bit is set, the task duration is two VSYNC periods. When the frame display rate is equal to the picture decoding rate, RPT will generally always be high. In case of a task launched by VID_TIS.FIS, RPT is not taken in account. When this bit is not set, no decoding or skipping task is executed for one or two VSYNC periods, depending on the state of VID_TIS.RPT. If set, the next task (decoding or skipping) is executed. EXE is internally cleared when the task starts its execution, i.e. setting this bit activates only one execution. Table 23.15 Fields of register VID_TIS
FIS
RPT
EXE
VID_TRF
Temporal Reference
3 DC2 TRF[7:0] 2 DTR 1 TRF[9:8] 0
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Description This register contain extensions of the decoding task instruction. It is used only when decoding a B frame on the fly.
Field
DC2
CO
D I F N
Bits
L A I T N E
Description
11
Redecode same B Frame twice. When this bit is set it signals the VLD that the next picture will have to be decoded twice. This bit is used when decoding a B Frame on the fly. It has to be set by the user before the first PSD interrupt corresponding to a B frame and reset on the according PSD interrupt. Disable temporal reference comparision. This bit is used only when decoding a B frame on the fly. On every B frame redecode the VLD uses the temporal reference field VID_TRF.TRF[9:0] to resynchronize on the previously decoded picture. When this bit is set this comparision mechanism is disabled. Temporal reference. This field holds the temporal reference of the current decoded B frame. On every B frame redecode the VLD uses the temporal reference field TRF to resynchronize on the previously decoded picture. TRF is used only when bit DTR is reset.
Table 23.16 Fields of register VID_TRF
DTR
10
TRF
9:0
VID_VBG
Start of Video Bit Buffer

5 VBG[13:8] VBG[7:0] 0
VideoBaseAddress + 0x14 and 0x15 Read/write 0 None
Description
The register holds the starting address of the video bit buffer, defined in units of 2 Kbits. If the video bit buffer starts at address 0, then this register does not need to be set up, since its reset state is 0. A soft reset must be done immediately after the loading of this register in order for the value to be taken into account. In other words it must only be changed before the first compressed data of a new sequence is input, and never during the decoding of a sequence.
VID_VBL
Video Bit Buffer Level

5 VBL[13:8] VBL[7:0] 0
VideoBaseAddress + 0x16 and 0x17 Read only 0
Description This register holds the current level of occupation of the video bit buffer, defined in units of 2 Kbits. It can be read at any time for the monitoring of the video bit buffer level. When VID_VBL is greater than or equal to the value held in the VID_VBT register, the status bit VID_STA.BBF (video bit buffer full) becomes set. When VID_VBL is zero, the status bit VID_STA.BBE (video bit buffer empty) becomes set.
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23 - Video decoder (VID) registers VID_VBS

0x18 0x19
CO
D I F N
7
Video Bit Buffer Stop

5
L A I T N E
VBS[13:8] VBS[7:0]
STi5500
VideoBaseAddress + 0x18 and 0x19 Read/write 0 None
Description
This register holds the address of the top of the video bit buffer, defined in units of 2 Kbits. The space allocated to the video bit buffer starts at the address defined by the VID_VBG register, or, by default, 0. The end address of the video bit buffer is: (32 x VID_VBS) + 31 VID_VBS must only be changed before the first compressed data of a new sequence is input, and never during the decoding of a sequence.
VID_VBT
7 0x1A 0x1B Address: Access: Reset state: Synchronization:
Video Bit Buffer Threshold

5 VBT[13:8] VBT[7:0] 0
VideoBaseAddress + 0x1A and 0x1B Read/write 0 Edge triggered
Description This register holds the level of occupancy of the video bit buffer, in units of 2 Kbits, which when reached causes the status bit VID_STA.BBF to become set, i.e. if VID_VBL VID_VBT, then VID_STA.BBF is set. If the bit CFG_CCF.PBO is set, then transfer of data from the video CD FIFO to the bit buffer is prevented if the bit buffer level is at or above the level defined in the VID_VBT register. If VID_VBT is set to a value equal to the top of the bit buffer, then this automatic mechanism will ensure that overflow never occurs.
VID_VFC
Chroma vertical filter

5 reserved 0x55 Read/write 0 VSYNC 4 VID_VFC[4:0] 0
Description
This register defines the vertical filter mode used for the chroma data. The uses of the vertical filtering modes are described in the Display chapter of the datasheet.
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STi5500 VID_VFL
0x54
CO
D I F N
7 0x54 Read/write 0 VSYNC
Luma vertical filter

5
L A I T N E
4
0 VID_VFL[4:0]
reserved
Description
This register defines the vertical filter mode used for the luma data. The uses of the vertical filtering modes are described in the Display chapter of the datasheet.
VID_XDO
Display X Offset
1 XDO[9:8] XDO[7:0] 0
VideoBaseAddress + 0x70 to 0x71 Read/write 0 VSYNC
Description
VID_XDO is set up with a number defining the beginning of the left-hand border of the display. This offset is measured from the active (first) edge of HSYNC and is specified in units of PIXCLK cycles. The horizontal offset, XDO, is given by:
XDO = VID_XDO + 10
The offset, XDO cannot be less than 153 video decoder clock cycles.
VID_XDS
Display X End
1 XDS[9:8] XDS[7:0] 0
VideoBaseAddress + 0x72 to 0x73 Read/write 0 VSYNC
Description
This register is set up with a number defining the right-hand boundary of the picture display window, expressed in units of PIXCLK cycles. The value of VID_XDS must be equal to VID_XDO plus the width of the display window. The actual offset, XDS', is given by:
XDS' = VID_XDS + 4
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23 - Video decoder (VID) registers VID_XFW

0x28
CO
D I F N
7
Displayed Frame Width

0 XFW[7:0]
L A I T N E
STi5500
VideoBaseAddress + 0x28 Read/write 0 VSYNC
Description This register is set up with a value equal to the width in macroblocks of the displayed picture. This is derived from the horizontal_size value transmitted in the sequence header.
VID_YDO
7 0x6E Address: Access: Reset state: Synchronization:
Display Y Offset
0 YDO[7:0]
VideoBaseAddress + 0x6E Read/write 0 VSYNC
Description
This register is set up with a number defining the first line of the picture display, i.e. the top edge of the display window. Lines are counted from the active (first) edge of VSYNC. In an interlaced display, the same value of VID_YDO would be used for both fields.
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STi5500 VID_YDS
0x6F
CO
D I F N
7
Display Y End
L A I T N E
YDS[7:0]
VideoBaseAddress + 0x6F Read/write 0 VSYNC
Description This register is set up with a number defining the bottom line of the display window. The value of YDS must be equal to:
VID_YDO + number of lines in picture counted in one field - 129 In an interlaced display, the same value of VID_YDS would be used for both fields.
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L A I T 24 Index of Registers N E D I F N CO
24 - Index of Registers
A_PTS_REG 117 AF_REG1-0 117 AR_SIZE_REG 118 ASCnBaudRate 23 ASCnControl 24 ASCnIntEnable 26 ASCnRxBuffer 27 ASCnStatus 28 ASCnTimeout 29 ASCnTxBuffer 30 AUD_ADA 31 AUD_ANC 31 AUD_BBE 31 AUD_CDI 32 AUD_CRC 32 AUD_DEM 32 AUD_DIF 33 AUD_DIV 33 AUD_ESC 34 AUD_EXT 34 AUD_FFL 34 AUD_FOR 35 AUD_HDR 35 AUD_IDE 35 AUD_IFT 36 AUD_IMS 36 AUD_ISS 36 AUD_ITM 37 AUD_ITR 37 AUD_ITS 38 AUD_LCA 38 AUD_LCK 38 AUD_LRP 39 AUD_MUT 39 AUD_ORD 39 AUD_P18 40 AUD_PLY 40 AUD_PTS 40 AUD_RCA 41 AUD_RES 41 AUD_RST 41 AUD_SCM 41 AUD_SCP 42 AUD_SEM 42 AUD_SFR 42 AUD_SID 43 AUD_SKP 43 AUD_SYE 43 AUD_SYN 44 AUD_SYS 45
STi5500
AUD_VER 45 BMDMADestAddress 46 CacheControl 47 CacheControlLock 47 CCCF1 58 CCCF2 58 CCLIF1 58 CCLIF2 59 CFG_CCF 50 CFG_CDR 50 CFG_DRC 51 CFG_GCF 51 CFG_MCF 52 CGMS_BIT 60 CHIPID 60 CKG_AUX 53 CKG_CFG 53 CKG_LNK 54 CKG_MCK 55 CKG_PCM 55 CKG_PLL 56 CKG_PXC 57 Clear_Exec 81 Clear_Mask 81 Clear_Pending 81 Clear_PnC2:0 92 Clear_PnComp 92 Clear_PnMask 92 Clear_PnOut 93 CONFIGURATION0 60 CONFIGURATION1 62 CONFIGURATION2 63 CONFIGURATION3 64 CONFIGURATION4 66 CONFIGURATION5 67 CONFIGURATION6 68 EMIConfigData0 74 EMIConfigData1 76 EMIConfigData2 77 EMIConfigData3 78 EMIConfigLockBank3-0 79 EMIConfigStatus 80 EMIDRAMInitialize 80 EN_LINK_REG 118 Exec 81 EXTRA_BITS_REG 119 FlushDCache 48 HandlerWptrn 82 INCREMENT_DFS 69 InputInterrupts 86
IntnPriority 86 InvalidateDCache 48 InvalidateICache 48 LINE_REG 70 LINK_STAT_FIFO 119 LINK_STAT_REG 121 Mask 82 MODE_REG 121 MPEGnBurstSize 87 MPEGnDecoderSelect 87 MPEGnHoldoff 87 MPEGnSuspend 88 PACKET_LENGTH 122 PCR_EXT_REG 122 PCR_REG 123 PCR_STREAM_REG 123 Pending 83 PES_CF1 89 PES_CF2 89 PES_TM1 90 PES_TM2 90 PES_TS 91 PHASE_DFS 70 PnC2:0 93 PnComp 94 PnIn 94 PnMask 94 PnOut 95 PWMCaptureCount 99 PWMControl 99 PWMCount 100 PWMIntAck 100 PWMIntEnable 101 PWMIntStatus 101 PWMnCaptureEdge 97 PWMnCaptureVal 97 PWMnCompareOutVal 98 PWMnCompareVal 98 PWMnVal 99 revid 71 ScnClkCon 103 ScnClkVal 103 SDAV_CONF_REG 123 SDAV_DATA_REG 124 SDAV_DMA_EN_REG 125 SelectCache 49 Set_Exec 84 Set_Mask 84 Set_Pending 84 Set_PnC2:0 95
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Set_PnComp 95 Set_PnMask 95 Set_PnOut 96 SPD_CTL1 104 SPD_CTL2 104 SPD_HLEX 105 SPD_HLEY 105 SPD_HLRC 105 SPD_HLRCO 105 SPD_HLSX 106 SPD_HLSY 106 SPD_LUT 106 SPD_RST 107 SPD_SPB 107 SPD_SPE 107 SPD_SPRead 108 SPD_SPWrite 108 SPD_SXD0 108 SPD_SXD1 109 SPD_SYD0 109 SPD_SYD1 109 SPD_XD0 110 SPD_XD1 110 SPD_YD0 110 SPD_YD1 111 SSC0BRG 112 SSC0Con 112 SSC0IEn 113 SSC0RBuf 114 SSC0SlAd 114 SSC0Stat 115 SSC0TBuf 115 STATUS 71 STREAM n configuration1 117 STREAM n configuration2 117 STREAM n configuration3 117 STREAM_EN_REGn 125 TIME_OUT_REG 126 TriggerMode 85
CO
D I F N
L A I T N E
24 - Index of Registers
VID_LSR 141 VID_NWM 142 VID_OBP 142 VID_OSD 142 VID_OTP 143 VID_PAN 143 VID_PFH 144 VID_PFV 144 VID_PPR1 144 VID_PPR2 145 VID_PTH 146 VID_QMW 146 VID_REV 146 VID_RFC 147 VID_RFP 147 VID_RSTA 147 VID_RSTV 148 VID_SCDcount 148 VID_SCN 148 VID_SPB 148 VID_SPE 149 VID_SPRead 149 VID_SPWrite 149 VID_STA 150 VID_TIS 151 VID_TRF 152 VID_VBG 153 VID_VBL 153 VID_VBS 154 VID_VBT 154 VID_VFC 154 VID_VFL 155 VID_XDO 155 VID_XDS 155 VID_XFW 156 VID_YDO 156 VID_YDS 157
ttx_block_map 72 ttx_block1-4 72 TtxtAbort 127 TtxtAckOddEven 127 TtxtDmaAddress 127 TtxtDmaCount 127 TtxtIntEnable 128 TtxtIntStatus 128 TtxtMode 128 TtxtOutDelay 129 USD_BMS 130 USD_BRP 130 USD_BWP 130 V_PTS_REG 126 VID_ABG 131 VID_ABL 131 VID_ABS 131 VID_ABT 132 VID_BFC 132 VID_BFP 132 VID_CDcount 133 VID_CSO 133 VID_CSR 133 VID_CTL 134 VID_DCF 135 VID_DFC 136 VID_DFP 136 VID_DFS 137 VID_DFW 137 VID_END 137 VID_FFC 138 VID_FFP 138 VID_FRZ 138 VID_HDF 138 VID_HDS 139 VID_ITM 140 VID_ITS 140 VID_LDP 140 VID_LSO 141
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L A I T 25 Revision history N E D I F N CO
25 - Revision history
Correction
STi5500
The corrections made to register manual revA in order to create this STi5500 register manual revB are given in the table below. Description
Table 1.2 Wait state encoding

Register AUD_SFR on page 42 Register CONFIGURATION5 on page 67 Register ttx_block1-4 on page 72
deleted all references to "2 wait states" reset state now defined 00 redefined bits bkr & bkg redefined txbs & txbe Table 25.1 RevA to revB corrections
Modifications relating to circuit improvements are included in this document, and given in the table below. Modification Register PES_CF1 on page 89 Register SPD_CTL1 on page 104 New register SPD_RST on page 107 Register VID_DCF on page 135 Register VID_DCF on page 135 New register VID_END on page 137 Description Added bit FAD (bit6) Bit SPP, VID_DCF on page 135 moved to SPD_CTL1 Bit SPR, VID_CTL on page 134 moved to SPD_RST Redefined bits2-0 Bit PXD re-defined Little endian - big endian conversion
Registers VID_STA on page 150, VID_ITM on page Added bit RPID (bit8) to each register 140 & VID_ITS on page 140 New register VID_NWM on page 142 Removed VID_DC2 Register VID_PPR2 on page 145 New register VID_RSTA on page 147 Added register VID_RSTV on page 148 Added register VID_SCN on page 148 Bit MP2, VID_TIS on page 151 moved to VID_PPR2 Audio reset Video reset Scan vector Not writable register mode
Removed registers VID_MLU & VID_MCH, Added registers VID_VFC on page 154 & VID_VFL on New chroma/luma vertical filter registers page 155 Table 25.2 Modifications
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L A I T N E
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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Sti5500 Register Manual

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Table 1.1 Register block base variables

Video and audio register addressing

Add to address 0x080 0x100 0x180

= 0x70 + WaitStateCode + AudioBaseAddress = 0x70 + 0x080 + 0x00001200 = 0x000012F0

Synchronization of video decoder registers

Table 2.1 Video registers

Table 2.1 Video registers

Table 2.1 Video registers

VID_CSO VID_CSR VID_YDO VID_YDS

Table 2.1 Video registers

0x00001206 0x00001207 0x00001208 0x00001209

Table 2.2 MPEG audio decoder registers

AUD_ORD AUD_RES AUD_RST AUD_SFR AUD_DEM AUD_IFT AUD_SCP AUD_ITS AUD_IMS

0x00001232 0x00001236 0x00001238 0x00001240 0x00001242 0x00001244 0x00001246 0x00001252

Table 2.3 Sub-picture decoder registers

0x00001407 0x00001408 0x00001409

Table 2.3 Sub-picture decoder registers

configuration0 configuration1 configuration2 configuration3 configuration4 configuration5 configuration6 status

cccf2 cclif1 cclif2

0x0000162A 0x0000162B 0x0000162C

Table 2.4 PAL/NTSC encoder (DENC) registers

0x00002000 0x00002004 0x00002008

Table 2.5 EMI configuration registers

Register CacheControl SelectCache InvalidateDCache InvalidateICache FlushDCache CacheControlLock

Address 0x00004000 0x00004100 0x00004200 0x00004300 0x00004400 0x00004500

Access R/W W W W W R/W

Table 2.6 Cache control registers

0x20000000 0x20000004 0x20000008

Table 2.7 Interrupt controller registers

Name STREAM_EN_REGn LINK_STAT_REG LINK_STAT_FIFO PACKET_LENGTH TIME_OUT_REG

Address 0x20002F00 +4n 0x20002F80 0x20002F84 0x20002F88 0x20002F8C

Number of bytes per packet. AR threshold to reset the block.

Table 2.8 Transport stream demultiplexor registers

PCR_STREAM_REG AF_REG0 AF_REG1

Table 2.8 Transport stream demultiplexor registers

Access R/W W R R/W R/W R R/W R/W W W

Table 2.9 ASC 0 registers

Register ASC1BaudRate ASC1TxBuffer

ASC1RxBuffer ASC1Control ASC1IntEnable ASC1Status ASC1Guardtime ASC1TimeOut ASC1TxReset ASC1RxReset

Description ASC 1 Baud rate generator/reload.

0x20004000 0x20004004 0x20004008

0x2000400C 0x20004010 0x20004014 0x20004018 0x2000401C 0x20004020 0x20004024

Table 2.10 ASC 1 registers

Access R/W W R R/W R/W R R/W R/W R/W W W

Table 2.11 ASC 2 registers (SmartCard0)

Register ASC3BaudRate ASC3TxBuffer ASC3RxBuffer ASC3Control ASC3IntEnable

Address 0x20006000 0x20006004 0x20006008 0x2000600C 0x20006010

Access R/W W R R/W R/W

Table 2.12 ASC 3 registers (SmartCard1)

ASC3Guardtime ASC3TimeOut ASC3TxReset

0x2000601C 0x20006020 0x20006024

Table 2.12 ASC 3 registers (SmartCard1)

Register Sc0ClkVal Sc0ClkCon

Address 0x20007000 0x20007004

Access W W SmartCard 0 clock.

SmartCard 0 clock control.

Table 2.13 SmartCard 0 registers

Register Sc1ClkVal Sc1ClkCon

Address 0x20008000 0x20008004

Access W W SmartCard 1 clock.

SmartCard 1 clock control.

Table 2.14 SmartCard 1 registers