8120 M Tellabs Node Operating Manual

Tellabs 8100 Managed Access System Tellabs 8120 Mini Node M Operating Manual
22030_12 07.01.2013
Document Information
Revision History
Document No. 22030_12 22030_11 22030_10 22030_09 Date 07.01.2013 09.03.2009 29.08.2008 02.11.2007 Description of Changes The Tellabs 8120 mini node has been discontinued. A discontinuation note has been added in ch. 1. Erroneous V35-M discontinuation note removed throughout the document. Layout and cross reference changes due to format conversion throughout the document. Safety notes related to grounding updated in chapters 4.5 and 6.11. Outdated data removed from the foreword. Figures 2, 24, 25 and 40 updated. The list of numbered items referring to the mechanical construction updated in chapter 4.8. Disassembling instructions updated in chapter 4.8.1. EMC standard updated in chapter 6.12.
2013 Tellabs. All rights reserved. This Tellabs manual is owned by Tellabs or its licensors and protected by U.S. and international copyright laws, conventions and treaties. Your right to use this manual is subject to limitations and restrictions imposed by applicable licenses and copyright laws. Unauthorized reproduction, modication, distribution, display or other use of this manual may result in criminal and civil penalties. The following trademarks and service marks are owned by Tellabs Operations, Inc. or its afliates in the United States and/or other countries: TELLABS , TELLABS logo, TELLABS and T symbol , and T symbol . Any other company or product names may be trademarks of their respective companies. The specications and information regarding the products in this manual are subject to change without notice. All statements, information, and recommendations in this manual are believed to be accurate but are presented without warranty of any kind, express or implied. Users must take full responsibility for their application of any products. Adobe Reader are registered trademarks of Adobe Systems Incorporated in the United States and/or other countries.
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Document Information
Terms and Abbreviations

Term Explanation
ADPCM AIS CAS CRC DMA FAS FrFEA HDLC IF MEI MFrFEA PMA RAI TS VF
Adaptive Differential Pulse Code Modulation Alarm Indication Signal Channel Associated Signalling Cyclic Redundancy Check Deferred Maintenance Alarm Frame Alignment Signal Frame Far-end Alarm High Level Data Link Control Interface Maintenance Event Information Multiframe Far-end Alarm Prompt Maintenance Alarm Remote Alarm Indication Time Slot Voice Frequency
Compliance Statement Hereby, Tellabs Oy declares that this product is in compliance with the essential requirements and other relevant provisions of Directive 1999/5/EC.
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Table of Contents
Table of Contents
About This Manual .............................................................................................................. 9

Objectives......................................................................................................................................................................... 9 Audience........................................................................................................................................................................... 9 Discontinued Products...................................................................................................................................................... 9 Document Conventions .................................................................................................................................................... 9 Documentation Feedback............................................................................................................................................... 10
Introduction ................................................................................................................. 11
1.1 Construction..........................................................................................................................................................11
Tellabs 8120 Mini Node M as Tellabs 8100 Network Element.................................. 13

2.1 2.2 2.3 General................................................................................................................................................................. 13 Framed Interfaces IF1 and IF2 ............................................................................................................................ 14 User Access Ports ................................................................................................................................................ 16 2.3.1 Unframed Interfaces ............................................................................................................................ 16 2.3.2 Framed Interface as User Access Port................................................................................................. 17 2.3.3 Rules for Mixing Different Interface Types ........................................................................................ 17 Applications......................................................................................................................................................... 17 2.4.1 Framed Interfaces ................................................................................................................................ 17 2.4.2 Unframed Interfaces ............................................................................................................................ 20 Network Synchronization .................................................................................................................................... 23
2.4
2.5
Operation ..................................................................................................................... 25
3.1 3.2 General................................................................................................................................................................. 25 G.704 Framed Interfaces IF1 and IF2 ................................................................................................................. 26 3.2.1 Frame and Multiframe Structure ......................................................................................................... 27 3.2.2 Buffers ................................................................................................................................................ 28 3.2.3 Split Trunk Lines ................................................................................................................................. 30 3.2.4 1+1 Protection ..................................................................................................................................... 30 Operation of Framed Interfaces ........................................................................................................................... 31 Unit Controller..................................................................................................................................................... 34 Cross-Connect Block........................................................................................................................................... 35 3.5.1 Cross-Connection ................................................................................................................................ 35 3.5.2 Master Clock Synchronization ............................................................................................................ 37 Operation of Unframed Channel Interfaces IF3-IF6 ........................................................................................... 38
3.3 3.4 3.5
3.6
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3.7
3.6.1 Data Formatting Functions .................................................................................................................. 39 3.6.2 Data Interfaces..................................................................................................................................... 43 3.6.3 Timing Modes...................................................................................................................................... 43 3.6.4 Rate Adaptation and Mapping............................................................................................................. 46 3.6.5 Cross-Connection of Unframed Interfaces .......................................................................................... 48 Test Resources ..................................................................................................................................................... 49 3.7.1 Equipment Test .................................................................................................................................... 49 3.7.2 Test of Framed Interfaces .................................................................................................................... 50 3.7.3 Tests of Unframed Interfaces............................................................................................................... 53
Installation ................................................................................................................... 56
Front Panel Indicators and Controls .................................................................................................................... 56 Back Panel Connections ...................................................................................................................................... 56 Mains Connection................................................................................................................................................ 58 Operating Environment ....................................................................................................................................... 58 4.4.1 DC Power Supply Cabling .................................................................................................................. 59 4.4.2 SC, Local Service Computer Connector.............................................................................................. 60 4.4.3 SYNC Connector................................................................................................................................. 60 4.5 Conguration of Tellabs 8120 Mini Node M ...................................................................................................... 60 4.5.1 NMS Control ....................................................................................................................................... 62 4.5.2 Local Control....................................................................................................................................... 62 4.6 Menus of Tellabs 8120 Mini Node M ................................................................................................................. 63 4.6.1 Security Menu...................................................................................................................................... 68 4.6.2 Faults Menu ......................................................................................................................................... 71 4.6.3 Parameters Menu ................................................................................................................................. 72 4.6.4 Interface Parameters Menu.................................................................................................................. 75 4.6.5 Cross-Connection Menu ...................................................................................................................... 80 4.6.6 Copy Settings Menu ............................................................................................................................ 86 4.6.7 Entering Security Menu of Tellabs 8120 Mini Node M ...................................................................... 87 4.7 Recommended Settings of Framed Interfaces ..................................................................................................... 87 4.7.1 Framed Interface Used as 2048 kbit/s Trunk....................................................................................... 87 4.7.2 Framed Interface Used as 2048 kbit/s User Access Point ................................................................... 88 4.7.3 Framed Interface Used as 8448 kbit/s Trunk....................................................................................... 89 4.7.4 BTE-384-M Settings............................................................................................................................ 90 4.7.5 BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M Settings ......................................... 91 4.7.6 Cross-Connection Example ................................................................................................................. 93 4.7.7 Binary-to-Hexadecimal Conversion Table .......................................................................................... 93 4.8 Service Operations and Modications................................................................................................................. 94 4.8.1 Instructions on Disassembling Tellabs 8120 Mini Node M ................................................................ 96 4.9 Unit List of Tellabs 8120 Mini Node M .............................................................................................................. 97 4.9.1 Common Units..................................................................................................................................... 97 4.9.2 Main Interface Modules....................................................................................................................... 98 4.9.3 V Series Interface Modules ................................................................................................................. 99 4.10 Connectors and Strappings of Framed Interfaces.............................................................................................. 100 4.10.1 G703-75-M and G703-120-M, G.703 2 Mbit/s................................................................................. 100 4.10.2 LTE-M Line Terminal 1 or 2 Mbit/s.................................................................................................. 102 4.10.3 G703-8M-M, 8 Mbit/s ....................................................................................................................... 103 4.10.4 OTE-LED-M, Optical LED, 2 or 8 Mbit/s ........................................................................................ 103 4.10.5 BTE-384-M, BTE-1088-M, BTE-2048-M, BTE-2048-2W-M and BTE-4096-M, 384 kbit/s4224 kbit/s .................................................................................................................................................. 104 4.10.6 BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M, 3202304 kbit/s ....................... 106 4.1 4.2 4.3 4.4
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4.10.7 V35-G704-SM, V.35 n x 64 kbit/s2 Mbit/s ................................................................................... 107 4.10.8 X21-G704-SM, n x 64 kbit/s2Mbit/s............................................................................................. 108 4.11 Connectors and Strappings of Unframed Interfaces.......................................................................................... 109 4.11.1 V35-M, V.35 48, 56, n x 64 kbit/s Interfaces, 2 pcs .......................................................................... 109 4.11.2 V36-M, V.36 48, 56, n x 64 kbit/s Interfaces, 2 pcs ...........................................................................110 4.11.3 V24-DCE-M, V.24/V.28 if/DCE, 0.664 kbit/s, 2 pcs .....................................................................112 4.11.4 V24-DTE-M, V.24/V.28 if/DTE, 0.664 kbit/s, 2 pcs ......................................................................113 4.11.5 X21-M, X.21 1.2n x 64 kbit/s Interface, 2 pcs ...............................................................................114 4.11.6 G703-64-M, G.703 64 kbit/s Co/Contradirectional Interface, 2 pcs ..................................................115 4.11.7 V35/V24-M, V.24/V.28 if/DCE, 0.664 kbit/s; V.35-IEC if, n x 64 kbit/s.......................................116 4.11.8 HSSI-M, TIA/EIA 612, 0.68448 kbit/s ..........................................................................................117 4.11.9 Mini LAN Module, 10Base-T, 642048 kbit/s.................................................................................119 4.12 Software Update ................................................................................................................................................ 120 4.12.1 Downloading Tellabs 8120 Mini Node M Software ......................................................................... 120 4.12.2 Replacing EPROMs........................................................................................................................... 121
Faults and Actions .................................................................................................... 123

5.1 5.2 Terminology....................................................................................................................................................... 123 Common Faults and Actions ............................................................................................................................. 124 5.2.1 Common Logic Faults (Block 0) ....................................................................................................... 124 5.2.2 Master Clock Faults (Block 0)........................................................................................................... 125 5.2.3 Cross-Connect Block Faults (Block 0).............................................................................................. 125 5.2.4 Faults of Framed IF Tx Signal (Block 1, 2) ..................................................................................... 126 5.2.5 Faults of Framed IF Rx Signal (Block 1, 2) ...................................................................................... 127 5.2.6 1+1 Protection Switch Fault Messages (Block 0) ............................................................................. 130 5.2.7 Miscellaneous Faults of Framed Interfaces (Block 1, 2)................................................................... 130 5.2.8 Fault and Service Status (PMA, DMA, MEI, S) in 1+1 Mode of Framed Interfaces ....................... 130 5.2.9 Fault Conditions of Framed Interfaces .............................................................................................. 131 Faults and Actions of Unframed Interfaces...................................................................................................... 132 5.3.1 General IF Faults of Unframed Interfaces ......................................................................................... 132 5.3.2 IF Signal Faults of Unframed Interfaces ........................................................................................... 133 5.3.3 Net Side Signal Faults of Unframed Interfaces ................................................................................. 133 5.3.4 Test Loop Activation of Unframed Interfaces ................................................................................... 134 5.3.5 Performance Conditions of Unframed Interfaces.............................................................................. 134 5.3.6 Common Faults of Unframed Interfaces ........................................................................................... 135 5.3.7 Reference Points of Unframed Interfaces.......................................................................................... 135
5.3
Technical Specications of Tellabs 8120 Mini Node M .......................................... 136

6.1 6.2 6.3 6.4 Relevant Recommendations .............................................................................................................................. 136 Cross-Connect ................................................................................................................................................... 137 Timing................................................................................................................................................................ 138 G.704 Framed Interface..................................................................................................................................... 138 6.4.1 Frame and Multiframe Buffer............................................................................................................ 138 6.4.2 8448 kbit/s Interface (CCITT G.704) ................................................................................................ 139 6.4.3 2048 kbit/s Interface (CCITT G.704/706)......................................................................................... 140 6.4.4 N x 64 kbit/s Interface with G.704 Type Frame ................................................................................ 141 Unframed Data Interfaces.................................................................................................................................. 142 6.5.1 V.24/V.28,V.35,V.36/V.11; 1.219.2 kbit/s, 48, 56, n x 64 kbit/s .................................................... 142
6.5
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6.5.2 X.21 1.219.2 kbit/s, 48, 56, n x 64 kbit/s....................................................................................... 143 6.5.3 Transparent 2 Mbit/s, n x 64 kbit/s.................................................................................................... 143 6.6 Data Interface Modules ..................................................................................................................................... 143 6.6.1 8448 kbit/s, G.703 Interface (G703-8M-M Module) ........................................................................ 143 6.6.2 2048 kbit/s, G.703 Interface (G703-75-M) ....................................................................................... 144 6.6.3 2048 kbit/s, G.703 Interface (G703-120-M) ..................................................................................... 144 6.6.4 2048 kbit/s and 1088 kbit/s Line Terminal Interface (LTE-M Module)............................................ 144 6.6.5 Optical Line Interface 2048 kbit/s / 8448 kbit/s (OTE-LED-M Module) ......................................... 145 6.6.6 Baseband Line Interface 64384 kbit/s (BTE-384-M Module) ...................................................... 145 6.6.7 Baseband Line Interfaces 320...4224 kbit/s (BTE-1088-M, BTE-2048-M, BTE-2048-2W-M, BTE-4096-M, BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M Modules) ............. 146 6.7 Service Computer (SC) Interface ...................................................................................................................... 146 6.8 Power Supply..................................................................................................................................................... 147 6.8.1 Power Consumptions of Tellabs 8120 Mini Node M Units and Modules......................................... 147 6.9 Mechanics.......................................................................................................................................................... 148 6.10 Environmental Conditions................................................................................................................................. 148 6.10.1 Climatic/Mechanical Compatibility .................................................................................................. 148 6.11 Safety Compatibility.......................................................................................................................................... 149 6.12 Electromagnetic Compatibility.......................................................................................................................... 149
Appendix 1: Frame Structures ...................................................................................... 150

Frame Structures at Bit Rates 482048 Kbit/s ........................................................................................................... 150 Frame Structures at Bit Rates below 48 Kbit/s ............................................................................................................ 157
Appendix 2: G.704 Frame Structures............................................................................ 162

8448 kbit/s Frame Structure ......................................................................................................................................... 162 2048 kbit/s Frame Structure ......................................................................................................................................... 163 N x 64 kbit/s Frame Structure ...................................................................................................................................... 164 Multiframe Structure in Signalling Time Slot.............................................................................................................. 166 CRC Multiframe Structure in TS0 for 2 Mbit/s and n x 64 kbit/s Frames................................................................... 167
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About This Manual
About This Manual

This section discusses the objectives and intended audience of this manual, Tellabs 8100 Managed Access System Tellabs 8120 Mini Node M Operating Manual and consists of the following sections: Objectives Audience Discontinued Products Document Conventions Documentation Feedback
Objectives
The goal is to describe the network element features of Tellabs 8120 mini node M and its installation.
Audience
This manual is intended for system specialists and personnel involved in network planning.
Discontinued Products
Tellabs 8100 Managed Access System Discontinued Products list can be found in Tellabs Portal, www.portal.tellabs.com by navigating to Product Documentation > Managed Access > Tellabs 8100 Managed Access System (Includes all 81XX products) > Technical Documentation > Network Element Manuals > 8100 List of Discontinued Products.
Document Conventions
This is a note symbol. It emphasizes or supplements information in the document.
This is a caution symbol. It indicates that damage to equipment is possible if the instructions are not followed.
This is a warning symbol. It indicates that bodily injury is possible if the instructions are not followed.
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About This Manual
Documentation Feedback
Please contact us to suggest improvements or to report errors in our documentation: Email: -documentation@tellabs.com Fax: +358.9.4131.2430
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1 Introduction
1 Introduction
The Tellabs 8120 mini node M has been discontinued.
This operating manual describes the version 6.1 or later of Tellabs 8120 mini node M (SBM 2048M). Tellabs 8120 mini node M (SBM 2048M) is a small cross-connect device, which can operate either as part of the Tellabs 8100 managed access system network connected to Tellabs 8000 network manager, or as a separate cross-connect device controlled and supervised locally. This piece of equipment can be furnished with up to two framed interfaces and up to two unframed interface modules (usually two interfaces per module). Tellabs 8120 mini node M can make connections between interfaces of any type. The transmission rates and physical features of the interfaces depend on the used interface modules. Different interface modules are available for different applications. The transmission rates of framed interfaces are 2048 kbit/s, 8448 kbit/s and n x 64 kbit/s, where n = 233. The frame structure of a framed interface is according to CCITT G.704. The modied G.704 frame is used at n x 64 kbit/s. The transmission rates of unframed interfaces can be 0.62048 kbit/s. The interfaces can, for example, be V.35, V.36, V.24 or X.21 depending on the used interface module. The conguration and control of Tellabs 8120 mini node M can be applied in different ways. As part of the Tellabs 8100 network, the control can be realised through Tellabs 8000 manager, where the control channel is connected to the device through a framed interface. On the front panel there is a connector for the service computer, which can manage the conguration and control with a user interface with windows. The front panel of Tellabs 8120 mini node M is provided with an LCD display and keyboard (four buttons) which can handle the menu controlled user interface control functions needed when using Tellabs 8120 mini node M.
1.1
Construction
Tellabs 8120 mini node M is built into a compact metallic case. It is suitable for tabletop use. Under the metallic cover there are the following parts: main unit switching power supply unit (AC or DC) channel board two user access interface modules two framed interface modules On the front panel there are an LCD display with 2 x 24 characters, four pushbuttons, alarm LEDs for each channel and a connector for the service computer.
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1 Introduction
Fig. 1 Tellabs 8120 Mini Node M Front Panel
On the back panel of Tellabs 8120 mini node M there are the interface connectors, a power cord, the synchronization connectors and a measurement point connector. The connector type depends on the module in use. The connectors for framed interfaces IF1 and IF2 are on the lower part of the back panel and the connectors for user access ports on the upper part.
Fig. 2 Example of Tellabs 8120 Mini Node M Back Panel Connectors
A framed interface module has one interface. The type for interfaces IF1 and IF2 can be selected irrespective of each other. An unframed interface module has typically two interfaces which are of the same type. The desired combination of modules can be selected for one piece of equipment according to the unit list. For further details and possible exceptions refer to 4.9 Unit List of Tellabs 8120 Mini Node M. For example in Fig. 2, the connectors for the framed interfaces IF1 and IF2 are on the bottom row of the back panel and the connectors for the user access ports at the upper part of it. In this example the interface IF1 is G703-75-M, and the interface IF2 is OTE-LED-M. The interfaces IF3 and IF4 are of type V.36, and the interfaces IF5 and IF6 are of type V.35.
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2 Tellabs 8120 Mini Node M as Tellabs 8100 Network Element

2.1 General
Tellabs 8120 mini node M is connected through the framed interfaces to another Tellabs 8120 mini node or a corresponding piece of equipment, a Tellabs 8100 node, the public transmission network or another transmission device with a G.703/G.704 interface. The interfaces with which Tellabs 8120 mini node M is connected to the Tellabs 8100 network or to another similar piece of equipment are called trunk interfaces in this manual. Tellabs 8120 mini node M can also be described as a digital multiplexer equipped with two trunk interfaces. Like an ordinary multiplexer, it can support channel interfaces. The cross-connect function of the equipment is independent of the channel interfaces. This facilitates the exible implementation of different channel interfaces.
Fig. 3 Architecture of Tellabs 8120 Mini Node M
The trunk interfaces are provided with the CCITT G.704/706 compliant frame structure. The system uses a synchronous time slot interleaved framing. A part of the frame is reserved for the internal information transfer of the system (frame alignment, CRC check, network management channel). For example, in the 2 Mbit/s G.704 frame this information is typically in time slot TS0. These time slots of the trunk lines are never used for transporting cross-connect channels (XB/XD channels). The user access interfaces can be divided into two main categories: unframed user data G.704 framed user data A framed interface can also be a user access interface. Cross-connections can be made in accordance with the following:
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framed/framed framed/unframed unframed/unframed When an interface is used for cross-connection, it is called a port. The mapping of the user access ports to the trunks by the cross-connect are based on the following signals: time slots: n x 64 kbit/s time slot bits: n x 8 kbit/s The n x 8 kbit/s and n x 64 kbit/s groups mapped by the channel interfaces are called XB channels. The XB channel can also be a combination of 64 kbit/s and 8 kbit/s signals.
Fig. 4 XB and XD Channels
If the interfaces are equipped with signalling or control signals, they are either mapped to the XB channel or to the corresponding signalling bits (n x 500 bit/s) of the XB channel. In the latter case the signals are mapped into the G.704-compliant multiframe of the 2 or 8 Mbit/s trunk. The n x 500 bit/s signalling bits are called the XD channel of the interface. Unframed interfaces do not normally use the XD channel.
2.2
Framed Interfaces IF1 and IF2

In most cases the framed interfaces of Tellabs 8120 mini node M are used as trunk interfaces. The framed interfaces (IF1, IF2) provided by Tellabs 8120 mini node M are shown in the table below. (The modules are electrically, but not mechanically, identical with the modules in the GMH unit of the Tellabs 8100 system.)
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Framed Interface Modules Module Type BTE-384-M2 Electrical Interface 2W/4W Biphase code 2W 2B1Q code 2W 2B1Q code 2W/4W 2B1Q code 4W 2B1Q code 2W 2B1Q code 4W 2B1Q code 2W/4W 2B1Q code 4W 2B1Q code LTE Bit Rate n= 26 XB/XD Capacity1 n-2 TS for XB channels 1 TS for XD channels4 n-1 TS for XB channels n-1 TS for XB channels n-1 TS for XB channels n-2 TS for XB channels 1 TS for XD channels4 n-1 TS for XB channels n-2 TS for XB channels 1 TS for XD channels4 n-1 TS for XB channels n-2 TS for XB channels 1 TS for XD channels4 n-2 TS for XB channels 1 TS for XD channels4 30 TS for XB channels 1 TS for XD channels4 n-2 TS for XB channels 1 TS for XD channels4 n-2 TS for XB channels 1 TS for XD channels4 30 TS for XB channels 1 TS for XD channels4 120 TS for XB channels 4 TS for XD channels4 5 spare TS5 30 TS for XB channels 1 TS for XD channels4 30 TS for XB channels 1 TS for XD channels4 120 TS for XB channels 4 TS for XD channels4 5 spare TS5
BTE-320-M2 BTE-576-M2 BTE-10882W-M2 BTE-2048-M2 BTE-20482W-M2 BTE-1088-M2 BTE-2304-M2 BTE-4096-M2 LTE-M2, 3
n=5 n=5, 9 n=5, 9, 16, 17 n=16, 17, 32, 33 n=16, 17, 32, 33 n=5, 9, 17 n= 16, 17, 32, 33, 34, 36 n= 16, 17, 82, 33, 64, 66 1088 kbit/s 2048 kbit/s
V35-G704-SM2 X21-G704-SM2 OTE-LED-M
V.36/V.11 V.11 Optical LED
n x 64 kbit/s n = 233 n x 64 kbit/s n = 233 2048 kbit/s 8448 kbit/s
G703-75-M G703-120-M G703-8M-M2
G.703 G.703 G.703
2048 kbit/s 2048 kbit/s 8448 kbit/s
1TS
= 64 kbit/s time slot. interface module has been discontinued. 3LTE = integrated line terminal. 4XD time slots can be turned off and used as XB time slots. 5One is used for HDLC. These ve XB time slots do not have XD channels associated with them.
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2.3
2.3.1
User Access Ports

Unframed Interfaces
Tellabs 8120 mini node M supports two channel interface modules.
Unframed Channel Interface Modules Module Type V35-M, V36-M6 V24-DCE-M6 V24-DTE-M6 V35/V24-M6 X21-M G703-64-M6 HSSI-M6 Mini LAN Module9 Electrical Interface V.35 or V.36/V.11 V.24/V.28 V.24/V.28 V.35-IEC X.21/X.27 G.703 co/contradir TIA/EIA 612 10Base-T Ethernet Bit Rate 0.64224 kbit/s7 0.664 kbit/s 0.664 kbit/s / 0.68192 kbit/s8 0.64224 kbit/s7 64 kbit/s 0.68448 kbit/s 642048 kbit/s
The modules are electrically, but not mechanically, identical with the modules in the channel unit of the Tellabs 8100 system. The functions of these data interfaces are V.110 rate adaptation for bit rates 56 kbit/s CRC end-to-end monitoring possible with all bit rates control signal transmission through the network (V.13 simulated carrier or in the V.110 frame) interface, local and V.54 remote loops One end of the circuit can be any other data interface or a G.704 user access point in another Tellabs 8120 mini node or in a Tellabs 8100 node. The circuit types can be point-to-point (pp) broadcast (bc) Tellabs 8120 mini node M does not support the point-to-multipoint server functions as the channel unit in the Tellabs 8100 node. The user interfaces, however, can be connected as end points to a point-to-multipoint circuit when the Point-to-Multipoint (pmp) Servers (branch points) are in the Tellabs 8100 nodes.
interface module has been discontinued. maximum bit rate per module is 8448 kbit/s. This capacity can be divided between two channels in the modules V35-M, V36-M and X21-M. Tellabs recommends the HSSI-M module for usage above 2 Mbit/s bit rates as it offers the possibility to have more cable length. 8Tellabs recommends the HSSI-M module for usage above 2 Mbit/s bit rates as it offers the possibility to have more cable length. 9The technical name SMU-BRIDGE can be seen in Tellabs 8000 manager.
7The
6The
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2.3.2
Framed Interface as User Access Port

Framed n x 64 kbit/s, 2 Mbit/s or 8 Mbit/s interfaces can be used as user access interfaces in which case the interfaces are called G.704 user access ports which means that there is no HDLC channel. In principle, the framed interfaces provide the same features as the corresponding trunk interfaces. A framed channel interface can offer several user access ports. A 2 Mbit/s G.704 user access port can comprise the following time slots and time slot fractions.
Cross-Connectable Time Slot Fractions n x 64 kbit/s 32 kbit/s 16 kbit/s 8 kbit/s XB n x 64 kbit/s 32 kbit/s 16 kbit/s 8 kbit/s XD n x (a, b, c, d) a, b/c, d a/b/c/d -
A typical G.704 user access port is a 2 Mbit/s interface for a digital PABX.
2.3.3
Rules for Mixing Different Interface Types

Usually, both ends of the connection use the same interface type. In some cases it is possible to mix different interface types. Different electrical interfaces are not usually of major concern. At least the following points must be checked between both ends: same use of control bits in V.110 frame same XB/XD capacity same XB framing of data circuits (V.110, modied V.110, no framing) The structure of the XB/XD channel is not normally transported outside the network. It is, however, very easy to do by using the G.704 framed user access port. In this case the standard procedures should be used: V.110 framing (56 kbit/s) V.13 simulated carrier (V type interfaces 64 kbit/s) X.30-specied X.21 C/I mapping (X.21 48 kbit/s)
2.4
2.4.1
Applications
Framed Interfaces
There are different applications for the transmission rate and the features of the framed interfaces in Tellabs 8120 mini node M. Fig. 5 presents the different ways to interconnect two Tellabs 8120 mini node M devices. The same alternatives are available when connecting Tellabs 8120 mini node M to a Tellabs 8100 node.
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Fig. 5 Tellabs 8120 Mini Node M Trunk Lines
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BTE Modules The BTE modules10 serve baseband transmission at rates 128-4224 kbit/s. The frame structure is a modied G.704 frame, where the overhead of 64 kbit/s is used for the frame structure. The available transmission rate for the terminal equipment is the line rate subtracted by 64 kbit/s. The rate can freely be allocated between all user access points by the cross-connection of the equipment. BTE-384-M uses biphase transmission for 2- or 4-wire lines at rates 128-384 kbit/s. The cable length can be up to 3.5-6 km depending on the cable type and the transmission rate. BTE-1088-M, BTE-2048-M, BTE-4096-M offer HDSL-like performance at rates 320-4224 kbit/s using 4-wire transmission, 2B1Q line code. BTE-2048-2W-M offers 2-wire full duplex operation over a single wire pair using echo cancellation. The cable length can be 3-10 km depending on the rate, module and cable characteristics. BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M offer HDSL-like performance at rates 320-2304 kbit/s using 2-wire full duplex transmission over a single wire pair. The line code is 2B1Q. BTE-1088-2W-M and BTE-2304-M offer also additional 4-wire modes at rates 320-2304 kbit/s. The cable length can be 4-10 km depending on the rate, module and cable characteristics. Using a BTE module, Tellabs 8120 mini node M can be connected to a Tellabs 8100 node with a corresponding interface, another Tellabs 8120 mini node or to table top baseband modems SBM 384A (with BTE-384-M), STU-2048 (with BTE-2048-M), STU-1088 (with BTE-1088-M), STU-320 (with BTE-320-M), STU-576 (with BTE-576-M), STU-1088-2W (with BTE-1088-2W-M) or STU-2304 (with BTE-2304-M). LTE-M11 The LTE-M module provides a line interface for a symmetrical pair cable. The transmission rates of the LTE module are 2048 kbit/s and 1088 kbit/s. The impedance of the transmission line is 120 and the maximum attenuation of the transmission line can be -36 dB. The 2048 kbit/s interface complies with G.703/G.704 Recommendations. At the 1088 kbit/s rate a modied G.704 frame is used. Depending on the cable type and transmission rate, cable lengths of over two kilometers can be reached. G703-75-M and G703-120-M The G703-75-M and G703-120-M modules offer an interface with a transmission rate of 2048 kbit/s. The impedance of the transmission line is xed (75 or 120 , respectively). The maximum attenuation of the transmission line is 6 dB. The interface complies with the corresponding Recommendations G.703/G.704. The interface is designed for the interconnection of equipment in the same physical location.
10The production of the interface modules BTE-64-M, BTE-320-M, BTE-384-M, BTE-576-M, BTE-1088-M, BTE-1088-2W-M, BTE-2048-M, BTE-2048-2W-M, BTE-2304-M, BTE-4096-M and baseband modems SBM 384, STU-320, STU-576, STU-1088, STU-1088-2W, STU-2048 and STU-2304 has been discontinued. 11The production of the interface module LTE-M has been discontinued.
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G703-8M-M12 The G703-8M-M module is similar to G703-75-M but with a transmission rate of 8448 kbit/s. The impedance of the transmission line is xed 75 and the maximum allowable attenuation of the transmission line is 6 dB. OTE-LED-M The OTE-LED-M module is an optical ber interface. Almost all ber types which are suitable for data transmission (not plastic-coated bers) can be used with this module. The connector is of type FC. Transmission distances of several dozens of kilometers can be achieved with an OTE module. The transmission rates are 2048 kbit/s and 8448 kbit/s, and the frame structure is according to G.704. V35-G704-SM and X21-G704-SM13 Tellabs 8120 mini node M can be equipped with a V35-G704-SM module, where the connection signal levels are according to the V.35 or V.11 Recommendations, the interface timing is codirectional and the connectors are of type D with 9 pins. The rate of the interface is n x 64 kbit/s (n = 233) and the frame structure is modied G.704. The interface is designed for the connection of Tellabs 8120 mini node M to the V series interface provided by the public data transmission network, using the bit rate of n x 64 kbit/s. The modules V35-G704-SM and X21-G704-SM have 2 23-1 type scramblers in both transmission directions. The scramblers can be used when the transmission rate is 31 x 64 kbit/s or lower except by the unframed mode, where the scramblers cannot be used. It is advisable to use the scramblers whenever it is possible. Special Modes The interfaces IF1 and IF2 of Tellabs 8120 mini node M can be connected to 1+1 protecting mode when both interfaces transmit the same data in the transmission direction. In the receive direction, however, the better one of the two received signals is selected for the terminal equipment interfaces. This duplication is used in order to protect the transmission. The protection can be realised with any two modules with the same transmission rate. The interfaces IF1 and IF2 can use the split trunk transmission method as well, where the signal from the terminal equipment interface is distributed to the two framed connections and returned at the receiving end in its original form. This facilitates a transmission where the transmission rate of the signal from the terminal equipment interface is higher than the rate of a separate framed interface. Restrictions for the maximum propagation time difference between the transmission lines of the framed interfaces are set. It is recommended that both interfaces use the symmetrical pairs located in the same cable.
2.4.2
Unframed Interfaces
The unframed interfaces of Tellabs 8120 mini node M support user bit rates 600 bit/s8448 kbit/s. Normally, Tellabs 8120 mini node M should be installed near the equipment in order to be accessed.
12The 13The
production of the interface module G703-8M-M has been discontinued. production of the interface modules V35-G704-SM and X21-G704-SM has been discontinued.
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Unframed Channel Interface Types Interface Bit Rate kbit/s 0.64.8 7.29.6 14.419.2 38.4 48 56 72 80 144 160 n x 64 n x 64 64 Interface Type V24, X21 V24, X21 V24, X21 V24, X21 V24, 35, 36, X21 V24, 35, 36, X21 V35, 36, X21 V35, 36, X21 V35, 36, X21 V35, 36, X21 V35, 36, X21 V35, 36, X21 G.703 (co or contradir) XB Bit Rate kbit/s 8 16 32 64 64 64 72 (+8 or 16) 80 (+8 or 16) 152 (+8) 160 (+8 or 16) n x 64 (+8,16 or 24) n x 64 (+8 or 24) 64 +(8) Structure V.110 V.110 V.110 V.110 V.110 V.110 frame frame frame frame frame V.13 Notes
1415 1415 1415 1415 1615 1615 17 17 17 17 17 18 17
V.24/V.28 can be synchronous or asynchronous. The ITU-T-specied V.14 synchronous/asynchronous conversion is used. The C/I control signal mapping of the X.21 interface is done for bit rates 48 kbit/s according to the Recommendation X.30 (compatible with V.110). At bit rates 56 kbit/s and n x 64 kbit/s the C/I can be mapped through the network but it is proprietary. The XB structure in the table above refers to the framing or coding of user data when it is mapped into the trunk. V.110 is a typical frame used for data connections and it is used in an ISDN network for the rate adaptation of V and X series interfaces. The framing is used between the user access ports of the connection and it is not visible outside the trunks of the network. The end-to-end connection is monitored and supervised by the V.110 frame in the data interface types <64 kbit/s. With bit rates n x 64 kbit/s it is only possible to map the user data into the XB/XD channel. It is, however, possible to map the data with an additional n x 8 kbit/s frame which includes end-to-end monitoring (CRC) and network-independent clocking for channels. The bit rate of the additional frame is presented below.
Bit Rate of Additional Frame 105/109 Transfer CRC Network Independent Clocking User Rate 512 kbit/s Frame Rate kbit/s 8 ON ON ON ON 8 8 16 User Rate >512 kbit/s Frame Rate kbit/s 8 8 24 16
ON
special, modied V.110 framing can be used (CRC error monitoring is included). synchronous bit rates of up to 64 kbit/s are supported. 16A modied V.110 framing can be used (CRC error monitoring and network independent clocking). 17A separate 8, 16 or 24 kbit/s frame can be used (CRC, 105/109 and network independent clocking). 18Simulated carrier function according to Recommendation V.13 (can be turned off). A separate 8 or 24 kbit/s frame can be used (CRC and network independent clocking).
15Also
14A
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105/109 Transfer
CRC
Network Independent Clocking ON
User Rate 512 kbit/s Frame Rate kbit/s 16 16 8
User Rate >512 kbit/s Frame Rate kbit/s 24 24 24
ON ON ON ON
ON ON
The end-to-end monitoring supervises the XB/XD signal path through the network. A V.110 framed port does this by counting errored frames. The CRC monitored ports count errored CRC blocks which include every bit of the user signal. Network independent clocking means that the users DTE equipment can provide timing for transmission data which is not frequency-synchronized to the network clock. The standard V.110 framing for low speed interfaces also supports the network independent clocking. The typical applications for the low-speed interfaces V.24/V.28 (0.619.2, 38.4 kbit/s and n x 3.6 kbit/s) are termination of point-to-point circuits in a data processing centre end point of point-to-multipoint circuits in the Tellabs 8100 network termination of V.110 formatted circuits The typical applications for the medium speed interfaces V.35, V.36 (9.638.4, 48, 56, and n x 64 kbit/s) are termination of point-to-point circuits in a data processing centre end point of point-to-multipoint circuits in the Tellabs 8100 network links for data multiplexers, PADs, LAN bridges and routers data links between two computers trunks of low or medium capacity data networks The typical applications for the high speed interfaces V35, V.36, HSSI (648448 kbit/s) are links for data multiplexers, PADs links for LAN bridges, routers data links between two computers trunks of low or medium capacity data networks The typical applications for the LAN module (642048 kbit/s) are LAN interconnection Low speed interfaces V.24/V.28 at rates n x 3.0 and n x 3.2 kbit/s may be used for access links to data networks using 6+2 (n x 3.2 kbit/s) or 8+2 (n x 3.0 kbit/s) signalling formats. Interfaces X.21 at rates 0.6, n x 1.2, 48, 64 and (n x 64) kbit/s may be used for X.21 access links to X.21 or X.25 data networks. In X.21 bis mode the X.21 interface may be applicable for a variety of applications with data multiplexers etc.
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The G.703 interface is mainly used for transfer between the Tellabs 8100 network and another transport network or switching system based on the G.700 Series ITU-T Recommendations. Some computers and data multiplexers may also be equipped with a 64 kbit/s G.703 interface.
2.5
Network Synchronization
Trunks use the synchronous octet interleaving; the buffer memories of the framed interfaces require that the average bit rate in the incoming signals is the same in all trunks (mesochronous clocks). The same requirement usually applies to the synchronous n x 64 kbit/s data interfaces (user access ports). Some data interface types allow the use of a plesiochronous clock in the user access ports. Tellabs 8120 mini node M is provided with an internal master clock, which gives timing to the cross-connect switch. The master clock can be locked to an external n x 64 kHz clock input an incoming n x 64 kHz clock of a trunk or channel interface If the master clock is not locked to any external reference timing, the clock operates in an internal mode with an accuracy of 30 ppm. The clock reference source is dened by a clock fallback list which can have up to ve clock entries. The following clock faults are recognized: loss of clock or signal loss of frame alignment at a clock interface far-end alarm concerning the loss of the reference clock of the node Two examples on the synchronization of Tellabs 8120 mini node M are given below.
Fig. 6 Independent Timing of Network Nodes
Nodes can be timed independently of one another. This practise can be used if an accurate station clock is available. In this practise the equipment uses exclusively the external clock input (EXT CLK).
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Fig. 7 Synchronization through Trunk
The usual practise with two pieces of equipment is to synchronize one to the external clock or to use its internal clock. The other piece is synchronized to the trunk coming from the master equipment. Both pieces should not be synchronized at the same time to the trunk coming from the other end because it causes a closed timing loop and corruption of data transfer. The same practise can also be used if there are many pieces of equipment in the same network. One piece is the master and the clock is distributed via the network to the other pieces. The network is normally locked to an external clock source via the network master equipment or to the internal clock of the master. The clock distribution network can make use of reserve routes. A change-over is based on the clock faults criteria. The selection of the reserve clock route must be done so that the change-over to a reserve route does not cause a closed timing loop.
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3 Operation
3.1 General
The functional block diagram is presented in Fig. 8.
Fig. 8 Tellabs 8120 Mini Node M Functional Block Diagram
The common functional blocks of Tellabs 8120 mini node M are G.704 framed interfaces IF1 and IF2 cross-connect block microprocessor block for control functions keyboard and display AC/DC power supply or DC/DC power supply
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The microprocessor block, the cross-connect block and the G.704 framing block are located on the main board. Two changeable interface modules for framed interfaces are located on the main board and connected through connectors to the framing block. The power supply is a separate board connected through cables to the main board and covered with a metallic shield to prevent the main current causing a hazard when the case is opened. The keyboard and the display are on the front panel. The channel board and two changeable user access interface modules are located over the main board and the framed interface modules. The cross-connect and microprocessor busses connect the channel board and the main board together.
3.2
G.704 Framed Interfaces IF1 and IF2

The G.704 framing block processes framed signals at 8448 kbit/s, 2048 kbit/s and n x 64 kbit/s. The block includes two independent transmission channels to carry data and also to provide an internal communication link of the Tellabs 8100 system. The transmission channel interfaces are independent of each other and they may, for example, be G.703 interfaces, optical interfaces, and, at certain speeds, also baseband interfaces. The framed signal which is carried on the transmission line is assembled and disassembled in the G.704 framing block. In the transmitting direction the Tx frame block creates a signal by mapping data from the X-bus into the correct time slots, adding frame alignment signal bits and the CRC check sum, and by generating the HDLC channel at a required position within the frame with the aid of the processor. In the receiving direction the Rx frame block searches the received signal for the frame synchronization word. When the synchronization is found, the Rx frame block can extract the data transmission time slots, check the CRC check sum, and recover and supply the HDLC channel to the processor. The frame structure and the use of the certain bits in the frame depend on the transmission speed. At 2048 kbit/s and 8448 kbit/s the frame structure is in accordance with G.704. A modied G.704 frame structure is used for other speeds. If required, it is also possible to remove the framing and have the channel to operate in transparent mode. In the G.704 framing block there are data buffers for the data transmission. The transmit buffers of the channels are used to store data so that there is always a time slot available to be transmitted by the Tx frame block. The transmit buffers also synchronise the phase of the transmitted frame with the phase of the X-bus and stuff idle data in the unused time slots of the frame. The receiving buffers of the channels store incoming data so that required time slots are always available for the cross-connect block. These buffers also form a exible buffer in order to compensate for minor momentary speed differences between the X-bus and the received signal. The length of the receiving buffers can be changed in accordance with the application requirements. For instance, in some cases a minimum connection delay is required whereas in plesiochronous operation slips should occur as seldom as possible.
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3.2.1
Frame and Multiframe Structure

The unit has two independent G.704 framed interfaces. The frame has the following three modes. 8448 kbit/s = 132 TS 2048 kbit/s = 32 TS n x 64 kbit/s = n TS The 2 Mbit/s and 8 Mbit/s frame structures conform with ITU-T G.704 Specication. The 8 Mbit/s frame structure is shown in Fig. 80 of Appendix 2 and the 2 Mbit/s frame structure in Fig. 81 of Appendix 2. For further details see Appendix 2. The 8 Mbit/s signal has four 2 Mbit/s groups (thirty time slots). The 2 Mbit/s frame has one signalling time slot (TS16), and in the 8 Mbit/s frame each group has its own signalling time slot (TS6770). The main features of the n x 64 kbit/s frame are the same as those of the 2 Mbit/s frame. The frame length is n time slots. Possible signalling bits are in the last time slot of the frame, or in TS16, if n 18. The framed interface lines primarily use the following time slots for XB channels.
8 Mbit/s 2 Mbit/s n x 64 kbit/s TS 532, 3465, 7198, 100131 TS 115, 1731 TS 1n-2 TS 115, 17n-1 Total 120 TSs Total 30 TSs Total n-2 TSs if n 17 Total n-2 TSs if n 18
The table of Multiframe Structure in Signalling Time Slot in Appendix 2 shows the G.704 multiframe structure of the signalling time slot. For the transmission of the XD channels the following time slots are used:
8 Mbit/s 2 Mbit/s n x 64 kbit/s TS 67, 68, 69, 70 TS 16 TS n-1 if n 17 TS16 if n 18
The trunk lines always use the G.704 compliant CRC check in order to detect errors in the received signal and to prevent alignment to an imitative frame alignment word. On the user access lines the CRC check can be turned off if the user equipment does not support the CRC frame structure. The CRC check is inserted into the different frame structures in the following way.
Frame 8 Mbit/s 2 Mbit/s n x 64 kbit/s Time Slot TS99 TS0/B1 TS0/B1 CRC Check CRC-6 CRC-4 CRC-4
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3.2.2
Buffers
In the transmit direction the buffer supplies time slot data from the X-bus to the frame to be transmitted. When the cross-connect block supplies data to the X-bus, it also adds information about the location in the transmitted frame where the data is to be placed. The unit stores the data in its transmit buffer in a position corresponding to the position of the time slot in the frame. The frame multiplexing circuits will fetch the data when they are transmitting the corresponding time slot. As it is possible to write the data from the bus to any time slot position in the buffer, the buffer must control that the write and read operations do not simultaneously address the same time slot. The transmit buffer length is two frames. The frame multiplexing block reads the rst frame area and the bus writes into the second frame area. This transmit buffer arrangement causes a delay of one frame (125 s). In the receiving direction the buffer supplies received time slot data from the demultiplexed frame to the X-bus. When the cross-connect block via the X-bus requests data from the interface block, it also species the time slot concerned. Usually, the phase of the received frame does not coincide with the frame phase of the X-bus; on the other hand, the receiver writes the time slot data into the Rx buffer clocked by the received frame. Therefore, the Rx buffer has to control that the read and write operations do not collide, in spite of speed uctuations and jitter. If the read and write addresses come too close, one of them has to be moved, in other words, centred. The centring is made by changing the read address, and the change is always one frame or a multiple of a frame. The centring causes a certain number of frames to be lost or retransmitted. Centring is required when equipment is powered up, when a received signal contains disturbances, or when the transmission is plesiochronous. If a plesiochronous system constantly exhibits a frequency difference in the same direction, the buffer has to be centred at regular intervals. The length of the interval depends on the frequency difference and on the buffer mode.
Frame Buffers The buffers have four operating modes.

Buffer Mode 4 Fr19 8 Fr 8 Fr/Split 64 Fr Rx Delay (Frames) 13 17 26 163 Tx Delay (Frames) 1 1 1 1 Usage Framed user access interfaces, n x 64 kbit/s trunks Special use Split trunk line components Special use, e.g. small slip rate in plesiochronous use
In a plesiochronous system the interval between the centring situations is:
19Fr
= frame = 125 s
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Buffer Mode 4 Fr20 8 Fr 8 Fr/Split 64 Fr
n x 64 kbit/s n x 8/df21 4 x n x 8/df 2 x n x 8/df 32 x n x 8/df
2048 kbit/s 256/df 1024/df 512/df 8192/df
8448 kbit/s 1056/df 4224/df
The 4 Fr buffer is the normal mode of the buffer. A buffer with a length of eight frames is used for split trunk operation. It may also be used for other applications; it should be used if, for example, unusually large uctuations have to be handled correctly or if the frame alternation has to be intact after the centring as well. The long buffer leads to a delay of up to 63 frames; thus, this buffer mode is recommended for special purposes only. The slip distance is very large in a plesiochronous system and the buffer is well suited for large frequency uctuations. This buffer mode can be used at 2048 kbit/s and n x 64 kbit/s. Multiframe Buffers In the transmitting direction the signalling data is directed through the same buffer as the time slot data. The signalling multiframe of the frame to be transmitted is synchronized to the multiframe clock of the X-bus. The cross-connect block supplies the frame signalling data, along with the other time slot data of the frame. The framing block generates a synchronization time slot in the rst frame of the signalling multiframe. Thus, the signalling data and the time slot data have equal delays in the transmitting direction. In the receiving direction the phase of the received signal multiframe usually differs from the phase of the X-bus multiframe. Thus, the received signalling data has to be buffered until the cross-connect block performs the cross-connect function for the data concerned. There are two alternatives for the multiframe buffer length: two and four multiframes. The multiframe buffer length depends on the selected length of the frame buffer.
Frame Buffer Mode22 48 frames 64 frames Multiframe Buffer Mode23 2 MFr 4 MFr MFr-Rx Delay 02 MFr 13 MFr MFr-Tx Delay 1 Fr 1 Fr
The time slot data and signalling data have separate buffers. Therefore, there are different delays in the processing of signalling data and time slot data. This means that the signalling data and the time slot data which are placed in a transmitted frame do not necessarily originate from the same frame.
20Fr 21df
= frame = 125 s = frequency difference between the signal received from the line and the receiving frequency generated by the master clock oscillator. 22The length of a frame is 125 s. 23The multiframe length is 2 ms.
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3.2.3
Split Trunk Lines

A split trunk line can be used to combine two parallel n x 64 kbit/s or 2048 kbit/s interfaces in order to increase the maximum number of time slots of a n x 64 kbit/s trunk interface. The time integrity of the time slots in the split trunk line is preserved even if the n x 64 kbit/s is connected through physically separated cables. The split trunk mode can be used for line speeds n x 64 kbit/s and 2048 kbit/s when a frame with CRC4 is used. The split trunk mode always requires long buffers (8 frames). One of the interfaces will function as a master and the others as slaves. Split components must have the same bit rate. The interfaces are synchronized to each other by their CRC4 multiframe structure. In the transmitting direction the interface transmit buffers and the Tx frame multiplexers are synchronized with the X-bus MSYN signal to transmit in the same multiframe phase. In the receiving direction the master interface sends information about its receiving buffer read phase to the slaves, which will centre their own receiving buffers to the same phase. This operation causes data time slots sent from a transmitting node in the same frame to be read together within one frame into the cross-connect block of the receiving equipment. Theoretically, the maximum delay allowed between lines in a split trunk line is 0.5 frames. Due to technical reasons, however, the maximum delay is 50 s. Each line of a split trunk line will handle its own signalling data. Those lines which carry one or more data channels with signalling data will use the last time slot, or TS16, if it is possible, as a signalling channel with a multiframe structure. It is not necessary to use a CAS time slot for lines that do not include data channels with signalling. When making cross-connection for a split trunk, a unidirectional channel from the control port of the master channel to the control port of the slave channel must be created. The port numbers for data ports of interfaces correspond to the interface numbers. In Tellabs 8120 mini node M the control port numbers are 20 for IF1 and 21 for IF2.
3.2.4
1+1 Protection
The interface can be 1+1 protected by another framed interface. In the protected mode both channels must have the same rate and framing mode settings. Framed interfaces working in the protected mode will look like one cross-connect port towards the X-bus. In the protected mode both channels transmit the same data signal coming from a buffer. Both channels use their own frame mux to create the frame structure. The receiving direction includes a change-over switch that selects the active receiver. Rx signal faults are classied into several categories. The switch uses fault categories to select the interface to be used. The fault categories are indicated in the fault table. For example, 1.x means rst category, the worst or most serious fault.
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Fig. 9 Protection Mode of Framed Interfaces
The operating modes of the change-over switch are normal operation prefer operation forced operation In normal operating mode the switch will automatically switch to the other interface if the Rx signal fault category (1, 2, 3, 4, 5, OK) of the active interface is continuously worse than the fault category of the other interface for a longer period than the given time delay. No switch-over operation is activated when the categories are the same for both interfaces. In prefer operating mode a switch-over is triggered if there is a difference between the interface fault categories. The better interface is switched into being active. In a situation with equal fault categories for both interfaces the switch selects the preferred interface. In forced operating mode the switch is forced to switch over without delay. Received data from the active interface is immediately connected to the X-bus. In this situation the Protection Switch Forced fault message with status MEI (maintenance event information) appears, and the red LED is turned on. A switch operating time delay is dened for the prefer and normal operating modes. The delay is dened as n x 10 ms, where n = 06000; in other words, the delay is 01 minutes. The delay denes the allowed fault duration before the switch is triggered to switch-over.
3.3
Operation of Framed Interfaces

Tellabs 8120 mini node M is connected to a transmission line through interface modules. The interface modules contain the analog components required for the interface and also the analog components needed for generating the input and the output clocks. The signals between the framing block and the interface module are digital signals which are converted to the transmission line level in the module. Line codes are coded/decoded in the framing block when modules of G.703 type or optical modules are used; in baseband modules the line coding is performed in the module. Each module type supports dened transmission rates which can be selected with the user interface. The codes and the available transmission rates are described in Technical Specications.
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The processor bus is connected to both interface module connectors. Through this bus it is possible to detect the module type and to read data regarding the module status, e.g. a missing incoming signal. Parameters which dene the module functions, e.g. the transmission rate and possible looping commands, can be selected through the bus. In the receive direction the interface module regenerates the coded signal received from the transmission line and transforms the signal to the digital level. The module monitors the level of the received signal; if it is too low or missing completely, the module sets an AIS signal to the framing block and at the same time activates a missing signal alarm via the processor bus.
Fig. 10 Data and Clock Processing in the Receive Direction
The receive direction clock is recovered from the data in the interface module. The clock is supplied to the framing block, which uses it to decode the line code and to demultiplex the frame. If there is no received signal, the interface module replaces the received clock with the transmitted clock. The receive clock in the V series modules is taken from the circuit 113 from line. The missing signal alarm with V series modules is based on detecting the incoming clock signal. The received clock from both framed interfaces is connected to the synchronization bus where the processor can select a desired clock to be used as a synchronization signal for the master clock of the equipment. The clock to the synchronization bus is disconnected if there is a received signal failure. The framing block generates the frame structure for the data in the transmit direction. The line code of the data is generated in the framing block for G.703 interfaces and for optical interfaces. The coded digital data is connected to the interface module where it is converted to a line level signal. NRZ data for baseband interfaces is connected to the interface module where it is coded and transformed into a line level signal.
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Fig. 11 Transmit Direction Clock and Data Generation at 8448 kbit/s
The transmit direction clock generation depends on the interface module and the transmission rate. In all cases the transmit direction clock is phase-locked to the C16M frame clock received from the X-bus. The transmit direction clock for 8448 kbit/s is usually generated by dividing the bus clock C16M by two. This divided clock is used to create the frame and to generate the output pulses in the coder. If the C16M clock is missing, the output clock is generated by using the oscillator of the interface module, which then is used to create the frame and to generate the output pulses in the coder. If the C16M clock is missing, a frame is transmitted, but the time slot data and possible multiframe signalling are set to AIS.
Fig. 12 Transmit Direction Clock and Data Generation at 2048 kbit/s
The transmit direction clock for 2048 kbit/s and 1088 kbit/s is generated by the phase-locked crystal oscillator of the interface module. The oscillator is locked to the C16M clock of the bus which is used to create the frame and to generate the output pulses in the coder. Even if the C16M clock is missing, the output signal is generated with the aid of the clock signal from the interface module crystal oscillator. The phase-locked oscillator will then be adjusted to its nominal frequency and the time slot data in the frame is set to AIS.
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Fig. 13 Transmitting Direction Clock and Data Generation in Baseband Modules
The clock which is used to create the frames for baseband modules is generated in the framing block by dividing the C16M bus clock by a programmable divider to the nominal transmission rate. This clock signal and the data to be transmitted are supplied to the module, where the phase-locked oscillator is locked to the clock. The clock, again, is generated by the framing block. The line coded data is then generated with the aid of the phase-locked oscillator clock signal. If the C16M clock is missing, the clock generated by the module is connected to the framing circuit. The output signal rate is adjusted to its nominal value, and the frame and a possible control channel are transmitted, but all other data is set to AIS. The transmit direction clock for V35-G704-SM and X21-G704-SM modules is generated by dividing the C16M clock by a suitable divider. This clock is used as the transmit clock of the module in circuit 115. The dividing process may cause some jitter to the clock in this case. If the C16M clock is missing, no signal or clock is sent from the module.
3.4
Unit Controller
The unit is controlled with an 80C186 microprocessor. The system program is stored on the board in two interchangeable EPROM memories. The application programs are stored in non-volatile FLASH memories; it is thus possible to update these programs without opening the case of the device. The non-volatile memory is also used to store the operating parameters and the serial number of the unit. In case of power interruption the unit is automatically reset to the conditions prevailing before the interruption, without specic parametrisation. The RAM memory of the processor operates as a working storage containing e.g. error counters and data buffers for the HDLC links and the frame control bus. The unit includes a multichannel analog-to-digital converter (A/D) which monitors the operating voltages and also the control voltage from the interface module connectors. The control voltage is, for instance, a voltage received from a baseband module controlling the baseband line power-off situation.
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3.5
Cross-Connect Block
The cross-connect block has the following main functions: cross-connection of XB and XD channels control of the cross-connect bus master clock oscillator of the unit interface for external clock input and output selection of a reference signal for the master clock oscillator selection of a clock signal for the external clock output The cross-connection is done in the switching matrix of the cross-connect block. The cross-connection bus contains approximately 1050 cross-connectable time slots (8-bit bytes). The bits from the interface blocks are collected by using this bus. The cross-connect switch combines the needed new bytes for the interfaces by using 8 kbit/s granularity. Usually, whole time slots or bytes are cross-connected. The delay caused by the cross-connection is one 8-kHz frame (125 s). The cross-connect block exchanges data with the interface units by placing a channel address on the X-bus which activates the data buffers of the corresponding channel. Received and transmitted data is carried on separate 8-bit-wide busses. The G.704 framing block receives from the cross-connect block the time slot address which directs the bus data transmission to one selected time slot at a time. The cross-connect block supplies the C16M bus clock through the X-bus. The C16M clock is also the central clock of the equipment; it is used to create clock frequencies for the transmitted signals. The bus supplies frame alignment and multiframe alignment signals to the frame buffers. Bus functions are also monitored by the interface blocks. When the interface is synchronized and the corresponding cross-connection is made, the unit will activate the IA Activity Missing alarm if it cannot receive its channel address from the bus. The interface blocks monitor the combined information formed by the bus clock and multiframe synchronization signal; if this information is missing, the unit will activate the Bus Sync Missing alarm.
3.5.1
Cross-Connection
The cross-connect block executes the cross-connection commands from the NMS or from the front panel user interface. The cross-connect commands are stored in a non-volatile memory. By means of cross-connection the data of the user access interface is placed in the selected time slots of the framed interface or in an another user access interface. Time slots from a framed interface can also be connected to freely selectable time slots of another framed interface. Thus, the data from the framed interface can consist of data from several interfaces, and some time slots can be unused. In this case the free TS data, which can be dened in the user interface, is placed in the unused time slots. The port is a description of interface properties for the cross-connection block. Every interface has one or more cross-connect ports. The port numbers for framed interfaces are 1 and 2, corresponding to the interface numbers IF1 and IF2. These port numbers are used to specify the port used by the payload data of the interface. The port numbers for user access interfaces are dependent on the used channel board and user access interface modules. Other port numbers are reserved for control channels.
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The cross-connection ports are dened by using interface denition, TS denition and a possible bit mask (n x 8 kbit/s connections). If need be, the cross-connection commands can include the signalling bits. The bit mask means a combination of eight bits, where state 1 indicates an 8 kbit/s channel of a time slot which is connected; state 0 means capacity left free. The mask can also be presented in hexadecimal format. The cross-connect types supported by the unit are 1. 2. Bidirectional connection: interface/(TS/bits) interface/(TS/bits) Unidirectional connection: interface/(TS/bits) interface/(TS/bits)
The n x 8 kbit/s and n x 64 kbit/s groups mapped by the interfaces are called the XB channel. The XB channel can be a combination of 64 kbit/s and 8 kbit/s signals. If the interfaces are equipped with signalling or control signals, they are either mapped to the XB channel or to the corresponding signalling bits (n x 500 bit/s) of the XD channel. In the latter case the signals are mapped to the G.704 compliant multiframe of the 2 or 8 Mbit/s trunk. The n x 500 bit/s signalling bits are called the XD channel of the interface. The number of the signalling bits depends on the capacity of the XB channel. Signalling bits are reserved for the XB channel in the following way.
XB Capacity TSn/B1B8 64 kbit/s TSn/B1B4 32 kbit/s TSn/B5B8 32 kbit/s XD Capacity 4 bits (a, b, c, d bits in G.704 structure) 2 bits (a, b) 2 bits (c, d)
The a, b, c, and d bits of the XD channel in the G.704 multiframe correspond to the XB channel time slots in the G.704 frame. The capacity reserved by XB and XD channels is determined by the interface type and the user requirements. Four signalling bits are reserved for each time slot. Even if only some of the bits are needed, all four bits are cross-connected and transferred to the far-end channel interface. Port Locking After the operator has changed the parameters of the interface to the desired state, the parameters of the interface must be locked. This means that the properties of the port are transferred to the cross-connect block which needs the information for capacity allocation. The cross-connect cannot be made before the port is locked, and the port cannot be unlocked if there are any cross-connections made to the port. The parameters of the interface can be changed if the port is in unlocked state. Split Trunk Connection In split trunk mode there is always a master and a slave. The data buffer of the slave follows the action of the master interface through a control channel created by the cross-connection. The control channel is made by unidirectional connection command, and its direction is from master to slave. In Tellabs 8120 mini node M the control port number is 20 for IF1and 21 for IF2. Protection Connection The framed interfaces in protected mode will look like one cross-connect port towards the X-bus. A cross-connect command made to one port causes a cross-connection to both interfaces. The port number for the protected ports is 1.
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3.5.2
Master Clock Synchronization

The 16 MHz master clock of the equipment is used for generating the timing of the cross-connect bus. The timing consists of 16 MHz 8 kHz frame synchronization 500 Hz multiframe synchronization The 16 MHz clock is also used to generate the Tx clock of each data interface. The master clock is usually synchronized to an incoming data signal (generally a 2 Mbit/s trunk, see 2.5 Network Synchronization on network synchronization). The clock of the desired interface is derived by using a separate sync clock bus. The cross-connect block controls the status of the synchronization clock and tells the required interface to connect the received clock of the interface to this bus.
Quality Level (QL) of Clock Signal When a HDLC channel is used at interface (IF1IF3) and the Message Sending option is activated, Tellabs 8120 mini node M may receive messages from its neighbour node. Some of these messages include information about the clock signal to which this neighbour node is synchronized. This information is called Quality Level (QL) and it has been dened as numerical values from 1 to 7 where 1 is the highest and 6 the lowest one (7 means do not use this clock; the gure is used to prevent timing loops). If for some reason the neighbour node changes its clock signal used for synchronization, the QL of this new reference clock is transmitted via the HDLC channel. Tellabs 8120 mini node M polls these QL values from all the interfaces and thus can select the best available clock signal. The clock signal which has the highest QL and whose status is OK is the one to which the master clock is synchronized. If clock signals have the same QL, the clock to which it is synchronized is the one with the highest priority according to the fallback list. Whenever all the clock signals are available for synchronization (the status of the clocks is OK), there is no activated alarm related to the master clock even if the last entry of the fallback list would be used. The QL of the clock signal from an interface which does not use the HDLC channel is xed to value 1. The QL of the internal clock is normally xed to 6. Clock Fallback List The clock fallback list denes the interfaces which can be used for synchronization. It also describes the priority order for situations where two or more clock signals have the same QL. The list can have up to ve entries. The form of the list is 1. IF_ 2. IF_ 3. IF_ (Internal) The last entry is automatically followed by the internal state.
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3.6
Operation of Unframed Channel Interfaces IF3-IF6

The channel interface board accesses unframed user signals at rates 0.6 kbit/s8448 kbit/s. It supports four independent data transmission interfaces. The board can take two interface modules, both supporting two channel interfaces. The available interface types support V.24, V.35, V.36, X.21, G.703 (64 kbit/s), HSSI or 10Base-T interfaces. Note that the HSSI-M interface module and Mini LAN Module support only one channel per module. User signals at bit rates below 64 kbit/s are rate-adapted in accordance with the frame structure V.110/X.30. The V.110 signals are transported as 8, 16, 32 or 64 kbit/s across the network. The n x 64 kbit/s signals are transported at the user rate across the network. Whenever required, the equipment supports end-to-end CRC supervision of the user signals and plesiochronous data timing. At rates below 64 kbit/s the CRC and plesiochronous timing features are supported in the V.110 frame. At higher rates an extra transmission capacity of 8, 16 or 24 kbit/s is required across the network. Asynchronous start-stop signals are supported at bit rates below 256 kbit/s. The basic functional blocks of the channel board are data formatting circuitry bus interfaces interface modules Data Formatting Circuitry The data formatting circuitry determines the majority of the characteristics of the data interfaces provided by the channel board. The data formatting circuitry is described in more detail in 3.6.1 Data Formatting Functions. Bus Interfaces The bus interfaces perform the adaptation between the data formatting circuitry and the data bus and the address bus of the main board of the equipment. There are also data and address busses for the microprocessor controls. The master clock of the equipment can be synchronized to the clock received from the unframed interfaces through the sync bus. Interface Modules Tellabs 8120 mini node M accesses the physical interfaces through the interface modules. The interface modules convert the CMOS level data, timing and control signals to balanced or unbalanced V.11, V.28, V.10, or G.703, according to the requirements for each interface type. The receiver circuits convert the incoming signal levels to CMOS level data, clock and control signals. The interface module monitors the existence of the received signal level; if the signal is missing, a power off signal indication is given to the unit controller. The interface signal coding (e.g. G.703 co- and contradirectional operation, or sync/async converter) is performed in the channel board. There is an additional 16-bit input buffer on the V24-DTE-M module. This buffer can be used if the buffer length in the base unit is not sufcient.
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3.6.1
Data Formatting Functions

The data formatting circuitry provides the main data processing functions: rate adaptation and framing CRC monitoring V.13 simulated carrier bit rate generation user interface signal coding (e.g. G.703) sync/async conversion V.54 and X.21 test loops test pattern generation and error counting
Fig. 14 Functional Block Diagram of Channel Board
Rate Adaptation and Framing
Bit Rates <64 kbit/s Data bit rates 64 kbit/s are, using the ITU-T Method V.110, rate-adapted to 8, 16, 32 or 64 kbit/s which can be handled by the cross-connect block and the routing tools. The V.110 frame is transparently transported through the network and can be used for the end-to-end monitoring of the channel quality.
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The V.110 frame offers three channels for the transfer of the control signals. They are called SA, SB, and X. The channel SA carries the signals 108/107 and the channel SB the signals 105/109. The channel X carries both the signal 106 and the far-end alarm. The signal 106 is either derived locally from the signal 105 or from the channel X received from the far-end. When 105 is turned on, the locally generated 106 signal is delayed until 105 is sampled by the framer. This generates the minimum 106 delay which guarantees that 109 is turned on before the rst data bit is received at the far end. When the 107/108 transfer is not required, both SA and SB (SA+SB = S) may carry the 105/109 or C/I signal, enabling the minimum control signal delay. The S signal is sampled once for each byte of user data. In the management menus this mode is called V.110S or X.30, and the basic V.110 mode simply V.110. The V.110 or V.110S congurations use bit oriented data buffering with a 2 bit jitter/wander margin. The byte oriented data buffering is used in X.21 applications or when octet timing is desired. The byte oriented buffering and minimum control signal delay is called X.30 as the mode conforms to the CCITT Recommendation X.30. User data rates < 600 bit/s are transferred by sampling at rate 4800 bit/s. Rates 0.6 kbit/s, n x 1.2 kbit/s (up to 38.4 kbit/s), and 48 kbit/s are supported in V.110, V.110S and X.30 modes. User rates n x 3.0 kbit/s (data network formats 8+2 bits), n x 3.2 kbit/s (data network formats 6+2 bits) and n x 3.6 kbit/s (including rates 3.6, 7.2, 14.4 and 28.8 kbit/s) are supported in modes V.110 and V.110S. At 56 kbit/s both ITU-T V.110b and V.110c (b, c refer to V.110 table 7b and 7c) framing is supported. Bit Rates n x 8 kbit/s At rates 8, 16, 32 kbit/s the user data is transferred in one, two or four bits of a time slot. At rates 72 and 80 kbit/s the data is transferred using one full time slot and one or two bits of another one. Rates 144 and 160 kbit/s need two full time slots and three or four bits of a third one (144 kbit/s uses one extra bit due to an ASIC restriction). No data framing is needed for the data transfer. The rates 48 kbit/s and 56 kbit/s are selected as 6 x 8 and 7 x 8 kbit/s in the management menu. Bit Rates n x 64 kbit/s At n x 64 kbit/s (rates 642048 kbit/s) the unframed user data is transferred in 132 time slots. The data buffer length may vary from three to sixty-four bytes. The nominal buffer length selection allows for 18 s, or at minimum one byte of jitter and wander. Bit Rates n x 64+8 kbit/s The n x 64+8 kbit/s rate is basically intended for the T1 rate 1544 kbit/s. Certain other n x 64+8 kbit/s rates are also supported. This mode uses n full time slots and one extra bit.
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CRC Monitoring The channel board can support end-to-end CRC monitoring of the user data. The CRC-4 procedure used is similar to the one for the G.704 2-Mbit/s frames. At rates < 1.2, n x 1.2, n x 3.0, n x 3.2, and n x 3.6 kbit/s, the CRC check sum is transferred on the last ve bits of frame alignment signal of the V.110 or X.30 frame. A modied V.110 frame is used at rates 48 and 56 kbit/s. When transferring the CRC check sum, the frames are called V.110M or X.30M, because the corresponding ITU-T frames do not support CRC monitoring. At n x 64 kbit/s and n x 64+8 kbit/s the CRC check sum is transferred end-to-end in a proprietary Martis frame, using 8 kbit/s extra XB capacity. The end-to-end performance monitoring is based on the end-to-end CRC monitoring, when activated. Channel associated end-to-end CRC monitoring is the only way to get accurate performance characteristics for a channel. Performance data is expressed in terms of G.821 parameters. Control Signals The unframed interfaces support control signals for the following user channels: 105/109 transfer at all bit rates (X.21bis) 108/107 transfer at V.110 based frames (X.21bis) 106 locally generated 106 transfer from the far-end (V.110 only, X.21bis) C/I at X.21 interfaces and bit rates 0.6, n x 1.2, 48 and n x 64 kbit/s The control channels can be transferred in several ways, depending on the user bit rate. The SA, SB and X bits are normally used (selection V.110, X.30) with V.110, V.110M, X.30, X30M frames. The V.13 simulated carrier or an 8 kbit/s channel are used at n x 8 and n x 64 kbit/s rates. The 8 kbit/s channel requires additional transmission capacity but it offers a continuous channel which is, for example, required for X.21 applications. V.13 Simulated Carrier The V.13 simulated carrier is an inband transfer method which does not require extra capacity. When 105 is turned off, the user data is substituted by a pseudo random pattern. When 48 bits of that pattern have been received, 109 is turned off and the user data (104) is blocked to off state. When 105 turns on, the pattern generator input is changed from 1 to 0 for 8 bits. After that 106 turns on, and the channel is ready for the transfer of the user data. If, due to transmission errors, the receiving end misses the turn on sequence, it will automatically return to on state when more than 31 errors have been detected in the pseudo random pattern during a certain time period. 106 Delay Normally, the minimum 106 delay required to guarantee proper operation is used. Whenever required, an additional delay may be selected in the range of 88000 bits. The delay is expressed in time units at the management interface.
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105 Supervision In some applications 105 should continuously stay in on condition. If desired, the channel board can monitor the 105 state and generate an alarm if 105 goes off. Bit Rate Generation A variety of bit rates is required for the unframed interfaces. The data timing signals are derived from the 16896 kHz system clock by built-in programmable frequency synthesisers. There is a synthesiser for each channel and each transmission direction. Timing Sources Depending on the conguration, the timing signal for the incoming data (Tx direction) can come from the user equipment or from the clock source of the channel board. The clock for the outgoing data (Rx direction) can come from the channel board or it can be taken from the Tx clock received from the user. Plesiochronous Clocking When the user data clock cannot be synchronized to the master clock of Tellabs 8120 mini node M, the plesiochronous operation (the same nominal bit rate) is required. The equipment supports the transfer of plesiochronous clocking at all bit rates except for at 8, 16 and 32 kbit/s. Plesiochronous transfer is supported in the standard ITU-T V.110 frame at rates n x 1.2, n x 3.2, and n x 3.6. A Martis modication of V.110 (V.110M) also supports plesiochronous clocking at n x 3.0, 48 and 56 kbit/s. An extra 8 kbit/s channel with the Martis frame is required at rates n x 8 kbit/s and n x 64 kbit/s. The 8 kbit/s channel supports both CRC monitoring and plesiochronous timing at bit rates of up to 512 kbit/s. With rates above 512 kbit/s plesiochronous clocking requires a 24 kbit/s channel. The V.110 method of transferring the data phase and stufng is used at all bit rates. The synthesisers operate in a digital PLL mode with slight jitter ltering of the input clock before phase comparison with the system reference clock. At the receiving end the synthesiser adjusts its phase according to the value received from the far-end. The phase adjustments take place in small steps in order to minimize the phase jitter amplitude and frequency spectrum width. With plesiochronous clocking the V.110 data buffer operates in bit mode. At n x 64 kbit/s rates the data buffer operates in a so-called frame synchronous mode where the data transferred during one X-bus frame form a block. The stufng bits are deleted and inserted at the border between two blocks. Async/Sync Conversion The asynchronous/synchronous converter samples the incoming signal at 16 times the user rate. The converter recognizes the start-stop pattern which may have start-stop bits and 6, 7, 8 or 9 data bits. Each detected erroneous pattern start-stop is considered as an input signal code error.
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In case of overspeed, the stop bits are deleted at certain intervals. The receiving side adds the deleted stop bits and compensates for the overspeed by shortening the stop bits of the eight consecutive characters. The method allows for 1.25% overspeed. At underspeed additional stop characters are inserted. In extended operation mode, the stop bits can be deleted from every fourth character enabling 2.5% overspeed. The async converter can be used at bit rates 600 bit/s64 kbit/s, 128 kbit/s and 256 kbit/s. At bit rates below 600 bit/s the async converter is by-passed and the user data is sampled at the rate of 4800 bit/s.
3.6.2
Data Interfaces
The interface signals of V.24/V.28, V.35, V.36 and X.21 interfaces are NRZ coded. Data and control signals can change their states at the edge of a clock period. The clock signal has a falling edge at the beginning of a period and a rising one in the middle of the period. The interface modules convert the CMOS level signals to appropriate interface signals.
Interface Module Signal Levels Signal Name Interface Type V.24/V.28 103 104 105 106 107 108 109 113 114 115 140 141 142 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.35 V.35 V.35 V.28 V.28 V.28 V.28 V.28 V.35 V.35 V.35 V.28 V.28 V.28 V.36 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.28 V.28 V.28 X.21 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 HSSI TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612
The data and clock signals for G.703 outputs come as positive and negative CMOS level pulses from the base unit. By the aid of drivers and transformers the control signals are converted to G.703 signals. The G.703 input signals are converted to CMOS signals using comparators.
3.6.3
Timing Modes
The clocking mode of data interfaces depends on the type of interface, on the type of the interfaced equipment and on the operation mode. The user clock may be considered to be locked to the network timing source if
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1. 2. 3.
the user equipment uses the clock supplied by the network interface the user system and the network use the same timing source, e.g. a national timing distribution network both the user system and the network are locked to the timing source according to the CCITT Recommendations G.811 and G.823
V Series Interfaces In most cases the unframed V series interface (V.24/V.28, V.35, V.36) is connected to a DTE as if it were a data modem (DCE). The data interface is clocked from the network. The clocking method can be used when the transfer delay between the DCE and DTE is below 0.15 bit (L < 30/(bit rate) m); bit rate in Mbit/s. The timing mode is called synchronous 114/115. Data in the direction DCE to DTE (104) is clocked by the timing signal 115. Data in the direction DTE to DCE (103) is clocked by the timing signal 114 from the DCE (IF module). At longer DTE-DCE distances and in applications where the DTE terminates a data circuit with clock looping at the far-end, or it is clocked by a timing source locked to the same source as Tellabs 8120 mini node M, the clock 113 is used in the direction DTE-DCE instead of 114. The signals in the direction DTE-DCE may contain jitter and wander when compared to the DCE-DTE timing. The timing mode is called 113/115 mesochronous. Data in the direction DCE to DTE (104) is clocked by the timing signal 115. Data in the direction DTE to DCE (103) is clocked by the timing signal 113.
Fig. 15 Contradirectional Synchronous and Codirectional Mesochronous Timing of an Unframed Data Interface in DCE Mode
Fig. 16 Contradirectional Synchronous and Codirectional Mesochronous Timing of an Unframed Data Interface in DTE Mode Tellabs 8100 Managed Access System Tellabs 8120 Mini Node M Operating Manual
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When interfacing a DCE, the interface module may operate either as a DCE (signals cross-connected in the interface cable) or as a DTE (without signal cross-connection in the interface cable). The timing signals may, in contradirectional mode, come from the DCE to the interface module (cases 115/114 EXT or 115 EXT), or, in codirectional mode, from both the DTE and DCE (115/113). Currently, only the V.24 DTE interface is available.
Fig. 17 Codirectional Plesiochronous Timing of an Unframed Data Interface
A data source (DTE or DCE) which cannot be synchronized to the Tellabs 8100 network is accessed using plesiochronous timing. In plesiochronous mode only codirectional timing is supported. Asynchronous V Series Interface The asynchronous operation is supported at bit rates of up to 256 kbit/s. The timing signals are switched off in the asynchronous mode. X.21 Interface
Fig. 18 Timing of an X.21 Unframed Data Interface 22030_12 2013 Tellabs. Tellabs 8100 Managed Access System Tellabs 8120 Mini Node M Operating Manual
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Only one clock signal is used in X.21 mode. The clock comes from the interface module or towards it. The clock is always locked to the same source as the clock of Tellabs 8120 mini node M. When required, octet timing may also be used. G.703 Interface
Fig. 19 Timing of a 64 kbit/s G.703 Unframed Data Interface
The G.703 interface at 64 kbit/s supports co- and contradirectional operation. Octet timing is also supported.
3.6.4
Rate Adaptation and Mapping

The frame structures used are described in Appendix 1. The signals and control signals in the channel board are rate-adapted and mapped as follows.
Rate Adaptation and Mapping at Bit Rates 48 kbit/s User Rate kbit/s < 0.6 0.6, 1.2, 2.4 0.6, 1.2, 2.4 4.8 4.8 9.6 9.6 19.2 19.2 38.4 38.4 3 6 12 24 3.2 Rate Adaptation Method V.110 V.110 X.30 V.110 X.30 V.110 X.30 V.110 X.30 V.110 X.30 V.110 V.110 V.110 V.110 V.110 XB Mapping kbit/s 1x8 1x8 1x8 1x8 1x8 2x8 2x8 4x8 4x8 8x8 8x8 1x8 2x8 4x8 8x8 1x8 Control Signals SA, SB, X SA, SB, X S SA, SB, X S SA, SB, X S SA, SB, X S SA, SB, X S SA, SB, X SA, SB, X SA, SB, X SA, SB, X SA, SB, X Plesiochronous Clocking No No No Yes No Yes No Yes No Yes No Yes Yes Yes Yes Yes
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User Rate kbit/s 6.4 12.8 25.6 3.6 7.2 14.4 28.8
Rate Adaptation Method V.110 V.110 V.110 V.110 V.110 V.110 V.110
XB Mapping kbit/s 2x8 4x8 8x8 1x8 2x8 4x8 8x8
Control Signals SA, SB, X SA, SB, X SA, SB, X SA, SB, X SA, SB, X SA, SB, X SA, SB, X
Plesiochronous Clocking Yes Yes Yes Yes Yes Yes Yes
End-to-end CRC monitoring can be supported at all bit rates mentioned above. The CCITT/ITU-T Rec. V.110 and X.30 do not support CRC monitoring. The frame type is renamed V.110M, or X.30M when CRC is activated.
Rate Adaptation and Mapping at Bit Rates 48 kbit/ User Rate kbit/s 48 48 56 56 56 64 64 72 72 80 80 144 144 160 160 N x 64 N x 64 N x 64 N x 64 Adaptation Method24 V.110 V.110M V.110/7b V.110/7c V.110M MartisDXX MartisDXX MartisDXX MartisDXX MartisDXX MartisDXX MartisDXX MartisDXX XB Mapping kbit/s 1 x 64 1 x 64 1 x 64 1 x 64 1 x 64 1 x 64 1 x 64+ 8 + 8 1 x 64+1 x 8 1 x 64+1 x 8+ 8 + 8 1 x 64+2 x 8 1 x 64+2 x 8+ 8 + 8 2 x 64+3 x 8 2 x 64+3 x 8+ 8 2 x 64+4 x 8 2 x 64+4 x 8+ 8 + 8 N x 64 N x 64+ 8 + 8 N x 64+ 8 + 8 N x 64+ 24 Control Signals SA, SB, X SA, SB, X SA, SB, X SA, SB, X SB SB SB SB SB SB SB SB CRC Support No Yes No No Yes No Yes No Yes No Yes No Yes No Yes No Yes Yes Yes Plesiochronous Clocking No Yes No No Yes No Yes No Yes No Yes No Yes No Yes No Yes N 8 No N > 8 Yes N > 8
24V.110/7b refers to CCITT Rec. V.110 Frame Table 7b, and V.110M/7c is a slightly modied V.110 frame. MartisDXX is a V.110 (56 kbit/s) like Martis specic frame. 8, 16 denotes extra capacity carrying CRC with plesiochronous timing control. SA, SB and X refer to SA, SB, X bits in the frame.
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User Rate kbit/s 1544 1544 1544
Adaptation Method24 MartisDXX MartisDXX
XB Mapping kbit/s N x 64+8 N x 64+8+ 8 + 8 N x 64+8+ 24
Control Signals SB SB
CRC Support No Yes Yes
Plesiochronous Clocking No No Yes
At all data rates the channels can support simulated carrier in accordance with V.13 for transfer of the 105/109 signal. V.13 is mostly used at rates n x 64 kbit/s.
3.6.5
Cross-Connection of Unframed Interfaces

The cross-connection ports are dened by using interface denition, TS denition, and a possible bit mask (n x 8 kbit/s connections). In some cases an unframed interface can be dened only by using the interface denition (in Tellabs 8000 manager only). The rst time slot of a port denition of an unframed interface is always TS0. The bit mask means a combination of 8 bits where state 1 indicates an 8 kbit/s channel of a time slot which is connected; state 0 means capacity left free. The mask can also be presented in hexadecimal format. The entire capacity of the unframed interface must be connected in order to ensure the proper function of the interface. The unframed interface can be provided with a control channel in some cases. Then the control channel must be connected as well. Many interface types can produce n x 8 kbit/s capacity even when the data speed in the user interface is n x 64 kbit/s. For example, an unframed n x 64 kbit/s connection with end-to-end CRC checking needs 8 kbit/s additional capacity in the XB channel. When the XB capacity of the unframed interface is exactly n x 64 kbit/s, the n x 8 kbit/s cross-connection is not needed. 4856 kbit/s data interfaces after V.110 rate adaptation, for example, need 64 kbit/s XB capacity. All low rate data interfaces (19.2 kbit/s) need n x 8 kbit/s cross-connection. When making connection to the unframed interface which has such control bits as CRC checking, the control bits are the last bits of the port. If the data uses the whole n x 64 kbit/s capacity (whole time slots), the control bits are the lowest bits of the next time slot. When the unframed interface is connected to the framed interface and a part of the full capacity consists of n x 8 kbit/s portions, a bit mask must be used for the connection of the n x 8 kbit/s portion. The control bits can be connected to any usable time slot and bit in the framed interface.
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Fig. 20 Example of Cross-Connection
The gure above shows an unframed interface IF3 with a bit rate of 144 kbit/s and control channel with 2 x 8 kbit/s (in all 160 kbit/s) connected to a framed interface IF1 which has the G.704 frame structure. The unframed port is specied as capacity 2 x 64 kbit/s and 4 x 8 kbit/s, which means two time slots and four bits. The rst time slot of the unframed interface is TS0. TS0 and TS1 of interface IF3 are connected to TS2 and TS3 of IF1. This can be made with the TS pair or TS area commands. In the TS pair command one time slot from both interfaces is dened, and the cross-connection is created between these time slots. In the TS area command the rst and the last time slot of an area with equal amount of time slots in both interfaces are dened, and the cross-connection is made between these areas. The last four bits of the unframed interface (two payload bits and two control bits) in TS2 are connected to the TS4 of the framed interface with the TS bits command. In the TS bits command the time slot and the bit mask for both the interfaces are dened, and the cross-connection is made between the unmasked bits. The control bits are automatically connected when the Connect whole port command in Tellabs 8000 manager is used.
3.7
Test Resources
Tellabs 8120 mini node M has many functions to indicate a defect in the operation of the equipment or in the data transmission. Some tests are performed when the power is switched on, some of them are running as background processes, and some of them are activated by the user. In the following chapters the tests are grouped to equipment tests, like the control of the voltages of the power supply, and to interface tests, by which the quality of data transmission can be controlled and the failure localisation in fault conditions can be performed. The type of the user-activated tests depends on the user interface. Usually, tests can only be activated through the service computer or the Tellabs 8000 manager network management system. In Tellabs 8120 mini node M, however, some tests can be activated through the front panel user interface. If the equipment is connected to Tellabs 8000 manager, it is possible to activate the test resources for the specied circuits in the desired place in the network.
3.7.1
Equipment Test
When the equipment is restarted after a reset, some start-up tests are executed. For instance, the correct starting of the main oscillator and the condition of the cross-connect RAM memory is checked. The equipment is not allowed to start other processes if these things are not in order.
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When the equipment is running, many tests are executed as background processes. The uP memory test and the data buffer test are checking the condition of certain components of the equipment. The uP memory test checks the EPROM, RAM and ash memories, and the data buffer test checks the Tx-ram and the Rx-ram memories of the framed interfaces. The tests run continuously. The results can be read with the service computer. A detected fault situation causes an alarm. The reason for the alarm can be traced using the user interface, or a service computer, if available. The equipment has capability to measure the voltages generated by the main power unit. The measurement process runs continuously and the results can be read using the service computer. Values that are too low will cause an alarm. The cross-connect bus test is also running as a background process for locked interfaces. This test checks the cross-connect data busses and some parts of the ASIC circuits. A failure of the test causes the IA Missing alarm for the failed interface.
3.7.2
Test of Framed Interfaces
G.821 Statistics To control the quality of the data transmission of the framed interfaces, the signal statistic values according to the ITU-T G.821 Specication are supported in both framed interfaces separately. Near-end and far-end statistics: total time (seconds) unavailable time (seconds) errored seconds severely errored seconds (10 -3) degraded minutes (10 -6) Error Counters The number of the following events can be read and cleared by the user interface in both framed interfaces separately in order to check the reason for poor quality, or to search the fault of the transmission line: code errors number of G.704 frame losses number of frame synchronization word errors number of CRC block errors buffer slips The count time of the counters is from the last reset of the counters or from the last reset of the equipment. In some cases all the values are not available; for example, the V.35 interface does not use coding in the transmission, and for this reason the code errors are not counted.
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Test Loop Functions The loops and measurement points are used to nd a faulty section of the line and to detect the faulty transmit or receive direction. When the framed interface is looped, all data circuits going through the interface are looped. The equipment includes a loop time-out control which will turn off a loop when the time dened by the user has come to an end.
Fig. 21 Loops of a Framed Interface
Interface Loop The following signals are activated during the interface loop. Tx data of the interface module is looped back to the receiver of the interface. Tx clock is looped to the Rx clock. AIS is transmitted to the line. Looped data is connected back to the demultiplexer. The type of the module determines the point where the loop is created in the module. In most cases, due to technical reasons, the loop is not made by using a signal with line level. The loop will, however, always test the control bus of the interface module, the connectors, and a part of the module logic. The line coder and decoder, as well as the frame multiplexer and demultiplexer, are also tested in the loop. There should be no other faults in the unit fault list when the loop is created. Equipment Loop The following signals are activated during the equipment loop.
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Tx data from the G.704 multiplexer (before the interface module) is looped back to the demultiplexer. AIS is transmitted to the line. Looped data is connected back to the frame demultiplexer. The equipment loop is made in the unit. This loop tests the frame multiplexer and demultiplexer. Neither the line coder, the decoder nor the interface module are included in the loop. It is also possible to detect faults in the transmitting and receiving buffers. If no problems are detected with the equipment loop, it is suggested that the user perform a test with the interface loop to ensure that the module is in order. Line Loop The following signals are activated during the line loop. Rx data, received by the interface module, is looped back to the interface output. The received clock signal is used as the transmitter clock. AIS signal is connected to the X-bus instead of the received signal. The interface module, the line coder, and the decoder, as well as the frame demultiplexer and the multiplexer, can be tested from the line connector of the module with the line loop test. When it is used, the HDLC controller works with the line loop. All other bits are looped back to the interface. Remote Line Loop The remote line loop operates in the looped unit in the same way as the local line loop. The remote line loop is activated from the unit at the other end of the line. The loop is made via the HDLC channel, and the control channel will continue to operate even when the remote line loop is active. The status of the looped unit can be checked with the user interface. When the loop is made, the yellow LED of the unit controlling the loop is switched on, and the yellow LED of the looped interface is also lit. The whole line can be tested with the remote line loop. Measuring Point A 75 G.703 type coaxial cable measuring point is provided on the back panel of the unit. The measuring point is isolated with a transformer, but the connector body is connected to the unit ground. Through the measuring point it is possible to measure the input and output signals of both framed interfaces IF1 and IF2, as well as the corresponding clocks. The choices are Rx data after the interface module but before the frame demultiplexer Rx clock Tx data after the frame multiplexer but before the interface module Tx clock The signal to be measured is selected with the service computer in the General Unit Parameters window. The selection can also be made with the front panel user interface in Tellabs 8120 mini node M. This selection is stored in the non-volatile memory of the unit so that the selection is also retained after a possible power interruption.
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The data signal of the measurement point is HDB3 coded and independent of the type of the interface module and the coding of the data interface signal. The signal levels and formats are in accordance with G.703. The loops and the measurement point can be used to detect a faulty Tx and Rx direction and to pinpoint a faulty line.
3.7.3
Tests of Unframed Interfaces
G.821 Statistics Every unframed interface has its own group of counters when the V.110, X.30 or the Martis framing is activated with the CRC transfer. The available circuit performance values are total time (seconds) unavailable time (seconds) errored seconds severely errored seconds degraded minutes With these values the quality of the data transmission can be controlled in accordance with the CCITT G.821. The values can be read and cleared with the user interface separately. Error Counters The channel board can count the following event numbers by using the software and the hardware counters. These event numbers can be read and cleared by user interface, each interface separately: number of V.110 frame losses (the frame from the net) (the frame of XB channel) number of multiframe losses (the frame from the net) number of frame word errors (the frame from the net) number of CRC block errors code errors in the user interface (G.703, start-stop format) buffer slips and adjustments Test Loop Functions To nd the places where problems might occur in the unframed interfaces, there are test loop functions which can be activated separately for each interface with the service computer or with the front panel user interface. All loops have a separate time-out counter which is adjustable by the user. The counter deactivates the loop when the set time has expired. The V.54 loops supported by the equipment can be limited or even disabled with the user interface. The V.54 loops also have special congurable values, adjustable to seconds, which will turn off a loop when the dened time has come to an end. A loop activated to an unframed interface only affects the data circuit which goes through the involved circuit.
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Fig. 22 Loops of Unframed Interface
Interface Loop The following signals are activated during the interface loop: The Tx data of the interface module is looped back to the receiver of the interface. The Tx clock is looped to the Rx clock. The looped signal is connected back to the cross-connection. The operator can activate an interface loop which is close to the physical user interface back towards the network. When this loop is activated, it is possible to test the correct function and cross-connection of the unframed interface by connecting measuring equipment to the framed interface to where the looped interface is cross-connected, or by connecting the data measuring equipment to the remote end of the circuit. Line Loop The following signals are activated during the line loop: Rx data, received by the interface module, is looped back to the interface output. AIS signal is connected to the X-bus, instead of the received signal. A line loop can be activated close to the X-bus interface towards the user interface. If some of the framing formats are used, the frame multiplexer and demultiplexer, as well as the CRC circuit, are included in the loop. By activating the line loop it is possible to test the whole interface from the line connector of the module.
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Local Loop and Remote Loop The unframed interfaces are equipped with the V.54 test loop functions supporting the local loop (loop 3, LL) and the remote loop (loop 2, RL). The X.21 loop functions (LL, RL, RLB) are supported by the X.21 interface module. The loops can be controlled with the user interface, or the loops can also be controlled with the user device through the signals 140 and 141. For these loops the user interface has congurable parameters to disable, enable, enable with timer, or only allow the operator to control the loops. All the loops have an adjustable enable timer. In general, the loops should be enabled in the equipment which are as close as possible to the user interfaces, and disabled in all intermediate equipment. The local loop can be activated with the user interface or by activating the input signal 141. Activating the local loop makes it possible to check the operation of the interface and the user line from the user device. The remote loop is activated when the V.54 loop circuit receiver recognizes the activation pattern coming from the far-end through the X-bus. The sending of the pattern from the far-end is activated by the user interface or by the input signal 141. The remote loop makes it possible to check the whole data circuit through the network. One way to perform this is to use the built-in test pattern generator and pattern error detector of the unframed interface. There is one test pattern generator per interface. When some of the V.54 loops are on, the test loop indication signal 142 goes on. Thereafter, the loop tests can be started. A loop 2 (RLB) activated from the far-end turns the signal 142 on and sets the received data to off. In case of X.21, loop 2 activated at the far-end sets the received data to off or to pattern 1010. Test Pattern Generator The channel module has built-in per channel test pattern generators and pattern error detectors. The test pattern is according to the ITU-T Recommendation O.151. Typically, a test is performed with the remote loop activated at the far-end. The user interface facilitates the activation of the test resources and presentation of the test results.
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4.1 Front Panel Indicators and Controls
The front panel of Tellabs 8120 mini node M is presented in Fig. 23.
Fig. 23 Front Panel of Tellabs 8120 Mini Node M
The four buttons and the LCD display are for local control operations. The front panel of Tellabs 8120 mini node M is equipped with LEDs to display the alarms of the system and the interface circuits. There are two alarm LEDs (red and yellow) for each block; IF1IF6 and SYS. Each block reports its own alarms with these LEDs. For the service computer (SC) there is a 9.6 kbit/s asynchronous V.24 interface with a 9-pin D connector.
4.2
Back Panel Connections

Fig. 24 shows a typical back panel arrangement of Tellabs 8120 mini node M. The xed items of the back panel are a power connector, a measurement connector, and the synchronization connectors. The back panel is furnished with four different changeable interface modules. The type of the connector depends on the type of the module. The numbering of the interfaces is also shown in the gure below.
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Fig. 24 Tellabs 8120 Mini Node M with BTE-384M, G703-75-M, V35-M and V36-M Modules
There are two places for unframed interface modules on the upper part of the panel. In one unframed module there are two channels with the same type of an interface. Each module can be of a different type, and there are no restrictions to usage of different types of unframed modules in the same piece of equipment. On the lower part of the back panel there are two places for framed interface modules. On the framed interface modules there is one interface in each module. Also the framed interfaces can be of a different type in the same piece of equipment. The synchronization connectors provide a 75 input and output for the clock signal of the master clock oscillator of the equipment. Through these connectors the equipment can be synchronized to an external clock source, or the equipment can give a clock to another data transmission equipment connected to the same transmission network. The control of the clock signal is handled with the Master Clock menu of the user interface. The interface signals and the Rx and Tx clocks of the framed interfaces can be measured with measurement equipment through the measurement connector. The impedance of the interface is 75 . The back panel arrangement for Tellabs 8120 mini node M with a different module conguration is shown in Fig. 25.
Fig. 25 Example of Back Panel with G703-75-M, OTE-LED-M, V36-M and V35-M Modules 22030_12 2013 Tellabs. Tellabs 8100 Managed Access System Tellabs 8120 Mini Node M Operating Manual
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If an unframed interface module (user access interface module) is removed permanently by the user, it must be replaced with a blank upper interface, part code 880070157A, to close the back panel opening.
If a framed interface module is removed permanently by the user, it must be replaced with a blank lower interface, part code 880070158A, to close the back panel opening.
4.3
Mains Connection
Tellabs 8120 mini node M is connected to a 100240 V AC mains supply with a three-pin grounded plug. The maximum power consumption is approximately 40 V A. The consumption varies depending on the installed module conguration and the bit rates in use. Other power supply alternatives are a 48 V DC or a 24 V DC power supply. Tellabs 8120 mini node M is equipped with one primary fuse. If the green power indicator is switched off, it indicates a failure of the fuse. Other power supply problems can be checked with the user interface which has a voltage measurement facility. The fuse of the AC model is located inside the metallic case. Only qualied personnel is allowed to change the fuse.
Tellabs 8120 mini node M must be disconnected from the mains supply before removing the cover as high voltages are present inside the case.
The AC model mains supply primary fuse can be changed after the metallic top cover and power supply shield have been removed. The primary fuse of the DC models is accessible on the back panel of the device. The fuse is of a standard 5 x 20 mm size and it must be replaced with the ratings indicated below.
Power Unit 8990NFS40 PDU422 24 V DC25 Fuse T1A T4A T4A Input Voltage 100240 V AC 10% 4763 Hz 1936 V DC, negative pole earthed 4060 V DC, positive pole earthed
PDU423 48 V DC
Power consumption: 40 V A max.
4.4
Operating Environment
When installing Tellabs 8120 mini node M, do not put it in a warm place.
25The
power supply module PDU422 has been discontinued.
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Never put Tellabs 8120 mini node M on top of another piece of equipment of the same kind because it can cause overheating and malfunctioning of the equipment. A very dusty or humid installing place can also cause incorrect working of Tellabs 8120 mini node M and, in some cases, even danger for the user.
Operating temperature: +5+35 C Operating humidity: < 85% RH, non-condensing The gure below shows how the ventilation air goes through the device. Enough free space should be left around Tellabs 8120 mini node M to guarantee proper functioning and ventilation.
Fig. 26 Route of Ventilation Air
Do not cover the ventilation holes on the case of Tellabs 8120 mini node.
4.4.1
DC Power Supply Cabling

Tellabs 8120 mini node M with DC power supply is connected to the main battery system with a two-wire cable which has the following color codes:
24 V DC Power Supply +24 V 0V Wire Color Red Black
48 V DC Power Supply -48 V 0V
Wire Color Blue Black
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4.4.2
SC, Local Service Computer Connector

The SC, local service computer connector is provided with a 9-pin female D-connector according to ISO 2110 Standard. The connector is furnished with two UNC 4-40 locking screws.
Pin # 1 2 3 4 5 6 7 8 9 ITU-T Circuit # 109 104 103 108 102 107 105 106 Signal Level V.28 V.28 V.28 V.28 V.28 V.28 V.28 Function Received line signal indicator Received data Transmitted data Data terminal ready Signal ground Data set ready Request to send Clear to send Not connected
4.4.3
SYNC Connector
The SYNC connectors are SMB type connectors, electrically of G.703/75 impedance.
4.5
Conguration of Tellabs 8120 Mini Node M

Step 1 Check that Tellabs 8120 mini node M is ready for operation: Interface modules are properly installed and fastened. The cover is installed. The metallic case is in its place and fastened with all screws. No loose parts are inside the case. Step 2 Put Tellabs 8120 mini node M to correct operation environment as described in 4.4 Operating Environment. Check that nothing covers the ventilation holes of Tellabs 8120 mini node M. Note that there are ventilation holes also on the sides of the metallic case. Step 3 Step 4 Connect interface connectors to the back panel of Tellabs 8120 mini node M. Connect the power cord to the main power supply and the protective earth wire to the grounding terminal. See the exact location of the wire in Fig. 40. Screw the grounding earth wire with washers tightly to the M5 nut at the back of the node.
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When DC power supply is used, Tellabs 8120 mini node M must be permanently connected to earth using the supplied grounding earth wire.
Fig. 27 Grounding Earth Wire Assembly
Step 5 Step 6
Tellabs 8120 mini node M is now ready for use. Check that no unusual alarms are on. Congure Tellabs 8120 mini node M with planned parameters. Check that the parameters for the framed interfaces and master clock are correct. (See 4.7 Recommended Settings of Framed Interfaces for recommended settings.) Set the node ID. When the power cord is connected, the green and yellow LEDs are lit. After a start-up time, which is from 30 to 60 seconds and depends on the conguration of the equipment, the yellow LED will be switched off and Tellabs 8120 mini node M is ready for operation. The meaning of the color of LEDs is explained below.
Green Yellow Red Lit when Tellabs 8120 mini node M is connected to the mains supply and the power is switched on. Lit when Tellabs 8120 mini node M is receiving alarm indication from the network (far-end alarm, AIS). Test state (loops etc.). All other fault situations.
The conguration of Tellabs 8120 mini node M can be monitored and altered through Tellabs 8000 manager or by a local service computer connected to the front panel connector, a 9.6 kbit/s asynchronous V.24 interface. There are two HDLC control channels (one in both framed interfaces IF1 and IF2). These are normally used when Tellabs 8120 mini node M is connected to Tellabs 8000 manager. The control functions operate as in a Tellabs 8100 cross-connect node. The Tellabs 8120 mini node M blocks have the same Tellabs 8000 manager functions as in the corresponding units in the Tellabs 8100 node. The common test resource, which is in the SCU unit of the other nodes, does not, however, exist in Tellabs 8120 mini node M. The conguration can also be done locally through the front panel keys and the LCD display. It can be monitored on the LCD display during operation without interfering with data transmission.
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4.5.1
NMS Control
Tellabs 8120 mini node M is designed to be controlled by Tellabs 8000 manager. The control functions operate as in a Tellabs 8100 cross-connect node. There are two HDLC control channels (one in both framed interfaces IF1 and IF2). These control channels are used when Tellabs 8120 mini node M is connected to Tellabs 8000 manager. There is a 9.6 kbit/s asynchronous V.24 interface on the front panel. Through this interface Tellabs 8120 mini node M can be controlled also with the service computer of the Tellabs 8100 system. The Tellabs 8120 mini node M blocks have the same NMS functions as the corresponding units in the Tellabs 8100 node. The common test resource, which is in the SCU unit of the other nodes, does not, however, exist in Tellabs 8120 mini node M.
4.5.2
Local Control
Tellabs 8120 mini node M has a local keyboard (four buttons) and an LCD display for local control operations. With these tools the local user can make the same operations that are possible with the service computer connected to the SC interface on the front panel. With the local keyboard and the LCD display the user can perform the following operations: read the node parameters node ID unit ID (hardware and software versions, serial number) read/set master clock parameters creating and deleting cross-connections (not possible with SC) alarm information from each interface and block read the active faults or the fault history clear the fault history set interface tests and loops read the error counters and G.821 error statistics from each interface read the status of V interface control signals read/set interface parameters In the following description the abbreviation NTUM refers to Tellabs 8120 mini node M. The NTUM parameter settings can be monitored during operation through the display without interfering the normal data transmission. The parameter settings are stored in a non-volatile memory. The Conguration menu recognizes the interface units and transmission modules and displays the correct menu items accordingly.
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The LCD display has two lines with 24 characters each. In most cases three item elds are shown at a time. The upper line is used to show the heading of an item; on the lower line there is the value of the item or the text DIR, which means that there is a sub-menu for the item. Although there are three items on the display, there may be many other items at the same level of the menu. The other items can be scrolled to the display with the keys. The blinking cursor indicates the current item eld. When the cursor is on the upper line, the SCROLL keys (< or >) are used to move from one item to another at the same menu level. When the cursor is on the lower line, the SCROLL keys are used to change the value of the parameter of the item. By using the EXIT and ENTER keys the user can move up or down in the menu structure. The ENTER key is also used to conrm a selection from a menu. When the cursor is on the upper line, the EXIT key causes a move upwards to the next menu level. On the lower line the EXIT key moves the cursor from the value eld to the heading of the item. The ENTER key moves the cursor from the heading to the value eld of the item or to the sub-menu if the value is DIR. When the cursor is on the value eld, the use of the ENTER key conrms that the present value of the eld is used as a new value of the item and the cursor moves to the heading of the item. If the value of an item is changed, the new value of the menu branch must be conrmed by the Update eld, which is the rst eld of the branch. The value of an item is changed in the following way. Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Step 8 Move the cursor with the SCROLL and ENTER keys to the heading of the item you want to change. Press the ENTER key to move the cursor to the value eld. Use the SCROLL keys to select the new value for the item. Press the ENTER key to conrm the new value. Use the SCROLL keys to move the cursor to the Update eld of the present menu branch. Press the ENTER key to move the cursor to the value eld of the Update eld. Press the ENTER key to conrm the update. The text Updating appears on the display. Do not push the keys before the text disappears and the menu text is visible. All the needed changes of a menu branch can be made before using the Update eld. If the phase of the present menu level (menu, sub-menu or item) is unknown to the user, the main level is reached by pressing the EXIT key several times.
4.6
Menus of Tellabs 8120 Mini Node M

The following gures present the menu structure of Tellabs 8120 mini node M.
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Fig. 28 Main Menu of Tellabs 8120 Mini Node M
Fig. 29 Menu of Main Parameters Tellabs 8100 Managed Access System Tellabs 8120 Mini Node M Operating Manual
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Fig. 30 Main Interface Parameters Menu of IF1 and IF2
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Fig. 31 Menu for IF1 and IF2 Parameters
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Fig. 32 Menu for Neighbour Node Message Parameters
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Fig. 33 Cross-Connect Menu
4.6.1
Security Menu
The security menu contains two items (device mode and panel locking) which can be set. This menu is entered in a specic way explained in 4.6.7 Entering Security Menu of Tellabs 8120 Mini Node M.
Device Mode Menu The Device Mode menu species the device mode of the NTUM. The NTUM can be either a MartisDXX device or a stand-alone device. The MartisDXX device is usually a part of the Tellabs 8100 network and it is managed by Tellabs 8000 manager. Therefore, you are not allowed to congure the cross-connections of the MartisDXX device by using the front panel keys and the LCD display. Neither are remote conguration and monitoring allowed when the NTUM is in the MartisDXX device mode. The text DXXNTUM indicates that the NTUM is in MartisDXX device mode.
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The text NTUM indicates that the NTUM is in the stand-alone mode. In this mode all the conguration and monitoring operations are allowed by the use of the front panel keys and the LCD display if the panel is unlocked. To change the device mode, use the SCROLL keys to select the new mode and press ENTER. When ENTER is pressed, the new mode is saved into the non-volatile memory to make sure that the NTUM will go to the correct mode after reset. Panel Menu The item for key panel locking has three settings (panel unlocked, panel locked, panel conguration locked) to prevent the user from accidentally selecting the wrong settings to the conguration items and thus making the NTUM non-functional. To make any changes to the NTUM conguration, the item for the key panel locking has to be unlocked. The items for panel locking and their features are Panel locked, Locked NTUM conguration cannot be seen nor altered Some statistics are available to the user Panel conguration locked, Cfg. Lock NTUM conguration can be seen but not altered Panel unlocked, Unlocked NTUM conguration can be seen and altered Menus are available to the user according to the device mode To change the panel mode, use the SCROLL keys to select the new mode and press ENTER. When the ENTER is pressed, the new mode is saved into the non-volatile memory to make sure that the NTUM will go to the correct mode after reset.
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Fig. 34 Device Modes of Tellabs 8120 Mini Node M
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NTUM Menu The NTUM user interface can be used to congure a local or a remote NTUM. The local NTUM is the target by default. The remote NTUM that is connected to the local NTUM via a trunk interface (IF1 or IF2) can be congured by using the local user interface if the HDLC communication channel is established over the trunk. To set the target NTUM, use the SCROLL keys to select it and press ENTER. Choices for the target NTUM are Local, Remote1 and Remote2. The number after the text Remote species the trunk interface that is used. The yellow LED of the corresponding interface blinks on the front panel of the local NTUM when it is in remote mode. The remote conguration is not allowed if the NTUM is part of the Tellabs 8100 network.
4.6.2
Faults Menu
Three menu branches are available from the eld of Faults by pressing the ENTER key: ActFlts, FltHist and ClrHist. From these elds the user can see the fault(s) which are active at the moment or receive the information of the latest fault state transitions (the fault history report) and clear the history report.
ActFlts The ActFlts menu is used to ask active faults from the target NTUM by pressing the ENTER key. The active faults can be seen in the following list format (fault/interface or common level fault).
1 2 3 4 Rx signal mis. Master clock t Fr fe alarm AIS from X-bus IF 1 Com IF 2 IF 5
If there are several faults, two of them will be displayed and the rest of the faults can be viewed by using the SCROLL keys. Pressing the ENTER key activates a new fault query from the NTUM. FltHist From the FltHist menu the user can see the fault history report by pressing the ENTER key. The fault history is useful when a fault has been on (the red LED ashes) but when asking for active faults the response is No faults. The display format is:
1 2 3 4 5 6 Reset Master clock Rx signal mi Fr f-e alarm Fr f-e alarm Rx signal mi Com Com IF 1 IF 2 IF 2 IF 1 DLT ON ON ON OFF OFF
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If there are several faults on the history report, two of them will be displayed and the rest of the faults can be viewed by using the SCROLL keys. The latest fault transition has the biggest number (in the case above 6 Rx signal mi IF1 OFF is the latest fault transition). Pressing the ENTER key activates a new fault query from the NTUM. ClrHist The fault history can be cleared in the ClrHist menu by pressing the ENTER key. After clearing the faults the unit starts the fault history collection automatically.
4.6.3
Parameters Menu
The general node and unit level parameters can be read and changed in the branch Param. (all parameters, e.g. the serial number, are not changeable). The readable and changeable parameters are the node and unit level identication data, the cross-connection clock selection (MastClk), the module dening, the 1+1 protection and the measurement point selection.
Node Identication Menu The NTUM has its own node identication number 065535 which can be changed by the user. Each node in the network must have a different Node ID. Unit Identication Menu Only the unit level information of the NTUM can be read in this branch.
Hw-ver Sw-ver Year Week Serial The hardware version of the unit. The software version of the unit is used to identify the downloaded software version etc. The year when the unit was manufactured. The week when the unit was manufactured. The serial number which is an absolute identication of the unit. The serial number is set at the production phase of the unit.
Master Clock Menu The NTUM has a 16-MHz master clock which is used for generating the timing of the cross-connect bus. The timing consists of 16 MHz 8 kHz frame sync 500 Hz multiframe sync The interfaces use these signals in the bus interface. The 16-MHz clock is also used to generate the Tx clock of each data interface. The master clock is usually synchronized to one of the incoming data signals (generally a 2 Mbit/s trunk). The clock of the desired interface is collected by using a separate synchronization clock bus (SYB). The master clock object tells the required interface to connect its Rx clock to this bus.
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The clock fallback list is used to dene the synchronization priority order. The list can have up to ve entries. The form of the clock fallback list is 1. 2. 3. 4. 5. IF_ IF_ IF_ IF_ Ext. clock (Internal)
The list can also be made shorter. The last entry is followed automatically by the internal state. On the back panel of the NTUM there is a connector for the external clock input. It can be selected to the clock fallback list. The frequency of the external clock can be dened as n x 64 kHz, where n = 1132 (64 kHz8448 kHz). The NTUM also has a clock output. It is electrically similar to the clock input. The clock output frequency is derived from the master clock and its frequency can be selected (n x 64 kHz). Usually 2048 kHz is used. The master clock of an NTUM can be congured and monitored by using the master clock menu. The master clock menu is entered by pressing the ENTER key when the cursor blinks on the MastClk text. The Master Clock menu contains the following elds (upper line).
Update Choices This eld updates the new master clock parameters to the target NTUM (local or remote). All the available interfaces that can be used as the master clock are displayed here. If there are no available interfaces, the text None is shown. The text Ext refers to the external clock. The list of the available interfaces can be scanned by using the SCROLL keys. To add an interface in the fallback list, press ENTER when the cursor blinks on that interface. The text Add IFn in 1st FBL slot is shown. Use the SCROLL keys to change the slot number. When the slot number of the fallback list is selected, press ENTER to add the interface in the fallback list. The fallback list of the master clock is displayed in this eld. The elements of the list are in the priority:source format. The text None indicates that the list is empty. The fallback list can be scanned by using the SCROLL keys. To remove an interface from the fallback list, press ENTER when the cursor blinks on that interface. The text Remove IFn from FB List is shown. Press ENTER again to remove the interface, otherwise press EXIT.
FB List
State
This is the sub-menu for the state monitoring of the master clock. Press ENTER to start the state monitoring. The State Monitoring sub-menu contains the following elds which are automatically updated every fth second. This eld indicates the current source of the master clock: Intern, SYB1, SYB2 or Extern. This eld indicates the current state of the master clock: OK, Alarm. This eld displays the source interfaces of the sync clock busses. This eld species the frequency of the external clock. To change the frequency, use the SCROLL keys to select a new frequency and press ENTER. This eld species the frequency of the clock output. To change the frequency, use the SCROLL keys to select a new frequency and press ENTER.
Source State SYB1/2 Ext Clk Clk Out
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OutCtrl
This eld species the control mode of the clock output. The output clock controlling is either ON or OFF. If the output clock controlling is ON and the output clock is enabled (an output clock frequency is specied), the output clock will be disabled if the source of the master clock is either an internal or an external clock. If the output clock controlling is OFF, the state of the output clock does not depend on the source of the master clock. To change the control mode, use the SCROLL keys to select a new mode and press ENTER. This eld species the acceptance time for the clock sources. A clock source is a valid source for the master clock if the status of the clock source has been OK for at least as long as the acceptance time species. The acceptance time value is 0-120 s. To change the acceptance time, use the SCROLL keys to select a new time and press ENTER.
AcpTime
Module Conguration Menu The NTUM device has six interfaces and four independent interface modules. The modules are numbered so that the modules 1 and 2 have corresponding interfaces (1 and 2), but modules 3 and 4 have both two interfaces (3, 4 and 5, 6). When the user has decided to install a new interface module, also the module conguration must be changed from the Cong branch.
IF1 Install Type Cong This eld shows the currently installed module (read-only information). This eld appears only if the installed module contains strappings. The eld shows the information on module strapping (75 /120 / contradirectional/codirectional). The module conguration eld denes what kind of a module the unit program currently services. Thus, there should be the same module in the Install eld as in the Cong eld. There is also a Not def selection which means that the interface has not been dened (module not in use) and no faults which belong to this module will be reported. If, for example, a module is not installed, the module should be congured as Not def.
1+1 Protection Menu The interfaces 1 and 2 can be congured into the 1+1 protected mode. In the protected mode both interface modules must support the selected bit rate. The Rx signal faults are classied into several categories. The switch uses fault categories to select the interface to be used. When the IF1 or IF2 parameters are updated in the protected mode, both interface parameters will be updated (except for the baseband parameters Line, Level, ScrmTyp, ScrmMo, 10E-3 Consequences, FltMsk and Congured Module).
Update This eld is used to update the 1+1 protection parameters in the NTUM. The 1+1 parameters (Mode, HomeSta, ChaDel and Force) can be changed on other elds but after the changes the parameters must be updated by pressing the ENTER key in the Update eld. In this eld the 1+1 mode can be dened on/off. The No prot selection means normal unprotected mode, ProtIf1 means protected mode by settings of interface 1, and ProtIf2 protected mode by settings of interface 2. The eld is displayed only in the 1+1 protected mode; it shows which Rx signal is connected to the cross-connection. The eld is auto-refreshed.
Mode
CurSele
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HomeSta
This eld is displayed only in the 1+1 protected mode. The home state can be changed in the eld to the switch which selects the Rx signal. The selection No H-S means that the switch chooses the better Rx signal and the selection changes will be made only when the unused Rx signal quality is better than the used Rx signal. The selection IF1/IF2 means that the IF1 or IF2 interface is dened as the home state, and when both interfaces are classied to the same category, the switch selection returns always back to the home state interface. This eld is displayed only in the 1+1 protected mode. The eld handles the protection switch change delay (0 ms10 min). The change delay is a lter parameter of the protection switch so that the fault transition which can affect the switch turning must be active for the duration of the change delay before the switch turns. This eld is displayed only in the 1+1 protected mode. The eld handles the force control of the protection switch. The state None is normal; in the state IF1 or IF2 the protection switch is forced to select IF1 or IF2. The time-out for this control is the same as the time-out for IF1 controls.
ChaDely
Force
Measurement Point Menu The NTUM device has one measurement point. The signal can be selected to this point from interfaces 1 or 2 and the signal can be either Rx clock or data or Tx clock or data.
MeasPnt The measurement point selections can be scanned by using the SCROLL keys. Press the ENTER key to conrm the selection.
4.6.4
Interface Parameters Menu

The interface parameters (interface 16) can be read and changed in this branch. The reading/change possibility depends on the panel state (see 4.6.1 Security Menu). Interfaces can be divided into two groups according to their sub-menus: interfaces 12 have the same type of sub-menus, whereas the sub-menus of interfaces 36 are similar. Parameters of Interface 1 and 2 The following menus are available when the selected interface is IF1 or IF2.
Param Update The general interface parameters can be read, changed and updated in this branch. This eld is used to update the interface parameters. The interface parameters (Framing, Rate, Basband, BitUse, CAS, CntrlTyp, Buffer, FtsData, FltMsk, FltAct) can be changed in other elds and sub-menus but after changes the parameters must be updated by pressing the ENTER key in the Update eld. The possible selections are On, Off RxM, Off. All selections are available when the interface is in unlocked state. If the state is locked, the changes can be made only between Off RxMon/ Off. The selectable bit rate depends on the congured module (the module must support the selected bit rate). If the device is in 1+1 protected mode, both interfaces must support the selected bit rate. When the framing is on, the minimum bit rate is 128 kbit/s (2 x 64k). If the interface is locked, no bit rate changes can be made.
Framing
Rate
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Basband *Line *Level *ScrmTyp *ScrmMo *WetCur
This eld is displayed when the congured interface module is a baseband module. There are three sub-menus under the Basband menu. The type of the line can be 2-wire or 4-wire when the biphase coding is used (BTE384). The possible output levels depend on the type of the BTE. With BTE384 the possible scrambler types are None, V32, V29, NDPN and NPDNV29; with other BTEs None and V29. The eld is displayed only when the congured module is BTE384 and the possible scrambler modes are call and answer. The eld is displayed only when the congured module is BTE384 and the wetting current has the states ON/OFF. In the state ON, the BTE module detects when the NTU is in the POWER OFF state. This eld is displayed when the congured interface module is V35-G704 or X21-G704. The scrambler has two states, ON/OFF. This eld is displayed when the framing is ON and the sub-menus depend on the selected bit rate (in the 8M mode the sub-menus are different).
VdhScrm BitUse
The following elds (TS0B1, CRCE, FSW/RAI, TS0B4TS0B8) are displayed when the bit rate is not 8M.
TS0B1 The eld for selecting the use of TS0B1; one of the following: CRC use: CRC4 will be generated into this bit HDLC use: HDLC channel in this bit X-Con: the bit comes from the cross-connection CBSC: the bit is controlled by a separate command, e.g. in master clock remote alarm use 0: the bit will be transmitted at the permanent 0 state 1: the bit will be transmitted at the permanent 1 state. Note! When the control type is master or slave, this bit must be in CRC use. The eld is displayed if TS0B1 is in the CRC state and the CRCE bit can be congured as:ReEnd: CRCE bit is used to indicate remote end CRC errors0: the bit will be transmitted at the permanent 0 state1: the bit will be transmitted at the permanent 1 state The frame synchronization word and the far-end alarm (TS0B3) usage:Regen: Transmitted sync. word and remote-end alarm are regeneratedX-Con: Transmitted sync. word and remote-end alarm comes from the cross-connectionX-Sync: Sent frame is synchronized to the frame coming from the cross-connectionRAIXcon: Remote-end alarm comes from the cross-connection Fields for selecting the use of TS0B4TS0B8 are similar (but independent).HDLC use: the bit is selected for HDLC useX-Con: the bit comes from the cross-connectionCBSC: the bit is controlled by a separate command e.g. in master clock remote alarm use0: the bit will be transmitted at permanent 0 state1: the bit will be transmitted at permanent 1 state
CRCE
FSW/RAI
TS0B48
The following elds (TS99B1-7, CRCE, TS99B8 and TS66B8) are displayed when the bit rate is 8M.
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*TS99B1-7
The eld for selecting the use of TS99B1-7.CRC use: CRC will be generated in these bitsHDLC use: bits are selected for HDLC useX-Con: bits come from the cross-connectionCBSC: bits are controlled by a separate command e.g. in master clock remote alarm use0: bits will be transmitted at the permanent 0 state1: bits will be transmitted at the permanent 1 state The eld is displayed if TS99B1-7 are congured for CRC use.ReEnd: CRCE bit is used to indicate remote-end CRC errors0: the bit will be transmitted at the permanent 0 state1: the bit will be transmitted at the permanent 1 state The eld for selecting the use of TS99B8.HDLC use: the bit is selected for HDLC useX-Con: the bit comes from the cross-connectionCBSC: the bit is controlled by a separate command e.g. in master clock remote alarm use0: the bit will be transmitted at the permanent 0 state1: the bit will be transmitted at permanent 1 state The eld for selecting the use of TS66B8.HDLC use: the bit is selected for HDLC useX-Con: the bit comes from the cross-connectionCBSC: the bit is controlled by a separate command e.g. in master clock remote alarm use0: the bit will be transmitted at the permanent 0 state1: the bit will be transmitted at the permanent 1 state
*CRCE
*TS99B8
*TS66B8
The HDLC and MCLRAI elds are both present whatever the bit rate is.
*HDLC The HDLC control channel usage is selected in this branch. When the HDLC channel is used in the time slots TS0, TS66 and TS99 or it is desired to be used there, the HDLC usage must be dened in the special time slot/bit eld(s). The following can be selected in this eld:In use: the HDLC channel will be in use.-----: the HDLC channel is not in use. When the HDLC channel is in use, the time slot for HDLC use can be selected in this eld. When the HDLC channel is in use, the bit(s) for HDLC use can be selected in these elds. The master clock remote alarm usage can be controlled in this branch. The clock remote-end alarm can be congured into frame special bits or in data bits. Special bits must be congured as CBSC for the clock remote-end alarm usage. If the clock remote-end alarm is in the data bit, this time slot must not be cross-connected (MCLRAI usage reserves the whole time slot).MCLRAIIn use: MCLRAI will be in use.-----: MCLRAI is not in use.TS: When MCLRAI is in use, the time slot for MCLRAI use can be selected in this eld.Bit18: When MCLRAI is in use, the user can dene in this eld which bit of the time slot is in MCLRAI usage.Pol.: When MCLRAI is in use, the user can dene the polarity of alarm in this eld. This eld is displayed when the framing is ON and sub-menus depend on the selected bit rate (in the 8M mode there are four CAS groups A, B, C and D; and in the other bit rate modes for signalling only one time slot is reserved).
*HDLC *TS *Bit18 *MCLRAI
CAS
The following elds (CAS, Bit5,7,8) are displayed when the bit rate is not 8M.
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*CAS
Use of channel associated signalling. When the bit rate is 1088 kbit/s (17 x 64 kbit/s) or higher, TS16 is used for signalling. In other cases the last time slot is used for signalling, e.g. if the rate is 384 kbit/s (6 x 64 kbit/s), the signalling will be in TS5:On: one time slot is reserved for signallingOff: signalling is not used and the signalling time slot can be in data use The elds are displayed if CAS is turned ON. There are three similar elds for selecting the usage of the special bits B5, B7, B8 of the signalling time slot.X-Con: the bit comes from the cross-connectionCBSC: the bit is controlled by a separate command e.g. in master clock remote alarm use0: the bit will be transmitted at the permanent 0 state1: the bit will be transmitted at the permanent 1 state
*Bit 5,7,8
The following elds (CAS A, Bit5,7,8CAS D, Bit5,7,8) are displayed when the bit rate is 8M. The elds for the signalling groups are similar. For this reason only the group CAS A is mentioned here. The time slots for the signalling groups are CAS A in TS67, CAS B in TS68, CAS C in TS69 and CAS D inTS 70.
*CAS A *Bit 5,7,8 Buffer FtsData Use of channel associated signalling of group A (TS67).On: TS67 time slot is reserved for signallingOff: signalling is not used and the signalling time slot can be used for data use Use of the bits 5, 7, 8 is as above. The eld is for handling the Rx buffer. The possible selections: 4, 8, 64 frame buffer. The selected bit rate and the split trunk usage affect the possible buffer length. The idle data of unconnected time slots can be dened in this branch. This means that the time slots which are not cross-connected are transmitted with idle data. It is recommended that all bits are set at the state 1. There are eight similar elds (one eld for each bit).1: the bit will be transmitted at the permanent 1 state.0: the bit will be transmitted at the permanent 0 state. In this eld the fault mask state (ON/OFF) can be handled. When the fault mask is ON, no interface faults will be generated (only the fault of the mask itself). Some fault actions and consequences can be dened in this branch. There are four sub-menus (AisInh, RaiInh, RaiCsq and E3Csq), each with two states ON/OFF. The AIS inhibit ON affects the AIS alarm generating.OFF: the AIS alarm will be generatedON: when the received signal is AIS or in the received signalling TS is AIS, no alarms will be generated due to this fault. RAI inhibit ON affects the far-end remote alarm generating (from frame and multiframe level).OFF: the remote-end alarm(s) will be generatedON: when the received frame or multiframe far end alarm, no alarms will be generated due to this fault. The remote alarm consequences affect to the AIS inserting into the received signalling time slot when the frame or the multiframe far-end alarm has been received.ON: AIS will be inserted when the far-end alarm has been received. The far-end alarm fault is provided with service alarm status (S).OFF: The far end alarm does not cause AIS inserting into the signalling time slot(s). The far-end alarm fault is generated without service alarm status. This eld affects the AIS inserting into the received signal when the received signal error rate is worse than 10E-3.ON: AIS will be inserted into the received signal when the error rate is worse than 10E-3. The BER10E3 alarm will have the service alarm status (S).OFF: The error rate 10E3 does not cause the AIS insertion into the received signal. The BER10E3 alarm is generated without service alarm status. AIS detection in unframed mode ON/OFF:
*Bit18 FltMsk FltAct *AisInh
*RaiInh
*RaiCsq
*E3Csq
AisDet
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NnmPara
This branch handles the neighbor node parameters of the interface. When the interface framing is ON and the HDLC channel is in use, these parameters affect the sending and the monitoring of neighbor node parameters. This eld is used to update the neighbor node parameters into the NTUM. The neighbor node parameters (Expected neighbour and Options) can be changed in other elds but after the changes the parameters must be updated by pressing the ENTER key in the Update eld. This branch has two sub-menu elds Own and the Neighbour alarms (Loop, Unexpected neighbour, No connection, OK). The Alarm elds are auto-refreshed. This is a read-only eld where the neighbor node alarms of the target NTUM can be read. This is a read-only eld where the neighbor node alarms of the neighbor of the target NTUM can be read. The eld is displayed only if there is a connection between the neighbors. This branch has six sub-menu elds each of which has data of the existing neighbor (neighbor: node ID, subrack address, unit number, link number, interface number and port number). The elds are auto-refreshed. The expected neighbor data has the same kind of data elds as in the Exist branch. Copies the existing data structure to the expected eld (you have to remember to update). This is useful when updating the correct neighbor info. This branch has three sub-menus to activate or deactivate the sending, the supervision and the monitoring. ON: the neighbor node data sending activatedOFF: the neighbor node data sending deactivated ON: the neighbor node state monitoring activatedOFF: the neighbor node state monitoring deactivated ON: the neighbor node supervision activatedOFF: the neighbor node supervision deactivated This eld is used to lock or unlock the interface. Locking means that the interface allocates the needed capacity from the cross-connection and unlocking that the interface deallocates the reserved cross-connection capacity. Please note that the text on the LCD display describes the next movement in the locking state if ENTER is pressed (e.g. if there is the text Lock, the interface is in the unlocked state and the next change is made to lock the interface). The loop can be activated/deactivated and the state of the loops can be seen in this branch. This is a read-only eld where the loop state can be seen (e.g. Line Loop, Equipment Loop, Interface Loop, Remote Loop). The eld is auto-refreshed. The loops can be activated/deactivated in this eld. The Remote loop availability depends on the interface parameters (Framing, HDLC, NnmPara/MesSend and Module).
Update
Alarms *Own *Far-end
Exist
Expec CpyExi Options *MesSend *StaMon *NeigSup Locking
Loops State Set
When the remote loop is a V54 loop (BTE384, and HDLC is not used), the following menus are displayed.
TraBits ErrBits InjErr Time-out Time-out The count of transmitted bits during a test (test generator connected when RL). The count of errored bits during the test. Inject one error into the transmitted data. The interface controls time-out parameter can be handled in this branch. The interface controls time-out in minutes. (When the loop has been activated, it will be deactivated automatically after the time dened in Time-out).
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ErCntrs ResCtrs FraLos FSW CRC CRCE BufSlip Code RxDelay
The error counters can be read and cleared in this branch. The elds are auto-refreshed. Clear all error counters. Count of frame alignment losses (read-only). Count of faulty frame alignment words (read-only). Count of CRC errors (read-only). Count of faulty CRC E-bits (read-only). Count of buffer slips (read-only). Count of code errors (read-only). The value describes the time which the incoming data is in the buffer before it is clocked into the cross-connection. The time value should remain the same. If the time increases or decreases, the incoming clock of the interface differs from the clock used by the cross-connection system. This eld is auto-refreshed. Branch to the standard G.821 statistics. By pressing the ENTER key in this eld the total time of the statistics can be seen on the display:Total Time9 dd 13 h 24 min 5 sWhen pressing the SCROLL keys, the display will show the available time, the unavailable time, severely errors seconds, errored seconds and degraded minutes. This eld is auto-refreshed. Clears the G.821 counters. This branch is displayed if the interface module is BTE-384 or BTE-768. Read-only information from the received signal level. Read-only information from the received signal quality with A (best quality) through F (poorest quality).The elds are auto-refreshed.
G.821 *Display
*ResG821 BbInfo *RxLevel *RxOual
4.6.5
Cross-Connection Menu
The cross-connection is done in the switching matrix of the NTUM. The cross-connection bus contains about 1050 cross-connectable time slots (8-bit bytes). The bits from the interfaces are collected by using this bus. The cross-connect switch combines (in other words, makes the cross-connection) the needed new bytes for the interfaces in accordance with the cross-connection commands by using 8 kbit/s granularity. The commands are stored in a non-volatile memory. The cross-connections of the target NTUM (local or remote) can be congured and seen by using the Cross-Connection menu. To simplify the use of this menu it is divided into four sub-menus.
Cross-Connection Conguration Menu Cross-connections can be created and deleted by using the Conguration menu. This sub-menu can be accessed only when the NTUM is in the stand-alone mode and the panel is unlocked. This sub-menu is divided into sub-menus to support the conguration of the various cross-connection formats (TS pair, TS area and TS bits) and the powerful delete operation (Del All). The following elds are common to all of these sub-menus:
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Oper
This is the leftmost eld of the TS pair, TS area and TS bits sub-menus and it is used to execute the desired cross-connection operation that is either CreCons (create) or DelCons (delete). When it has been selected by using the SCROLL keys, the operation can be executed by pressing the ENTER key. Before executing the cross-connection operation all parameters should be set. This eld is used to specify the directionality of the cross-connection: either unidirectional (AB) or bidirectional (A B). This eld is used to specify the channel of the cross-connection. The n x 8 kbit/s and n x 64 kbit/s groups mapped by the channel interfaces are called the XB channel. The XB channel can be a combination of 64 kbit/s and 8 kbit/s signals. If the interfaces are equipped with signalling or control signals, they are mapped either to the XB channel or to the corresponding signalling bits (n x 500 bit/s) of the XD channel. In the later case the signals are mapped to the G.704 compliant multiframe of the 2 or 8 Mbit/s trunk. The n x 500 bit/s signalling bits are called the XD channel of the interface. The number of the signalling bits depends on the capacity of the XB channel. Data interfaces do not normally use the XD channel. Signalling bits are reserved for the XB channel in the following way.
Dir XB+XD
XB Capacity TSn/B1B8 TSn/B1B4 TSn/B5B8 TSn/B1B2 TSn/B3B4 TSn/B5B6 TSn/B7B8 64 kbit/s 32 kbit/s 32 kbit/s 16 kbit/s 16 kbit/s 16 kbit/s 16 kbit/s
XD Capacity 4 bits (a,b,c,d bits in G.704 structure) 2 bits (a,b) 2 bits (c,d) 1 bit (a ) 1 bit (b ) 1 bit (c ) 1 bit (d )
The a, b, c and d bits of the XD channel in the G.704 multiframe correspond to the XB channel time slots in the G.704 frame. The capacity reserved by XB and XD channels is determined by the interface type and the user requirements. Four signalling bits are reserved for each time slot. Even if only some of the bits are needed, all four bits are cross-connected and transferred to the far-end channel interface.
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Fig. 35 XB and XD Channels in Network
X-Group
If the cross-connection is a part of the cross-connection group (X-Group), the ID of the group can be set by using this eld. A zero X-Group ID indicates that the cross-connection is not a member of any of the X-Groups and it is always in the active state. The X-Group IDs 116382 are valid. The TS pair cross-connection format describes the connection between the time slot of an interface and another time slot of the same or another interface. Both interfaces of the connection should reside in the same NTUM (local or remote).
Time Slot Pair
The TS Pair sub-menu contains the following elds: Oper X-Group, Dir, XB+XD, IF A, IF B, TS A, TS B where IF A: Interface number (only locked interfaces are valid). This is the source interface of the unidirectional connection. IF B: Interface number (only locked interfaces are valid). This is the destination interface of the unidirectional connection. TS A: Number of the time slot in the IF A. This is the source time slot of the unidirectional connection. TS B: Number of the time slot in the IF B. This is the destination time slot of the unidirectional connection. Example: DIR = A<->B, XB, IF A = 1, IF B = 2, TS A = 2, TS B = 5
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Fig. 36 Cross-Connection of One Time Slot between Two Framed Interfaces
Time Slot Area
The TS area cross-connection format describes the connection between the continuous area of time slots of an interface and another continuous area of time slots of the same or another interface. Both interfaces of a connection should reside in the same NTUM (local or remote).
The TS Area sub-menu contains the following elds: Oper X-Group, Dir , XB+XD, IF A, IF B, fstTS A, lstTS A, fstTs B, lstTs B where IF A: Interface number (only the locked interfaces are valid). This is the source interface of the unidirectional connection. IF B: Interface number (only the locked interfaces are valid). This is the destination interface of the unidirectional connection. fstTS A: Number of the rst time slot of the area in the IF A. This species the source of the unidirectional connection. lstTS A: Number of the last time slot of the area in the IF A. This species the source of the unidirectional connection. fstTS B: Number of the rst time slot of the area in the IF B. This species the destination of the unidirectional connection. lstTS B: Number of the last time slot of the area in the IF B. This species the destination of the unidirectional connection. Example: DIR = A->B, XB, IF A = 1, IF B = 2, fstTS A = 0, lstTS A = 2, fstTS B = 3, lstTS B = 5
Fig. 37 Cross-Connection of Three Time Slots between Two Framed Interfaces 22030_12 2013 Tellabs. Tellabs 8100 Managed Access System Tellabs 8120 Mini Node M Operating Manual
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Time Slot Bits
The TS Bits cross-connection format describes the connection between the bits in a time slot of an interface and other bits in a time slot of the same or another interface. The interfaces that are to be connected should reside in the same NTUM (local or remote).
The TS area sub-menu contains the following elds: Oper X-Group, Dir, XB+XD, IF A, IF B, TS A, TS B, bMask A, bMask B where IF A: Interface number (only the locked interfaces are valid). This is the source interface of the unidirectional connection. IF B: Interface number (only the locked interfaces are valid). This is the destination interface of the unidirectional connection. TS A: Number of the time slot in the IF A. This is the source time slot of the unidirectional connection. TS B: Number of the time slot in the IF B. This is the destination time slot of the unidirectional connection. bMask A: Bit mask of the TS A. The bit mask consists of eight bits (one byte) where a 1 state of a bit indicates the connection. In the user interface of the NTUM the bit mask is presented in the hexadecimal format. 4.7.7 Binary-to-Hexadecimal Conversion Table contains the table for the binary to hexadecimal conversion. bMask B: Bit mask of the TS B. Example: DIR = A<->B, XB, IF A = 1, IF B = 2, TS A = 2, TS B = 5, bMask A = 85H, bMask = 62H
Fig. 38 Cross-Connection of Time Slot Bits
Delete All
This menu is used to delete all cross-connections of the target NTUM (local or remote). The X-Group identier of the cross-connections to be deleted can be specied. The default value of the X-Group identier is Any, which will delete all cross-connections of the target NTUM.
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Cross-Connection Display Menu By using this menu the current state of the cross-connections can be seen. Also the existing cross-connections can be deleted more efciently than by using the Conguration menu. The X-Group identier and one interface of the cross-connections to be displayed can be specied. To see the existing cross-connections, press the ENTER key twice when the cursor blinks over the GetCons eld on the upper line of the LCD display. The text Getting is shown on the display during the message send/receive operation. If the target NTUM does not contain the specied (interface, x-group) connections, the text No connections is shown. Otherwise, the rst connection is shown. The cross-connection is shown so that it occupies both lines of the LCD display and the source end of the unidirectional connection is on the upper line. The rest of the connections can be viewed by using the SCROLL keys. The existing cross-connection can be deleted by using this menu only when the NTUM is in stand-alone mode and the panel is unlocked. To delete it, press the ENTER key when the existing cross-connection is on the display. After that, a question Delete connection? is shown. Press ENTER again if you want to delete the connection, otherwise press EXIT. X-Group Menu An x-group is a group of the cross-connections that have a common x-group identier. The x-group is either active or passive. If the x-group is active, all cross-connections of that x-group are active. Several x-groups can be in active state at the same time if the cross-connections of these x-groups do not overlap each other. The x-group IDs 116382 are valid and the state of the x-groups are stored in a non-volatile memory. The x-group concept is very useful when the user wishes to use one NTUM in the different cross-connection congurations. It is much more simple to passivate the current conguration and activate the new one by passivating and activating the x-groups than deleting the current commands and creating new ones by using the Cross-Connection Conguration menu. The state of the x-groups of the NTUM can be congured and seen by using the X-Group menu. To simplify the use of this menu it is divided into two sub-menus (Cong, Display). Conguration: This menu is used to activate and passivate the x-groups. It can be accessed only when the NTUM is in stand-alone mode and the panel is unlocked. The x-group conguration menu consists of the following elds. Oper: This eld species an operation which is used either to activate (ActGrp) or to passivate (PassGrp). When the operation has been selected by using the SCROLL keys, the operation can be executed by pressing the ENTER key. Before executing the operation the x-group should be specied. X-Group: This eld is used to specify the x-group to be activated or passivated. Display: By using this menu the current state of the x-groups can be seen and their states can be changed. To see the state of the x-groups of the existing cross-connections, press ENTER when the cursor blinks over the Display eld. The text Getting is shown on the display during the message send/receive operation. After that the states of the rst two x-groups are shown on the LCD display, each on its own line. The rest of the x-groups can be viewed by using the SCROLL keys. The letter E in the status line of an x-group indicates that the x-group is empty, in other words it does not contain any cross-connections.
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The state of the x-groups can be changed by using this menu only when the NTUM is in stand-alone mode and the panel is unlocked. To change the state of the x-group, press ENTER when the cursor is on the upper line of the display. After that the question Activate/Passivate X-Group n? is shown. Press ENTER again if you want to change the state, otherwise press EXIT. Note that x-group 0 is always active and it is not possible to change its state. Interface Capacity Menu This menu displays the cross-connection capacity of the locked interfaces of the target NTUM (local or remote). The capacity of an interface is displayed in the time slots + bits format. Each time slot contains eight bits. If the interface has signalling capacity, the XD symbol is added at the end of the line. To see the capacity of the interfaces, press ENTER when the cursor blinks on the IF Cap? text. The capacities of the two rst interfaces are displayed and the rest of the interfaces can be viewed by using the SCROLL keys.
4.6.6
Copy Settings Menu

The interface parameters can be copied from one interface to another (the locking state and the congured module type are not copied). Also the cross-connection of one interface can be copied to another, or the whole cross-connection of the device can be copied. The copying possibility depends on the mode of the device and the panel state.
Copy Interface Parameters Menu The copying of the interface parameters is started by pressing the ENTER key in the IfParam eld. After that the text CpyFrom is shown on the display. Now the ENTER key must be pressed and the cursor moves on the LocIf1 text. Then the interface where parameters will be copied from is selected by using the SCROLL keys. When the interface has been selected, the reading of the parameters is activated by pressing the ENTER key and the text CpyTo is displayed. Now the ENTER key must be pressed and the cursor moves to the interface selection. The interface where parameters will be copied to is selected with the SCROLL keys and the parameters are copied by pressing the ENTER key. Copy Cross-Connections Menu The copying of the cross-connections is started by pressing the ENTER key in the X-Con eld. After that the CpyFrom text is shown on the display. Now the ENTER key must be pressed and the cursor moves on the LocIf1 text. The cross-connection(s) that are to be copied are selected using the SCROLL keys. When the interface/device has been selected, the reading of the cross-connections is activated by pressing the ENTER key and the text CpyTo is displayed. Now the ENTER key must be pressed and the cursor moves to the interface/device selection. The target to which the cross-connections are to be copied is selected with the SCROLL keys. The copy of the cross-connections is conrmed by pressing the ENTER key. If the selected interface where the copy has been performed from has connections only to one interface, the text Peer interface is IF1 appears on the LCD display where the user can select the other interface of the cross-connection(s).
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The copying of the cross-connections is conrmed by pressing the ENTER key.
4.6.7
Entering Security Menu of Tellabs 8120 Mini Node M

To enter the Security menu, press all the four keys simultaneously for about ve seconds until the display shows the items of the Security menu. This must be performed as the rst operation after a reset and within 30 seconds from the activation of the display.
4.7
Recommended Settings of Framed Interfaces

In the next chapter there are some examples of setting parameters for framed interfaces.
4.7.1
Framed Interface Used as 2048 kbit/s Trunk

Main Parameters Bit rate Framing Control type Buffer length 2048 kbit/s ON Normal 4 Frames
Bit Usage FSW usage TS0 B1 usage CRC E-bits usage TS0 B4 B5 B6 B7 B8 FSW Regenerate CRC Rem end error ind Permanent 1 HDLC HDLC HDLC HDLC ON OFF TS0
HDLC link Master clock RAI
Free TS Data 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1
CAS Free bits B5 B7 B8
ON Permanent 1 Permanent 1 Permanent 1
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NNM Parameters NNM options Neighbour supervision State monitoring Message sending Expected neighbour Node Subrack Unit Link Interface Port Any Any Any Any Any Any Off Off On
4.7.2
Framed Interface Used as 2048 kbit/s User Access Point

Main Parameters Bit rate Framing Control type Buffer length 2048 kbit/s ON Normal 4 Frames
Bit Usage FSW usage TS0 B1 usage CRC E-bits usage TS0 B4 B5 B6 B7 B8 FSW Regenerate CRC Rem end error ind Permanent 1 Permanent 1 Permanent 1 Permanent 1 Permanent 1 OFF OFF --
HDLC link Master clock RAI
Free TS Data 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1
CAS Free bits B5 B7 B8
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NNM Parameters NNM options Neighbour supervision State monitoring Message sending Expected neighbour Node Subrack Unit Link Interface Port Any Any Any Any Any Any Off Off Off
The HDLC channel is not used in a user access point. Because the HDLC channel is not used, all NNM options are set to the off state. CAS will be used if the user access device needs the channel associated signalling. CRC shall be used if the user access device can use G.704 framing with CRC-4. If the CRC is not used, the recommended usage for TS0 B1 is Permanent 1.
4.7.3
Framed Interface Used as 8448 kbit/s Trunk

Main Parameters Bit rate Framing Control type Buffer lenght 8448 kbit/s ON Normal 4 Frames
Bit Usage TS99 B1B7 usage TS99 B8 usage TS66 B8 usage CRC E-bits usage HDLC link Bit mask 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 CRC Permanent 1 Permanent 1 Rem end error ind ON TS33
Master clock RAI
OFF
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Free TS Data 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1
CAS, All Groups Free bits B5 B7 B8
4.7.4
BTE-384-M Settings
Main Parameters Bit rate Framing Control type Buffer lenght 6 x 64 kbit/s (384 kbit/s) ON Normal 4 Frames
Bit Usage FSW usage TS0 B1 usage CRC E-bits usage TS0 B4 B5 B6 B7 B8 FSW Regenerate CRC Rem end error ind Permanent 1 HDLC HDLC HDLC HDLC ON TS0
HDLC link
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Master clock RAI
OFF
Free TS Data 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1
Baseband Line connection Scrambler type Scrambler mode Output level Wetting current 2-wire full duplex V.32 Call +0 dBm Off
CAS
OFF
The Baseband settings depend on which equipment Tellabs 8120 mini node M is connected to. These settings are for connection to a Tellabs 8100 node. If the piece of equipment connected to Tellabs 8120 mini node M is SBM 384A, the Scrambler mode setting will be Answer and the Wetting current setting will be in the On state.
4.7.5
BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M Settings

Main Parameters Bit rate (depends on the module) 5 x 64 kbit/s (BTE-320-M) 9 x 64 kbit/s (BTE-576-M) 17 x 64 kbit/s (BTE-1088-2W-M) 36 x 64 kbit/s (BTE-2304-M) ON
Framing
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Main Parameters Control type Buffer length Normal 4 frames
Bit Usage FSW usage TS0 B1 usage CRC E-bits usage TS0 B4 B5 B6 B7 B8 FSW Regenerate CRC Rem end error ind Permanent 1 HDLC HDLC HDLC HDLC ON TS0
HDLC link
Master clock RAI
OFF
Free TS Data 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1
Baseband Line connection Scrambler type Scrambler mode Output level Timing 2-wire full duplex V.32 Call/Answer26 +13.5 dBm Master/Slave26
CAS
OFF
NNM Parameters NNM options Neighbour supervision State monitoring Message sending Expected neighbour Node Subrack Any Any Off Off On
26It
depends on the other end settings.
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NNM Parameters Unit Link Interface Port Any Any Any Any
4.7.6
Cross-Connection Example
IF 1; trunk <-> IF3; V.35 64kbit/s + CRC + Control Channel (8 kbit/s) IF Cap = 1TS+2bits (Use the menu to get this information) DIR = A<->B, XB, IF A = 1, IF B = 3, TS A = 4, TS B = 0 DIR = A<->B, XB, IF A = 1, IF B = 3, TS A = 6, TS B = 1, bMask A = c0H, bMask B = 03H
Fig. 39 Cross-Connecting Example
4.7.7
Binary-to-Hexadecimal Conversion Table

CCITT BITS B1 B5 0 0 0 0 B2 B6 0 0 0 0 B3 B7 0 0 1 1 B4 B8 0 1 0 1 BIT MASK IN HEXADECIMAL FORMAT 0 1 2 3
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CCITT BITS B1 B5 0 0 0 0 1 1 1 1 1 1 1 1 B2 B6 1 1 1 1 0 0 0 0 1 1 1 1 B3 B7 0 0 1 1 0 0 1 1 0 0 1 1 B4 B8 0 1 0 1 0 1 0 1 0 1 0 1
BIT MASK IN HEXADECIMAL FORMAT 4 5 6 7 8 9 A B C D E F
Examples on Binary-to-Hexadecimal Conversion CCITT BITS B1 0 0 0 0 0 0 0 1 0 1 B2 0 0 0 0 0 0 1 1 1 0 B3 0 0 0 0 0 1 1 1 0 1 B4 0 0 0 0 1 1 1 1 1 0 B5 0 0 0 1 1 1 1 1 1 0 B6 0 0 1 1 1 1 1 1 0 1 B7 0 1 1 1 1 1 1 1 1 0 B8 1 1 1 1 1 1 1 1 0 1 BIT MASK IN HEXADECIMAL FORMAT 01 03 07 0F 1F 3F 7F FF 5A A5
4.8
Service Operations and Modications

Tellabs 8120 mini node M is housed in a metallic case suitable for tabletop use. Because the conguration of Tellabs 8120 mini node M is performed with various user interfaces, most of the settings needed in installation can be done without opening the case. The Fig. 40 presents the mechanical construction of Tellabs 8120 mini node M. The numbers in brackets in the following description refer to the numbers in that gure.
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Inside the metallic case there are the main unit (#6), the interface unit (#3), the power supply (#9) under the protection cover (#7) and up to four changeable interface modules (#1 and #4). In order to make any physical changes in Tellabs 8120 mini node M hardware, such as changing the interface modules, the casing must be opened. The operation must be performed by qualied personnel only, as it involves electrical safety.
Tellabs 8120 mini node M must be disconnected from the mains supply before removing the cover as high voltages are present inside Tellabs 8120 mini node M case.
The following service operations or modications require the opening of the casing. Changing the interface modules. Changing the setting of the straps on the interface modules. Updating the controller software by changing the EPROMs. The straps of the interface modules depend on the module type. Strapping instructions can be found in 4.10 Connectors and Strappings of Framed Interfaces and 4.11 Connectors and Strappings of Unframed Interfaces. The numbered items in Fig. 40 are the following: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Upper modules (unframed interfaces) Metal top cover Interface unit VCM 402 Lower modules (framed interfaces) Main unit SMU 701 Mains supply unit protection cover Distance bolts Power supply Screws Metallic lower casing Front panel Grounding earth wire Spacers
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Fig. 40 Mechanical Construction of Tellabs 8120 Mini Node M
4.8.1
Instructions on Disassembling Tellabs 8120 Mini Node M

The following steps are required when disassembling Tellabs 8120 mini node M.
Step 1 Step 2 Step 3 Step 4
Check that Tellabs 8120 mini node M is disconnected from the mains supply. Loosen and remove all the screws at the back panel of Tellabs 8120 mini node M, slide the cover backwards and lift it off. To remove the upper modules (#1), loosen and remove the screws on the modules. The upper modules can now be lifted off. To remove the VCM402 PCB you have to remove both upper modules rst and loosen and remove the distance bolts. VCM402 can now be lifted off.
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Step 5
To remove the lower interface modules loosen and remove the distance bolts. The lower modules can now be lifted off.
When adding a new interface module, remove the metal plate covering the interface slot in the back panel. The cover is removed by bending the plate until the points of support brake. If the lower interface modules are not assembled, it is compulsory to use spacers under the distance bolts.
Step 6 Step 7
The Tellabs 8120 mini node M device is assembled in the opposite order. When connecting the transmission modules or the interface board to the pin connectors, take care not to bend the pins of the connectors. Check very carefully that the pins are set into the connectors in the correct position and that the pins are not bent.
Step 8 Step 9
Do not use unnecessary force when tightening the screws and nuts. Before connecting the power, make sure that no loose parts are left inside the box.
Step 10 When the power is connected, check that Tellabs 8120 mini node M starts running in the normal way and that no unusual alarms are visible. Check with the service computer or with the user interface of the NTU that the voltages are in normal range. If Tellabs 8120 mini node M malfunctions, disconnect the power and check that the assembly was made correctly and that the pin connectors are positioned in the correct way.
4.9
4.9.1
Unit List of Tellabs 8120 Mini Node M

Common Units
Name SMU-M SMU 701 VCM 402 SMZ 414 a b c 8990NFS40 PDU 42227 Description Multiplexer for two G.704 interfaces and four V type interfaces Main unit V interface base unit Tellabs 8120 mini node M program AC/DC power supply Unit power supply module, 1936 V DC, negative pole earthed Unit power supply module, 4060 V DC, positive pole earthed 1 1 1 01/SMU 01/SMU 01/SMU Equipping
PDU 423
27The
product has been discontinued.
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4.9.2
Main Interface Modules

(G.704 framed interfaces IF1 and IF2, 1 interface/module)
Name a LTE-M28 LTE 404 OTE-LED-M OTE 405 BTE-384-M28 BTE 406 DPZ 380 G703-75-M GDH 477 G703-120-M GDH 487 G703-8M-M28 GDH 508 BTE-2048-M28 BTE 424 BAI 482 DPZ 498 BTE-20482W-M28 BTE 496 BAI 497 DPZ 578 BTE-1088-M28 BTE 479 BAI 483 DPZ 498 BTE-4096-M28 BTE 481 BAI 484 DPZ 498 Description Line terminal 2 or 1 Mbit/s LTE-M base module Optical LED 2 or 8 Mbit/s OTE-LED-M base module Baseband module 384 kbit/s Baseband base module 128384 kbit/s Parameter PROM G703 2 Mbit/s, 75 coaxial G703-75-M base module G703 2 Mbit/s, 120 symmetrical G703-120-M base module G703 8 Mbit/s, 75 coaxial G703-8M-M base module Baseband module 2048 kbit/s Baseband base module Baseband analog submodule Signal processor PROM T-SDSL module 2048 kbit/s 2w T-SDSL base module T-SDSL analog submodule Signal processor PROM Equipping 02/SMU 1/LTE-M 02/SMU 1/OTE-LED-M 02/SMU 1/BTE-384-M 1/BTE 406 02/SMU 1/G703-75-M 02/SMU 1/G703-120-M 02/SMU 1/G703-8M-M 02/SMU 1/BTE 1/BTE 1/BTE 02/SMU 1/BTE 1/BTE 1/BTE
Baseband module 1088 kbit/s Baseband base module Baseband analog submodule Signal processor PROM Baseband module 4096 kbit/s Baseband base module Baseband analog submodule Signal processor PROM
02/SMU 1/BTE 1/BTE 1/BTE 02/SMU 1/BTE 1/BTE 1/BTE
28The
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Name k V35-G704-SM28 VDH 474 X21-G704-SM28 XDH 473 BTE-320-M28 BTE 592 DPZ 650 BTE-576-M28 BTE 596 DPZ 650 BTE-10882W-M28 BTE 559 DPZ 650 BTE-2304-M28 BTE 562 DPZ 650
Description V.35 n x 64 kbit/s2 Mbit/s scrambler V35-G704-SM base module X.21 n x 64 kbit/s2 Mbit/s scrambler X21-G704-SM base module T-SDSL module 320 kbit/s, 2-wire T-SDSL base module Signal processor PROM T-SDSL module 576 kbit/s, 2-wire T-SDSL base module Signal processor PROM T-SDSL module 1088 kbit/s, 2/4-wire T-SDSL base module Signal processor PROM
Equipping 02/SMU 1/V35-G704-SM 02/SMU 1/X21-G704-SM 02/SMU 1/BTE 1/BTE 02/SMU 1/BTE 1/BTE 02/SMU 1/BTE 1/BTE
T-SDSL module 2304 kbit/s, 2/4-wire T-SDSL base module Signal processor PROM
02/SMU 1/BTE 1/BTE
4.9.3
V Series Interface Modules

(Interfaces IF3-IF6)
Name a V35-M VDM 409 V36-M28 VDM 410 V24-DCE-M28 VDS 411 V24-DTE-M28 VDS 416 X21-M XDM 412 Description V.35 48, 56, n x 64 kbit/s interface module, 2 ch V35-M base module V.36 48, 56, n x 64 kbit/s interface module, 2 ch V36-M base module V.24/V.28 IF/DCE, 0.664 kbit/s IF module, 2 ch V24-DCE-M base module V.24/V.28 IF/DTE, 0.664 kbit/s IF module, 2 ch V24-DTE-M base module X.21 0.6n x 64 kbit/s interface module, 2 ch X21-M base module Equipping 02/SMU 1/V35-M 02/SMU 1/V36-M 02/SMU 1/V24-DCE-M 02/SMU 1/V24-DTE-M 02/SMU 1/X21-M
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Name f G703-64-M29 GCL 413 V35/V24-M29 VDM 434 HSSI-M28 HDH 708 Mini LAN Module EBH719
Description G.703 64 kbit/s co/contradir. interface module, 2 ch G703-64-M base module V.35-IEC+V.24/DCE, 0.6n x 64 kbit/s, 2 ch V35-IEC/V24-DCE-M base module HSSI, 0.6n x 64 kbit/s interface module, 1 ch HSSI-M base module Mini LAN Module, interface module, 1 ch Mini LAN Module base module
Equipping 02/SMU 1/G703-64-M 02/SMU 1/V35-IEC/V24 02/SMU 1/HSSI-M 02/SMU 1/Mini LAN Module
4.10 Connectors and Strappings of Framed Interfaces

4.10.1 G703-75-M and G703-120-M, G.703 2 Mbit/s
Front Panel of G703-75-M
Fig. 41 Front Panel of G703-75-M
The G703-75-M module is used when 75 coaxial cable interface is needed. The Tx and Rx coaxial cable shields are xed to ground. The connector is coaxial SMB.
29The
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Front Panel of G703-120-M
Fig. 42 Front Panel of G703-120-M
The G703-120-M module is used when 120 symmetrical cable interface is needed.
Fig. 43 D-Type 9-Pin Female Connector
J1 Connector Pins (v1.0) Pin 1 2 4 5 6 9 Signal Transmit signal B Transmit signal A Receive signal B Receive signal A Tx cable shield Rx cable shield
J1 Connector Pins (v2.0 or higher) Pin 1 2 4 5 6 9 Signal TxB TxA RxB RxA Ground Ground
Settings for Use with 120 Symmetrical Cable Strapping instructions for v1.0 are as follows.
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Strap CN5 CN8
Main Position ON ON
Alternative Position OFF OFF
Function of Main Position Tx cable shield grounded Rx cable shield grounded
Note that there are no strappings with v2.0 or higher.
4.10.2
LTE-M Line Terminal 1 or 2 Mbit/s
Front Panel
Fig. 44 Front Panel of LTE-M
P2 Connector Pins Pin 1 2 4 5 6 9 Signal Transmit signal B Transmit signal A Receive signal B Receive signal A Tx cable shield Rx cable shield
Settings for Use with 120 Symmetrical Cable

Strap S1 S2 Main Position 2 1 Alternative Position 1 2 Function of Main Position Tx cable shield grounded Rx cable shield not grounded
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4.10.3
G703-8M-M, 8 Mbit/s
Front Panel
Fig. 46 Front Panel of G703-8M-M
The connector is coaxial SMB. Strappings There are no strappings on the G703-8M-M module. The Rx and Tx coaxial cable shields are xed to ground.
4.10.4
OTE-LED-M, Optical LED, 2 or 8 Mbit/s
Front Panel
Fig. 47 Front Panel of OTE-M
The connector is a standard optical connector of FC type. Strappings There are no strappings on the OTE-M module.
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4.10.5
BTE-384-M, BTE-1088-M, BTE-2048-M, BTE-2048-2W-M and BTE-4096-M, 384 kbit/s4224 kbit/s
Front Panel
Fig. 48 Front Panel of BTE-384-M, BTE-1088-M, BTE-2048-M, BTE-2048-2W-M and BTE-4096-M
Pin Assignment at CN1 4-WIRE USE Pin 1 2 3 4 5 6 7 8 9 Transmit signal B Transmit signal A Not connected Receive signal B Receive signal A TX cable shield Not connected Not connected RX cable shield 2-WIRE USE BTE-384-M Not connected Not connected Not connected Tx/Rx signal B Tx/Rx signal A Not connected Not connected Not connected Cable shield BTE-2048-2W-M Tx/Rx signal B Tx/Rx signal A Not connected Not connected Not connected Not connected Not connected Not connected Cable shield
Strappings in BTE-384-M There are two strappings available on the BTE-384-M baseband module.
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S1: TX direction cable shield grounded/not grounded S2: RX direction cable shield grounded/not grounded (RX/TX direction in BTE-384 in 2-wire mode) S3/S4: wetting current enabled/disabled If wetting current is enabled, it can be turned ON or OFF in Tellabs 8000 manager. If wetting current is disabled, this function is disabled in Tellabs 8000 manager. If the customer wants to enable switching of wetting current, both S3 and S4 must be in position ON. This mode is not recommended due to EMC requirements.
Fig. 50 BTE-384-M Strappings
The strappings are located near the line connector. The default position of the strappings is off, shields not grounded.
Fig. 51 S3 and S4 Located between Line Transformers M1 and M2
Strappings in Other BTE Modules There are two strappings available on the module. J1: TX direction cable shield grounded/not grounded J4: RX direction cable shield grounded/not grounded
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Fig. 52 BTE Strappings
The strappings are located near the line connector. The default position of the strappings is off, shields not grounded. This strapping information does not concern the following BTE modules, BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M. These modules do not have any strappings.
4.10.6
BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M, 3202304 kbit/s
Front Panel
Fig. 53 Front Panel of BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M Modules
Pin Assignment at CN1 Pin 4-WIRE USE (BTE-1088-2W-M, BTE-2304-M) Transmit signal B Transmit signal A Not connected Receive signal B Receive signal A 2-WIRE USE (BTE-320-M, BTE-576-M, BTE-1088-2W-M, BTE-2304-M) Tx/Rx signal B Tx/Rx signal A Not connected Not connected Not connected
1 2 3 4 5
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Pin
4-WIRE USE (BTE-1088-2W-M, BTE-2304-M) Not connected Not connected Not connected Not connected
2-WIRE USE (BTE-320-M, BTE-576-M, BTE-1088-2W-M, BTE-2304-M) Not connected Not connected Not connected Not connected
6 7 8 9
Strappings in BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M Modules The BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M modules do not have any strappings.
4.10.7
V35-G704-SM, V.35 n x 64 kbit/s2 Mbit/s
Front Panel
Fig. 55 Front Panel of V35-G704-SM Module
D-Type 9-Pin Female Connector Pin 1 2 3 4 5 6 7 8 9 Signal Transmit Signal B Transmit Signal A Ground Receive Signal B Receive Signal A Transmit Clock B Transmit Clock A Receive Clock B Receive Clock A 103B 103A 115B 115A 113B 113A In In Out Out In In Name (DTE) 104B 104A Direction Out Out
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Strappings All strappings of the module must be in position 1.
4.10.8
X21-G704-SM, n x 64 kbit/s2Mbit/s
Front Panel
Fig. 57 Front Panel of X21-G704-SM
D-Type 9-Pin Female Connector Pin 1 2 3 4 5 6 7 8 9 Signal Transmit Signal B Transmit Signal A Ground Receive Signal B Receive Signal A Transmit Clock B Transmit Clock A Receive Clock B Receive Clock A Name (DTE) T/b T/a G R/b R/a X/b X/a S/b S/a In In Out Out In In DCE, out DCE, out Direction Out Out Notice
Strappings All strappings of the module must be in position 1 when used in DTE mode. All strappings of the module must be in position 2 when used in DCE mode. The factory settings are in position 1.
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4.11 Connectors and Strappings of Unframed Interfaces

4.11.1 V35-M, V.35 48, 56, n x 64 kbit/s Interfaces, 2 pcs
Fig. 59 Front Panel of V35-M Module
Fig. 60 34-Pin Female Connector
The V.35 interface is equipped with a rectangular 34-pin female connector according to ISO 2593 Standard. The nominal connector pin diameter is 1.6 mm. The connector is provided with two UNC 6-32 locking screws. Data and timing signals are symmetrical with a level of 0.55 V (+ 20%) to 100 load. The electrical characteristics of the control circuits are in accordance with V.28.
V35 Connector Pin Assignment Pin Number A B P S R T C D E CCITT V.35 Circuit Number --102 103A 103B 104A 104B 105 106 107 input output output Request to send Ready for sending Data set ready V.28 V.28 V.28 output Received data V.35 Input/Output Cable shield Signal ground input Transmitted data V.35 Signal Level Signal
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Pin Number F H U W Y AA V X N L NN
CCITT V.35 Circuit Number 109 108 113A 113B 114A 114B 115A 115B 140 141 142
Input/Output output input input
Signal Level
Signal
Signal detector Data terminal ready Transmitted data timing from DTE
V.28 V.28 V.35
output
Transmitted data timing from VCM
V.35
output
Received data timing from VCM
V.35
input input output
Remote loop-back Local loop-back Test indicator
V.28 V.28 V.28
4.11.2
V36-M, V.36 48, 56, n x 64 kbit/s Interfaces, 2 pcs
Fig. 61 Front Panel of V36-M Module
The V.36 interface is provided with a 37-pin female D-connector according to ISO 4902 Standard. The connector is furnished with two either UNC 4-40 or M3 locking screws.
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V36 Connector Pin Assignment Pin Number 1 19, 20 4 22 6 24 7 25 9 27 11 29 13 31 12 30 17 35 5 23 8 26 14 10 18 CCITT V.36 Circuit Number --102 103A 103B 104A 104B 105A 105B 106A 106B 107A 107B 109A 109B 108A 108B 113A 113B 114A 114B 115A 115B 140 141 142 input input output Remote loop-back Local loop-back Test indicator V.28 V.28 V.28 output Received data timing from VCM V.11 output Transmitted data timing from VCM V.11 input Transmitted data timing from DTE V.11 input Data terminal ready V.11 output Signal detector V.11 output Data set ready V.11 output Ready for sending V.11 input Request to send V.11 output Received data V.11 input Input/ Output Signal Level Signal
Cable shield Signal ground Transmitted data V.11
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4.11.3
V24-DCE-M, V.24/V.28 if/DCE, 0.664 kbit/s, 2 pcs
Fig. 63 Front Panel of V24-DCE-M Module
The V.24/V.28 interface is provided with a 25-pin female D-connector according to ISO 2110 Standard. The connector is furnished with two either UNC 4-40 or M3 locking screws. The electrical characteristics of all circuits are according to V.28.
V24/V.28 Connector Pin Assignment Pin Number 1 7 2 3 4 5 6 8 20 24 15 17 21 CCITT V.24 Circuit Number --102 103 104 105 106 107 109 108 113 114 115 140 input output input output output output input input output output input Input/Output Signal
Cable shield Signal ground Transmitted data Received data Request to send Ready for sending Data set ready Signal detector Data terminal ready Transmitted data timing from DTE Transmitted data timing from VCM Received data timing from VCM Remote loop-back
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Pin Number 18 25 9 10 11-14 16, 19 22, 23
CCITT V.24 Circuit Number 141 142 -----------
Input/Output input output output output
Signal
Local loop-back Test indicator +10 V output via 321R -10 V output via 321R Not connected Not connected Not connected
4.11.4
V24-DTE-M, V.24/V.28 if/DTE, 0.664 kbit/s, 2 pcs
Fig. 65 Front Panel of V24-DTE-M Module
V24/V.28 Connector Pin Assignment Pin Number 1 7 2 3 4 5 6 8 CCITT V.24 Circuit Number --102 103 104 105 106 107 109 output input output input input input Input/ Output Signal
Cable shield Signal ground Transmitted data Received data Request to send Ready for sending Data set ready Signal detector
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Pin Number 20 24 15 17 21 18 25 9 10 11-14 16, 19 22, 23
CCITT V.24 Circuit Number 108 113 114 115 140 141 142 -----------
Input/ Output output output input input output output input output output
Signal
Data terminal ready Transmitted data timing from VCM Transmitted data timing from DCE Received data timing from DCE Remote loop-back Local loop-back Test indicator +10 V output via 321R -10 V output via 321R Not connected Not connected Not connected
4.11.5
X21-M, X.21 1.2n x 64 kbit/s Interface, 2 pcs
Fig. 67 Front Panel of X21-M Module
The X.21 interface is provided with a 15-pin female D-connector according to ISO 4903 Standard. The connector is furnished with two either UNC 4-40 or M3 locking screws. The electrical characteristics of all circuits are according to V.11. The X.21 interface is electrically and mechanically compatible with CCITT Recommendation X.21 for point-to-point applications. Functionally, circuits C and I correspond to V.24 circuits 105 and 109. The signal levels for all circuits are X.27 (V.11).
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X.21 Connector Pin Assignment Pin Number 1 2 9 3 10 4 11 5 12 6 13 7 14 8 15 CCITT X.21 Circuit Number --T(A) T(B) C(A) C(B) R(A) R(B) I(A) I(B) S(A) S(B) X/B(A) X/B(B) G ---output/input DTE transmit signal element timing/ Byte timing Signal ground or common return Not connected output/input Signal element timing output/output Indication output/output Receive input/input Control input/input Mode DCE/DTE Signal
Cable shield Transmit
4.11.6
G703-64-M, G.703 64 kbit/s Co/Contradirectional Interface, 2 pcs
Fig. 69 Front Panel of G703-64-M Module
Fig. 70 D-Type 15-Pin Female Connector 22030_12 2013 Tellabs. Tellabs 8100 Managed Access System Tellabs 8120 Mini Node M Operating Manual
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G.703 Connector Pin Assignment Pin Number 1 2 3 4 5 6 7 8 9-15 Input/ Output Signal
output output input input output output output output
Receive data (A) Receive data (B) Transmit data (A) Transmit data (B) Receive data timing (A) Receive data timing (B) Transmit data timing (A) Transmit data timing (B) Ground
4.11.7
V35/V24-M, V.24/V.28 if/DCE, 0.664 kbit/s; V.35-IEC if, n x 64 kbit/s
Fig. 71 Front Panel of V35/V24-M Module
The V.24/V.28 interface is provided with a 25-pin female D-connector according to ISO 2110 Standard. The connector is furnished with two either UNC 4-40 or M3 locking screws. The electrical characteristics of all circuits are according to V.28. The pin assignment is the same as with the V24-DCE-M module (See 4.11.3 V24-DCE-M, V.24/V.28 if/DCE, 0.664 kbit/s, 2 pcs). The V.35-IEC interface is equipped with a 25-pin female D-connector according to ISO 2110 Standard. The connector is furnished with two either UNC 4-40 or M3 locking screws. The data and timing signals are symmetrical with a level of 0.55 V (+20%) to 100 load. The electrical characteristics of the control circuits are according to V.28.
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V.35 IEC Connector Pin Assignment Pin Number 1 7 2 14 3 16 4 5 6 8 20 24 11 15 12 17 9 21 18 25 CCITT V.35 Circuit Number --102 103A 103B 104A 104B 105 106 107 109 108 113A 113B 114A 114B 115A 115B 140 141 142 input input output Remote loop-back Local loop-back Test indicator V.28 V.28 V.28 output Received data timing from VCM V.35 output Transmitted data timing from VCM V.35 input output output output input input Request to send Ready for sending Data set ready Signal detector Data terminal ready Transmitted data timing from DTE V.28 V.28 V.28 V.28 V.28 V.35 output Received data V.35 input Input/ Output Signal Signal Level
Cable shield Signal ground Transmitted data V.35
4.11.8
HSSI-M, TIA/EIA 612, 0.68448 kbit/s
Fig. 73 Front Panel of HSSI-M Module
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Fig. 74 II-Type 50-Position SCSI Connector
HSSI-M Pin Assignment Pin Number 1 26 2 27 3 28 4 29 5 30 6 31 7 32 8 33 TIA/EIA-613 Circuit Number 102 102 115A 115B 107A 107B 104A 104B LCA30 LCB 30 114A 114B 102 102 108/2A 108/2B Input/ Output Output Output Output Output Output Output Output Output Output Output Input Input Signal Signal Level
Common Common Receiver signal element timing Receiver signal element timing DCE ready DCE ready Received data Received data Loopback request from DCE Loopback request from DCE Transmitter signal element timing Transmitter signal element timing Common Common DTE ready DTE ready
TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612
30LC
is not specied in TIA/EIA-613, the pair is reserved for future use interchange circuits from DCE.
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Pin Number 9 34 10 35 11 36 12 37 13 38 19 44 24 49 25 50
TIA/EIA-613 Circuit Number 113A 113B 143A 143B 103A 103B 144A 144B 102 102 102 102 142A 142B 102 102
Input/ Output Input Input Input Input Input Input Input Input Output Output -
Signal
Signal Level
Transmitter signal element timing Transmitter signal element timing Loopback A Loopback A Transmitted data Transmitted data Loopback B Loopback B Common Common Common Common Test mode Test mode Common Common
TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 TIA/EIA-612 -
4.11.9
Mini LAN Module, 10Base-T, 642048 kbit/s
Fig. 75 Front Panel of Mini LAN Module
Fig. 76 RJ-45 Connector 22030_12 2013 Tellabs. Tellabs 8100 Managed Access System Tellabs 8120 Mini Node M Operating Manual
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4 Installation
The 10Base-T interface is implemented with an RJ-45 connector (twisted pair). The connector contact identication for RJ-45 is presented in Fig. 76 and the pin assignment in the table below.
Pin 1 2 3 6 4,5,7,8 Signal Tx+ (TD+) Tx- (TD-) Rx+ (RD+) Rx- (RD-) Not connected
The cabling of the LAN interface must remain inside the building.
4.12 Software Update

If the controller software needs to be updated, a service computer or Tellabs 8000 manager is needed. The EPROMs inside Tellabs 8120 mini node M only include the operating system of the controller. The application software which is always needed for Tellabs 8120 mini node M to function is downloaded to the ash memories soldered on the main board of the equipment. Flash memories are of an electrically programmable and erasable memory type. If only the EPROMs are changed without performing a download, the equipment will not operate. Updating software means in most cases only the downloading of the application software. The software can be downloaded on a running device. After the download process the piece of equipment makes a reset which causes a short (3060 seconds) interruption to the data transmission going through the equipment. The downloading process does not change any settings or the cross-connection of the equipment. The following instructions describe how to update the software of Tellabs 8120 mini node M by downloading a compatible binary le through the management interface and how to replace the EPROMs on Tellabs 8120 mini node M.
4.12.1
Downloading Tellabs 8120 Mini Node M Software

The downloadable software for Tellabs 8120 mini node M is normally delivered as a binary SMZ4NN_X.Y le on a micro oppy disk, where X.Y is the version of the software (SMZ4NN can be either SMZ 414 or SMZ 430, depending on the type of Tellabs 8120 mini node). The downloadable software must be compatible with the EPROM set of the target unit. The compatibility between the target unit software and the downloadable le is dened by the following two rules: The product codes must be the same (SMZ4NN). Two versions, U.V and X.Y are compatible if U = X. The following instructions should be followed when downloading the Tellabs 8120 mini node M software.
Step 1
Check that you have the correct downloadable software available.

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Step 2 Step 3 Step 4 Step 5 Step 6 Step 7
Select the correct target if you are using Tellabs 8000 manager. Check the compatibility of the software versions. Open the Downloading window. Select the correct binary le SMZ4NN_X.Y from your directory. For example: SMZ414_4.6 Activate downloading. Wait for the operation to end. The downloading takes some minutes, including erasing time, data transfer and programming time, and checking and restarting time. After downloading, check the software version.
4.12.2
Replacing EPROMs
There are two EPROMs for the software. The EPROMs are labeled with the identication stickers which contain the following information: product code (SMZ4NN), version number and EVEN/ODD to indicate the positions of EPROMs.
The download must be disabled before installing the EPROMs with new versions. Tellabs 8120 mini node M must be disconnected from the mains supply before removing the cover as high voltages are present inside the Tellabs 8120 mini node M case.
The following instructions should be followed when installing or replacing the EPROMs. Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Step 8 Check that the unit is executing the PROM application. Remove the metallic cover of Tellabs 8120 mini node M. Remove the old EPROMs from their sockets. Put the new EPROMs (SMZ4NN rx.y ODD and EVEN) into the sockets. Check the correct places of the EPROMs (see the gure below). Check the direction of the EPROMs. The Pin #1 end is identied by a slot at the end of the component package. Replace the metallic cover of Tellabs 8120 mini node M. Download the new software version.
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Fig. 77 Location for EPROMs
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5 Faults and Actions

5.1 Terminology
The following acronyms will be used in the tables below:
Maintenance Status PMA DMA MEI Prompt maintenance alarm Deferred maintenance alarm Maintenance event information
Service Status S Service alarm
LED Indications R Y RB Red alarm LED Yellow alarm LED Red alarm LED blink
Consequent Actions TxAIS RxAIS TxTS-AIS AIS FrFEA MFrFEA AIS insertion to Tx signal AIS insertion to Rx signal AIS insertion in time slots of Tx signal AIS insertion to whole signal Frame level far-end alarm (TS0/B3 in 2 Mbit/s frame, TS66/B7 in 8 Mbit/s frame) Multiframe level far end alarm (FR0/TS sig/B6)
Also MFrFEA is transmitted if FrFEA is transmitted.
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5.2
5.2.1
Common Faults and Actions

Common Logic Faults (Block 0)
Fault Condition Reset There has been a unit reset (detected always after the power-up of the unit) Power supply (5 V,+12 V,-12 V) The voltage generated by the main supply unit is below the threshold limit. CPU memory faults RAM fault A background process has found a RAM location where the read value does not match with the written test pattern. EPROM fault The calculated check sum does not match with the stored one. FLASH faults A problem has been found when saving parameters or programs to the non-volatile memory. Incompatible EPROM/FLASH SW The downloaded software (on the ash) is not compatible with the system software on the EPROMs. Checksum err in downloaded SW The downloaded software has been corrupted. SW unpredicted This fault condition should never occur (or not yet supported). Missing settings One of the setting structures has been corrupted on the non-volatile memory. Missing application program There is no application program on the ash memory.Download the latest version of the SMZ program. Tx RAM error There is a difference between the written and read data in the Tx data buffer RAM of the framed interface. Rx RAM error There is a difference between the written and read data in the Rx data buffer RAM of the framed interface. Status PMA, S LED R Note Fault message (with delta event) appears when the unit starts to operate. Rx signal action depends on the frame level alarm of the corresponding interface. -
PMA
PMA, S
PMA
PMA PMA
R R
PMA, S PMA, S
PMA, S PMA, S
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5.2.2
Master Clock Faults (Block 0)

Fault Condition Loss of master clock locking The internal clock is used with non-empty fallback list. Fallback list warning The lowest choice is used (there is more than one choice in the fallback list). Loss of external clock The external clock input is enabled but the clock, connected to input, is not acceptable. External clock warning The external clock is included in the fallback list but the external clock input is not enabled. Phase locked loop alarm The phase locked loop of the master clock cannot be locked to any clock. Clock far end alarm choice N The state of the fallback list choice N indicates the clock far end alarm. Status MEI MEI LED Note
PMA
MEI
PMA
MEI
5.2.3
Cross-Connect Block Faults (Block 0)

Fault Condition Block IA fault Data transfer between the cross-connection and a specied block (interface/port) does not work. X-connect RAM fault Problem found when conguring the cross-connect matrix. ASIC latch error An ASIC setting cannot be corrected by a checking background process. ASIC latch warning An ASIC setting is corrected by a checking background process. Flash list check sum error One of the ash lists (e.g. a port descriptor list) has been corrupted. X-connect ash lst conict A corrupted cross-connect record has been found in the non-volatile memory after the unit reset. The record has been deleted. PortDescr ash lst conict A corrupted port descriptor record has been found in the non-volatile memory after the unit reset. The record has been deleted. Status PMA, S PMA, S PMA, S MEI LED Y Note
PMA,S
MEI
MEI
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Fault Condition Swp trk ash lst conict A corrupted swap trunk record has been found in the non-volatile memory after the unit reset. The record has been deleted. Pass trk ash lst conict A corrupted passivate trunk record has been found in the non-volatile memory after the unit reset. The record has been deleted. Time contr. X-conn warning A delta fault indicating a problem when switching the time controlled cross-connection on/off. Additional information can be read in the error log of the time control process.
Status MEI
LED
Note
MEI
PMA
5.2.4
Faults of Framed IF Tx Signal (Block 1, 2)

Fault Condition Tx Clock fault (PLL) The fault will be activated if the interface module transmitting clock phase locking to X-bus clock fails. Bus faults IA activity missing The fault will be activated if the unit cannot nd its locked interface address on the cross-connection bus. The cross-connect block should activate the IA on the bus if the interface is locked. Bus sync. fault (block 0) No cross-connection bus sync detected. AIS from X-bus The fault will be activated if the frame sync. word and RAI from the X-bus and TS0B2 changes between 0 and 1 are missing. BTE Tx line test The fault will be activated if a BTE module Tx test pattern generator is activated (used in V.54 remote loop). PMA, S R TxTS-AIS Status PMA, S LED R Tx signal TxAIS
PMA, S MEI, S
R Y
TxTS-AIS TxAIS31
MEI, S
Test pattern
31Only
when FAS is transferred through the network.
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5.2.5
Faults of Framed IF Rx Signal (Block 1, 2)

Signal and Frame Faults 1.1 Interface module missing No interface module is present but one is dened in the settings. 1.2 Wrong interface module There is a conict between the installed module and the settings. 1.3 Rx signal missing The signal level is below a specic level (the level depends on the used interface module and the selected bit rate). 1.4 Rx signal is AIS The Rx signal is detected to be AIS. 1.5 Loss of frame alignment 1.5.1 Frame alignment lost See CCITT G.706 Loss of frame alignment. 1.5.3 Frame alignment lost by CRC See CCITT G.706 Frame alignment recovery (2048 mode 915 CRC block errors detected). 1.5.2 CRC missing This fault indicates that the remote end does not use the CRC. 1.6 BER 10 -3 The bit error rate is calculated from faulty frame alignment words or from code errors. The 10E-3 alarm status depends on fault consequences (AIS insertion). 1.7 Wrong input signal 1.7.1 Own NNM messages received The control channel of the interface is used and the neighbour supervision option of the interface is ON and the received NNM message contains the same identication data as the NNM message sent to the interface. 1.7.2 Wrong IDs in NNM messages The control channel of the interface is used and the neighbour supervision option of the interface is ON and the received NNM message contains unexpected neighbour identication data. 1.7.3 No response to NNM message The control channel of the interface is used and the neighbour node supervision option of the interface is ON and no NNM (Neighbour Node Monitoring) message has been received from the interface in eight seconds. 1.8 NTU problems PMA, S R RxAIS PMA, S PMA, S DMA R R RxAIS RxAIS FrFEA FrFEA Status PMA, S PMA, S PMA, S LED R Rx signal RxAIS Tx signal -
RxAIS
Cut off
RxAIS
FrFEA
MEI, S
RxAIS
FrFEA
RxAIS
FrFEA
PMA, S
RxAIS
FrFEA
PMA, S
RxAIS
PMA, S
RxAIS
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Signal and Frame Faults 1.8.1 NTU power off / local loop The fault will be activated if the used module is BTE384 and the wetting current is ON and the received current value differs in frequency of 1.54.5 Hz and the current value difference is more than 1.5 mA. 1.8.2 NTU line break The fault will be activated if the used module is BTE384 and the wetting current is ON and the received current value is lower than 1.2 mA. 1.8.3 NTU short circuit The fault will be activated if the used module is BTE384 and the wetting current is ON and the received current value is higher than 6.5 mA. 1.9 ASIC register error The fault will be activated if difference of the write/read data of ASIC has been found. 2 Loops 2.1 Local loops 2.1.1 Interface back to equipment An interface loop is created in the interface module. It loops the transmitted data and the clock signal back to the interface receiver. 2.1.2 MUX/DEMUX back to eq. As in the Interface back to equipment loop above, but the loop is made before the interface module on the framing block in the base card. 2.1.3 MUX/DEMUX back to line Rx data is looped back to the interface transmitter. When it is used, the HDLC channel works with this line loop. All other bits are looped back to the interface. 2.1.4 Line loop made by neighbour This alarm will be activated if the HDLC channel is in use and MUX/DEMUX back to line loop has been made from the remote end, or the BTE module is used and the remote end has made loop by using the V.54 loop sequence. 2.2 Remote loops 2.2.1 Remote controlled line loop (2.1.4) This alarm will be activated if the HDLC channel is in use and MUX/DEMUX back to line loop has been made to the neighbour unit, or the BTE module is used and the V.54 loop has been made to the remote end.
Status MEI
LED Y
Rx signal RxAIS
Tx signal -
MEI
MEI
PMA, S
MEI, S
TxAIS
MEI, S
TxAIS
MEI, S
RxAIS
MEI, S
RxAIS
MEI, S
3 Multiframe level faults 3.1 Multiframe alignment lost (group N) The multiframe alignment in signalling time slot is lost. PMA, S R RxAIS/SigTS MFrFEA
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3.2 AIS in signalling (group N) The signal in the signalling time slot is detected to be AIS. Multiframe faults of the 8 Mbit/s signal are detected separately in each of the four signalling time slots (groups).
MEI, S
RxAIS/SigTS
MFrFEA
4 Far-End Alarms 4.1 Frame far-end alarm (FrFEA) The alarm state of the frame far end bit is received. The alarm status depends on fault consequences (AIS insertion into the signalling time slot). 4.2 Multiframe far-end alarm (MFrFEA) The alarm state of the multiframe far end bit is received. The alarm status depends on fault consequences (AIS insertion into the signalling time slot). MEI, S Y RxAIS/SigTS RxAIS operation can be turned off RxAIS operation can be turned off
MEI, S
RxAIS/SigTS
5 Degraded Signal 5.1 Error rate 10 -3 See CCITT G.736. The bit error rate is calculated from faulty frame alignment words or from code errors. The 10E-3 alarm status depends on fault consequences (AIS insertion). 5.2 Error rate 10 -6 The BER10E-6 error rate is calculated from CRC block errors when the bit rate is 1024 kbit/s. The counting time is 10 s and the limit for the fault condition depends on the used bit rate (2048 limit is 10). 5.3 Frequency difference The measurement period is 15 s and the phase drifting limit is 5 s. The fault will be activated if the phase drifting limit has been exceeded in three measurements out of four. 5.4 Buffer slips/1 hour The fault will be activated if one or more buffer slip(s) has been observed during the last hour. DMA R -
DMA
DMA
MEI
RB
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5.2.6
1+1 Protection Switch Fault Messages (Block 0)

Fault Condition Protection switch forced When the unit is in 1+1 protected mode and the protection switch has been forced to select a signal from IF1 or IF2. Loss of protected signal In 1+1 protection mode both interfaces IF1 and IF2 have faults which in unprotected mode have S status. Status MEI LED R Rx signal Tx signal -
PMA, S
-32
-32
5.2.7
Miscellaneous Faults of Framed Interfaces (Block 1, 2)

Fault Condition Port locking conict The fault will be activated if the cross-connection system has the port descriptor but the interface is unlocked, or if the cross-connection system has no port descriptor although the interface is locked. Use lock/unlock. HDLC overlap with X-bus The fault will be activated if the HDLC control channel bit(s) are also used by the cross-connection bus. Master clock RAI overlap with X-bus The fault will be activated if the MCLK/RAI bit is also used by the cross-connection bus. G821 unavailable state The fault will be activated if the G.821 supervision is used and the state of the signal becomes unavailable (10 consecutive SES seconds). The fault will be deactivated when 10 consecutive non-SES seconds have been found. G821 limit event This fault will be activated as a delta fault if G.821 supervision is used and at least one performance limit has been exceeded in a 15-minute period. Faults masked/Test The fault will be activated when the interface fault mask setting is ON (all interface faults will be cleared). Status DMA LED R Rx signal Tx signal -
DMA
DMA
PMA, S
DMA
MEI
5.2.8
Fault and Service Status (PMA, DMA, MEI, S) in 1+1 Mode of Framed Interfaces
In principle, both interfaces generate their own alarms (alarm messages with fault status). PMA and S statuses are processed in this mode.
32Signal
actions depend on actions of the protected interfaces.
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PMA Status Processing
In protection mode the normal PMA status is changed to the DMA status, and with the PMA status there is an additional fault condition, Loss of protected signal. In normal or prefer operating modes this special condition is created when both interfaces have a fault of category 3 or worse. In forced operating mode this condition occurs if the forced interface has a fault of categories 3 through 1. The inactive interface is not able to generate a fault with the PMA status. In protection mode an S status is generated only in the Loss of protected signal fault condition. A far-end alarm indicates that the Rx signal is out of service (S status). FrFEA: Rx frame out of service MFrFEA: Rx multiframe out of service Tx far-end alarms (FrFEA, MFrFEA) of both interfaces are generated assuming a fault status of the active interface. During a short period, when the change-over switch is in a transition phase, the far-end may generate an alarm even if there is no fault in the better interface. In forced operating mode only the active forced interface can cause far-end alarms to be sent. RxAIS and RxAIS to SigTS are always generated when FrFEA or MFrFEA are sent. AIS generating depends on the fault status of the selected interface.
S Status Processing Far-End Alarms in 1+1 Mode
RxAIS Processing
5.2.9
Fault Conditions of Framed Interfaces

Multiframe Alignment Lost The fault will be activated if two consecutive faulty multiframe alignment words have been received or if all signalling time slots in one multiframe contain only zeros (0). The fault will be deactivated when the frame alignment is found and the rst four bits of the signalling time slot are found to be zeros (0) and when the prior signalling time slot has had at least one bit in state 1. The state of TS0B3 frame far-end alarm bit will be switched if the opposite state is received in three consecutive frames. State 1 for alarm. The state of signalling time slot frame 0 B6 alarm bit will be switched if the opposite state is received in three consecutive frames. State 1 for alarm. A signal containing two or less zeros in a 2-frame period is recognized as an AIS signal. After AIS is detected, a signal containing three or more zeros in a 2-frame period is recognized not to be an AIS signal. A signal containing less than eight zeros in a 2-frame period is recognized as an AIS signal. After AIS is detected, a signal containing 12 or more zeros in a 2-frame period is recognized not to be an AIS signal. A signal in the signalling time slots containing one or no zeros in a multiframe period is recognized as an AIS signal. 2048 kbit/s and n x 64 kbit/s count time is 4 seconds: Count to activate alarm: 94 Count to inactivate alarm: 17 8448 kbit/s count time is 2 seconds: Count to activate alarm: 199 Count to inactivate alarm: 48 Count time is one second:
Frame Far-End Alarm (FrFEA) Multiframe Far-End Alarm (MFrFEA) AIS in Frame 2048 kbit/s and n x 64 kbit/s
AIS in Frame 8448 kbit/s
AIS in Multiframe Error Rate 10E-3 Limits from Frame Alignment Word
Error Rate 10E-3 Limits from Code Errors
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Speed kbit/s 8448 2048 1088 CRC Spurious Frame Alignment Limits Rate kbit/s 256 320 384 448 512 576 640 704 768 1088 2048 8448 CRC Missing
Activate 8296 1973 1033
Inactivate 893 229 126 Values from 1000 counted to start a new frame search 613 637 660 681 700 719 736 753 768 832 915 826
The fault will be activated if in 2M mode a framing has been found and the CRC multiframe alignment has been lost 100200 ms; or if in 8M mode more than six CRC alignment losses due to excessive block errors have been found in a period of 3 seconds. In 2M mode the fault will be deactivated if a CRC multiframe alignment has been found; in 8M mode if no more than one frame alignment lost due to excessive CRC block errors in a three-second period has been found.
5.3
5.3.1
Faults and Actions of Unframed Interfaces

General IF Faults of Unframed Interfaces
Fault Condition IF module missing No interface module is present but there is one dened in the settings. Wrong interface module There is a conict between the installed module and the settings. Power off in input Incoming data signal (103) out of the CCITT specs. ASIC register err HW error found in the ASIC. Status PMA, S PMA, S MEI,PMA, S LED R UI2 C1 OFF/-
OFF/-
Y R
OFF
AIS OFF
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5.3.2
IF Signal Faults of Unframed Interfaces

Fault Condition Input signal faults (UI1) Interface signal missing No carrier state of the baseband module. Faulty input signal in the case of a G.703 module. 105 off in input 105 signal off in input and 105 supervision selected in parameters. Code errors from input Code erros (HDB3, AMI or G.703 codir/contra). No input clock (NRZ). Timing errors Rx buffer slips Buffer slip in Tellabs 8100 bus interface, input signal (UI1) buffer slip (n x 64kbit/s). Tx buffer slips Buffer slip in Tellabs 8100 bus interface, output signal (UI2) buffer slip (n x 64kbit/s). Rx buffer alignment V.110 or X.30 buffer slip. Tx buffer alignment V.110 or X.30 buffer slip. DMA R AIS PMA, S R AIS Status LED UI2 C1 Note
MEI, -
AIS
Used when 105 should be continuously on.
PMA,S R
AIS
DMA
AIS
DMA
AIS
V.110, X.30 or MartisDXX framing in use.
DMA
AIS
5.3.3
Net Side Signal Faults of Unframed Interfaces

Fault Condition Input signal from net side (C2) AIS detected from network AIS from the cross-connection bus. Loss of frame sync Loss of frame sync state in the case of a V.110 or X.30. Loss of multiframe sync Loss of multiframe sync state in the case of a V.110 or X.30. Alarm from far end Alarm bit set in V.110 or X.30 frame. MEI, S PMA, S PMA, S MEI, S Y AIS V.110, X30 or MartisDXX framing in use V.110, X30 or MartisDXX framing in use Used at bit rates 2.4 kbit/s. V.110, X30 or MartisDXX framing in use Status LED UI2 C1 Note
AIS
RAI
AIS
RAI
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5.3.4
Test Loop Activation of Unframed Interfaces

Fault Condition Interface loop active Interface loop activated (by the manager). Local loop or test active Local loop or test activated (by the manager). V.54 loop active V.54 loop activated (by the interface signal or from the far-end). Status MEI, S MEI, S MEI, S LED Y Y Y UI2 AIS C1 AIS -
5.3.5
Performance Conditions of Unframed Interfaces

Fault Condition Performance conditions G821 unavailable state The fault will be activated if the G.821 supervision is used and the state of the signal becomes unavailable (10 consecutive SES seconds). The fault will be deactivated when 10 consecutive non-SES seconds have been found. G821 limit event This fault will be activated as a delta fault if the G.821 supervision is used and at least one performance limit has been exceeded in a 15-minute period. CRC errors from far end CRC errors detected at the far-end. PMA,S Available when end-to-end CRC monitoring is activated. Status LED UI2 C1 Note
DMA
Available when end-to-end CRC monitoring is activated. Available when end-to-end CRC monitoring is activated. Available when end-to-end CRC monitoring is activated. V.110, X.30 or MartisDXX framing in use.
DMA
CRC errors from near end CRC errors detected at the near-end.
DMA
FAS-errors Frame sync word errors detected in case of V.110 or X.30.
PMA
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5.3.6
Common Faults of Unframed Interfaces

Fault Condition RL state program error Remote loop state program not stored (HW error). Bus sync. fault (block 0) No cross-connection bus sync detected. IA activity missing The fault will be activated if the unit cannot nd its locked interface address on the cross-connection bus. The cross-connect block should activate the IA on the bus if the interface is locked. Faults masked/Test The fault will be activated when interface fault mask setting is ON (all interface faults will be cleared). Status PMA, S PMA, S PMA, S LED R UI2 C1 Note
R R
AIS AIS
AIS AIS
MEI, -
5.3.7
Reference Points of Unframed Interfaces

The channel board in Tellabs 8120 mini M holds four identical interface blocks numbered 3 and 6. The common parts are named block 0. The signals and directions are identied as follows.
Signals and Directions of Fault Conditions Reference point UI1 UI2 C1 C2 Signal description Input signal at the receive part of the user interface Output signal at the transmit part of the user interface XB output signal towards the X-bus interface XB input signal from the X-bus interface, net side signal
Fig. 78 Naming of Signal Reference Points
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6 Technical Specications of Tellabs 8120 Mini Node M

All CCITT references concern the Blue Book, 1988. When applicable, the references to former CCITT Recommendations have been amended to ITU-T references. These references include the date of the valid ITU-T Recommendation in case these are revised in the future. If a CCITT Recommendation has not been updated as ITU-T by the International Telecommunication Union, CCITT is used in this document.
6.1
Relevant Recommendations
The ITU-T/CCITT Recommendations concerning Tellabs 8100 trunk interfaces and user access ports are shown below.
Rec. ITU-T Date(CCITT 1988) April 1991 CCITT CCITT CCITT March 1993 CCITT CCITT March 1993 Main Characteristics of Equipment and Trunk Interfaces
G.703 G.704 G.706 G.732 G.736 G.744 G.821 G.823
Physical/electrical characteristics of hierachical digital interfaces Synchronous frame structure used at primary and secondary hierachical levels Frame alignment and CRC procedures for G.704 frames Characteristics of primary PCM multiplexing equipment operating at 2048 kbit/s Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s Second order PCM multiplex equipment operating at 8448 kbit/s Error performance of an international digital connection The control of jitter and wander on the 2048 kbit/s hierarchy
Standard Transmission Network Interfaces (2 Mbit/s and 8 Mbit/s) 2048 kbit/s framed interface 8448 kbit/s framed interface G.704, G.706, G.732, G.736, G.821, G.823 G.704, G.744, G.821, G.823
User Access Points For Unframed Data Interfaces33 V.11 (ITU-T 03/93) V.13 (ITU-T 03/93) V.14 Electrical characteristics for balanced double-current interface circuits Simulated carrier control Transmission of start-stop characters over synchronous bearer channels
33
All references to CCITT Recommendations, except those listed as ITU-T.
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User Access Points For Unframed Data Interfaces33 V.24 V.28 V.29 V.35 (CCITT Red Book) V.36 V.54 V.110 (ITU-T 09/92) X.21 (ITU-T 09/92) X.27 X.30 X.54 Interface circuits between DCE and DTE Electrical characteristics for unbalanced double-current interchange circuits 9600 bits per second modem standardised for use on point-to-point 4-wire leased telephone-type circuits Data transmission at 48 kbit/s using group band modem Modems for synchronous data transmission using group band modems Loop test devices for modems ISDN rate adaption for V-series interfaces Synchronous data network interface between DCE and DTE Same as V.11 ISDN rate adaption for X.21 interfaces Allocation of channels on international multiplex links at 64 kbit/s.
User Access Points for Voice Frequency Interfaces G.711 (CCITT) G.712 (CCITT) G.713 (CCITT) G.714 G.715 G.721 (CCITT 1986/88) G.961 (ITU-T 03/93) 64 kbit/s PCM encoding 4-wire voice frequency interface 2-wire voice frequency interface Separate performance characteristics for the encoding and decoding sides of PCM channels applicable to 4-wire interfaces Separate performance characteristics for the encoding and decoding sides of PCM channels applicable to 4-wire interfaces 32 kbit/s ADPCM Access digital section for ISDN primary rate at 2048 kbit/s
6.2
Cross-Connect
Cross-connection method Frame frequency Capacity: The sum of cross-connected signals Smallest cross-connect unit Signalling cross-connection Delay of cross-connect core Synchronous time slot interleaving 8 kHz 64 Mbit/s 8 kbit/s n x 500 bit/s (channel associated signalling = CAS) n x 64 kbit/s 1 frame = 125 s CAS bits (500 bit/s) 2 ms
Time integrity between time slots in cross-connected signals is maintained.
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6.3
Timing
Master clock frequency Master clock functional modes 16 896 kHz 30 ppm Locking to the interface rx clock (n x 64 kbit/s) Locking to external clock input (n x 64 kHz) Internal mode Clock fallback list (5 levels + internal mode) n x 64 kHz 50 ppm Frequency n x 64 kHz, n=132 Electrically G.703/75 Frequency 2048 kHz Locked to node master clock Electrically G.703 /75 75 , SMB connector G.736
Locking frequency External clock input External clock output
Connector type Jitter transfer function and jitter in the output clock
6.4
6.4.1
G.704 Framed Interface

Frame and Multiframe Buffer
Frame Buffer Mode 4 Fr34 8 Fr 8 Fr 64 Fr Bit Rates Rx Delay Frames 13 26 17 163 Tx Delay Frames 1 1 1 1 Plesiochronous buffer Main Usage
n x 64k, 2 Mbit/s, 8 Mbit/s n x 64k, 2 Mbit/s n x 64k, 2 Mbit/s, 8 Mbit/s n x 64k, 2 Mbit/s
Non-trunk lines and n x 64 kbit/s trunks Split trunk lines
Slip rate when the incoming signal is plesiochronous Buffer Length 4 Fr 8 Fr (split trunk line) 8 Fr 64 Fr Slip Rate n x 64 kbit/s n x 8/df35 2 x n x 8/df 4 x n x 8/df 32 x n x 8/df Slip Rate 2 Mbit/s 256/df 512/df 1024/df 8192/df Slip Rate 8 Mbit/s 1056/df 4224/df -
Split trunk line operation (two physical lines combined to one logical trunk):
341
Fr = 125 s difference (input x Mbit/s signal frequency - nodes x Mbit/s frequency)
35df=frequency
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Line bit rates n x 64 kbit/s (3 n 32), 2 Mbit/s All split components must have the same bit rate Tolerated delay difference between lines < 50 s
Multiframe buffer modes When Frame Buffer Is 48 frames long 64 frames long Jitter and wander tolerance MFr Buffer36 2 MFr 4MFr G.823 Rx Delay 02 MFr 13 MFr Tx Delay 1 Fr 1 Fr
6.4.2
8448 kbit/s Interface (CCITT G.704)

Electrical interface G.703 See 6.6.1 8448 kbit/s, G.703 Interface (G703-8M-M Module). Optical line See 6.6.5 Optical Line Interface 2048 kbit/s / 8448 kbit/s (OTE-LED-M Module). Multiplexing method Bits in time slot Time slots in frame Frame alignment time slot Frame alignment procedure Far end alarm CRC error check CRC error indication to the remote end Error performance monitoring Signalling multiframe time slots Multiframe time slot content Multiframe far end alarm Multiframe alignment procedure Frames in multiframe Signalling bits Synchronous time slot interleaving (G.704) 8 132 numbered 0131 TS0/B18 + TS66/B16 G.744 TS66/B7 CRC-6 in bits TS99/B16 (can be disconnected) TS99/B7 G.821 TS67,68,69,70 (G.704) F0/TS sig (0000 xyxx) F0/TS sig/B6 G.732 (same as in 2 Mbit/s interface) Separate multiframe alignment for each signalling time slot 16 4 pcs a,b,c,d / 64 kbit/s time slot 2 pcs a,b / c,d / 32 kbit/s 1 pc a / b / c /d / 16 kbit/s Control channel datalink n x 8 kbit/s (n=18) Any time slot except TS0 and TS66 Tellabs 8100 trunk lines preferable TS01/B1B8 (64 kbit/s) or TS33/B1B8
361
MFr = 2 ms
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Time Slot Usage in Trunks Cross-connectable time slots with signalling bits (CAS) Cross-connectable time slots without signalling bits Free bits 120 time slots TS5TS32, TS34TS65, TS71TS98, TS100TS131 5 time slots TS1TS4,TS33 TS66/B8, TS99/B8
6.4.3
2048 kbit/s Interface (CCITT G.704/706)

Electrical interface G.703 See 6.6.2 2048 kbit/s, G.703 Interface (G703-75-M) and 6.6.3 2048 kbit/s, G.703 Interface (G703-120-M). Line terminal See 6.6.4 2048 kbit/s and 1088 kbit/s Line Terminal Interface (LTE-M Module). Optical line See 6.6.5 Optical Line Interface 2048 kbit/s / 8448 kbit/s (OTE-LED-M Module). V.35 See 6.5.1 V.24/V.28,V.35,V.36/V.11; 1.219.2 kbit/s, 48, 56, n x 64 kbit/s. V.36/V.11 See 6.5.1 V.24/V.28,V.35,V.36/V.11; 1.219.2 kbit/s, 48, 56, n x 64 kbit/s. Multiplexing method Bits in time slot Time slots in frame Frame alignment time slot Frame alignment method Far end alarm CRC error check CRC block error indication to the remote end Error performance monitoring Signalling multiframe time slot Multiframe alignment time slot content Multiframe far end alarm Multiframe alignment method Frames in multiframe Synchronous time slot interleaving 8 32 numbered 031 TS0 G.706 TS0/B3 CRC-4 in CRC multiframe of TS0/B1 (G.704/706,CRC can be disconnected) CRC multiframe E-bit G.821 TS16 (G.704) F0/TS16 (0000 xyxx) F0/TS16/B6 G.732 16
Signalling bits
4 pcs a,b,c,d / 64 kbit/s time slots 2 pcs a,b / c,d / 32 kbit/s 1 pc a / b / c /d / 16 kbit/s
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Time slot usage in trunks: cross-connectable time slots with signalling bits (CAS) free bits Control channel datalink
30 time slots , TS1TS15, TS17TS31 TS0/B48 (see Control Channel Data Link below)
n x 8 kbit/s (n=18) Any time slot except TS0 frame alignment bits Tellabs 8100 trunk lines preferable TS0/B58 (16 kbit/s)
6.4.4
N x 64 kbit/s Interface with G.704 Type Frame

Electrical interface N x 64 kbit/s baseband interface See 6.6.6 Baseband Line Interface 64384 kbit/s (BTE-384-M Module) and 6.6.7 Baseband Line Interfaces 320...4224 kbit/s (BTE-1088-M, BTE-2048-M, BTE-2048-2W-M, BTE-4096-M, BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M Modules). 1088 kbit/s line terminal See 6.6.4 2048 kbit/s and 1088 kbit/s Line Terminal Interface (LTE-M Module). V.35 n x 64 kbit/s (signals 103,104,113,115; V.35 electrical specs.) V.36 n x 64 kbit/s (signals 103,104,113,115; V.11 electrical specs.) for V.35 and V.36 n=232, with n=32 the frame parameters are the same as in Fig. 81 in Appendix 2Fig. 81 in Appendix 2 in Tellabs 8120 Mini Node M Operating Manual (document number 22030_XX). Multiplexing method Bits in time slot Time slots in frame Frame alignment time slot Frame alignment method Far end alarm CRC error check CRC block error indication to the remote end Error performance monitoring Signalling multiframe time slot (TS sig.) Multiframe alignment time slot content Multiframe far end alarm Multiframe alignment method Frames in multiframe Signalling bits Synchronous time slot interleaving 8 N numbered 0n-1 TS0 G.706 TS0/B3 CRC-4 in CRC multiframe of TS0/B1 (G.704/706,CRC can be disconnected) CRC multiframe E-bit G.821 Last time slot in frame (TSn-1) except with n17 TS signalling=16 F0/TS signalling (0000 xyxx) F0/TS signalling/B6 G.732 16 4 pcs a, b, c, d / 64 kbit/s 2 pcs a, b / c, d / 32 kbit/s 1 pc a / b / c / d / 16 kbit/s
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Time slot usage in trunk lines: cross-connectable time slots with signalling bits (CAS) free bits Control channel data link
n-2 pcs TS0/B48 (see Control Channel Data Link below)
n x 8 kbit/s (n=18) Any time slot except TS0 frame alignment bits Tellabs 8100 trunk lines preferable TS0/B58 (16 kbit/s)
6.5
6.5.1
Unframed Data Interfaces

V.24/V.28,V.35,V.36/V.11; 1.219.2 kbit/s, 48, 56, n x 64 kbit/s
Interface type Data bit rate Framing inside Tellabs 8100 network Interface functions Handshake signal transmission37 - 105/109 - 106 - 108/107 - 140/142 SB X SA V.54 SB X SA V.54 V.13 V.54 V.24/V.28 1.2, 2.4, 4.8, 7.2, 9.6, 14.4, 19.2, 38.4 kbit/s V.110 V.24 V.35,V.36/V.11,V.24/ V.35,V.36,V.24 (n=1) V.28 48, 56 kbit/s V.110 V.24 n x 64 kbit/s n=1,2,,32 V.24
Electrical Interface - V.24 - V.35 - V.36 Interface signals Connector type - V.24 - V.35 - V.35-IEC - V.36 Test loops via data interface - RL, V.54 remote loop, (loop 2) - LL, V.54 local loop, (loop 3) ISO 2110, D-type 25-pin female connector ISO 2593, D-type 34-pin female connector ISO 2110, D-type 25-pin female connector ISO 4902, D-type 37-pin female connector V.28 for all signals V.35 for signals 103, 104, 113, 114, 115, V.28 for other signals V.28 for signals 140, 141 and 142, V.11 for other signals 102, 103, 104, 105, 106, 107, 108, 109, 113, 114, 115, 140, 141, 142
37SA,
SB, X are bits in V.110 frame
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6.5.2
X.21 1.219.2 kbit/s, 48, 56, n x 64 kbit/s

Data bit rate 1.2, 2.4, 4.8, 9.6, 19.2, 38.4, 48 kbit/s X.30 (V.110) V.24 56 kbit/s n x 64 kbit/s n=1, 2,, 32 -
Framing inside Tellabs 8100 network Interface functions Control signal transmission - C/I
V.110 V.24
S1+S3+S4S1, S3, S4 are bits in V.110 frame
S3+S4
Interface signals - bit rates 1.248 kbit/s - bit rates 56n x 64 kbit/s Electrical interface Connector type G, T, R, S, C, I G, T, R, S X.27(V.11) ISO 4903, D-type 15-pin female connector
6.5.3
Transparent 2 Mbit/s, n x 64 kbit/s

Interface type Data bit rate, n x 64 kbit/s G.703 2 Mbit/s n=32 G.703 64 kbit/s n=1 Optical Line n=32 Line Terminal n=17, 32 Baseband Line n x 64 kbit/s n=166
The G703-64-M interface is designed for indoor use only. It is not meant for external connections.
6.6
6.6.1
Data Interface Modules

8448 kbit/s, G.703 Interface (G703-8M-M Module)
Bit rate Coding Nominal impedance Nominal peak voltage Pulse width Attenuation margin Jitter tolerance Connector type 8448 kbit/s 30 ppm HDB3 75 2.37 V/75 unbalanced 59 ns 10 ns 06 dB/4 MHz G.823 50 , SMB-type connector
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6.6.2
2048 kbit/s, G.703 Interface (G703-75-M)

Bit rate Coding Nominal impedance Nominal peak voltage Pulse width Attenuation margin Jitter tolerance Connector type 2048 kbit/s 50 ppm HDB3 75 2.37 V/75 unbalanced 244 ns 25 ns 06 dB/1 MHz G.823 50 , SMB-type connector
6.6.3
2048 kbit/s, G.703 Interface (G703-120-M)

Bit rate Coding Nominal impedance Nominal peak voltage Pulse width Attenuation margin Jitter tolerance Connector type 2048 kbit/s 50 ppm HDB3 120 3.0 V/120 balanced 244 ns 25 ns 06 dB/1 MHz G.823 D-type 9-pin female connector
6.6.4
2048 kbit/s and 1088 kbit/s Line Terminal Interface (LTE-M Module)
Bit rate Coding Nominal peak voltage Pulse width Attenuation margin Jitter tolerance 2048 kbit/s 50 ppm HDB3 3.0 V / 120 symmetrical 244 ns 25 ns 036 dB at 1024 kHz G.823 460 ns 40 ns 036 dB at 544 kHz Mask like G.823 for 2048 kbit/s with the following exceptions: A0: 19.6 (18 s) A1: 0.75 A2: 0.10 f4: 50 kHz 1088 kbit/s 50 ppm HDB3
Input impedance Return loss Connector type Overvoltage protection
120 symmetrical G.703 D-type 9-pin female connector Gas discharge tubes, diodes
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6.6.5
Optical Line Interface 2048 kbit/s / 8448 kbit/s (OTE-LED-M Module)

Bit rate Transmission path Optical transmitter Nominal wave length Optical line code Symbol rate Optical receiver Min. sensitivity (BER Optical connector LED safety 10 -9) 2048 kbit/s 50 ppm 8448 kbit/s 30 ppm Standard multimode ber (G.651) Standard single mode ber (G.652) Semiconductor LED 1300 nm CMI 4096 kBd (2 Mbit/s) 16896 kBd (8 Mbit/s) PIN diode -50 dBm (2M) -42 dBm (8M) FC type with a receptacle EN 60825-1/A2: 2001 (IEC 60825-1 Ed. 1.2, 2001-08)
Functional mode multimode single mode multimode single mode LED 2 M LED 2 M LED 8 M LED 8 M
Minimum output power -20 dBm -30 dBm -20 dBm -30 dBm
Attenuation margin 30 dB 20 dB 22 dB 12 dB
Fig. 79 Class 1 LED Product
6.6.6
Baseband Line Interface 64384 kbit/s (BTE-384-M Module)

Bit rate Line interface Line code Interface impedance N x 64 kbit/s (n=16) 2/4W full-duplex Biphase space 150 symmetrical
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Output level/150 Return loss Maximum input level/150 Minimum input level/150 Equalizer Connector type
0/-6 dBm >12 dB 0 dBm -33 - -38 dBm (varies according to bit rate) Adaptive D-type 9-pin female connector
6.6.7
Baseband Line Interfaces 320...4224 kbit/s (BTE-1088-M, BTE-2048-M, BTE-2048-2W-M, BTE-4096-M, BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M Modules)
Bit rate n x 64 kbit/s, n=5 (BTE-320-M) n=5, 9 (BTE-576-M) n=5, 9, 16, 17 (BTE-1088-2W-M) n=5, 9, 17 (BTE-1088) n=16, 17, 32, 33 (BTE-2048, BTE-2048-2W-M) n=16, 17, 32, 33, 34, 36 (BTE-2304-M) n=16, 17, 32, 33, 64, 66 (BTE-4096) 4 W full-duplex (BTE-1088-M, BTE-2048-M, BTE-4096-M) 2 W full-duplex (BTE-320-M, BTE-576-M) 2 W/4W full-duplex (BTE-2048-2W-M, BTE-1088-2W-M, BTE-2304-M) 2B1Q 135 symmetrical +13.5 /+6 dBm/0 dBm > 12 dB + 15 dBm -15-30 dBm, varies according to bit rate and transmit level Adaptive D type 9-pin female connector
Line interface
Line code Interface impedance Output level/135 Return loss Maximum input level/135 Minimum input level/135 Equalizer Connector type
6.7
Service Computer (SC) Interface

Interface type Electrical interface Data bit rate Character format Connector type Interface signals Protocol V.24 V.28 9.6 kbit/s asynchronous 8 bit, no parity, 1 stop bit ISO 2110, D-type 9-pin female connector 102, 103, 104, 105, 106, 107, 108, 109 Layers 27 proprietary
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6.8
Power Supply
AC Power Supply Input voltage Type number 100...240 V AC 10% 4763 Hz 8990NFS40
DC Power Supply 24 V Input voltage Type number 1936 V DC, negative pole earthed PDU 42238
DC Power Supply 48 V Input voltage Type number 4060 V DC, positive pole earthed PDU 423
Power Consumption Dependent on furnishing, max < 40 W
6.8.1
Power Consumptions of Tellabs 8120 Mini Node M Units and Modules

Unit or Module BTE-64-M39 BTE-320-M39 BTE-384-M39 BTE-576-M39 BTE-1088-M39 BTE-1088-2W-M39 BTE-2048-M39 BTE-2048-2W-M39 BTE-2304-M39 BTE-4096-M39 G703-64-M39 G703-75-M G703-120-M G703-8M-M39 Description Baseband interface module T-SDSL interface module Baseband interface module T-SDSL interface module Baseband interface module T-SDSL interface module Baseband interface module T-SDSL interface module T-SDSL interface module Baseband interface module G.703 64 kbit/s interface module G.703 2 Mbit/s 75-ohm interface module G.703 2 Mbit/s 120-ohm interface module G.703 8 Mbit/s 75-ohm interface module Power Consumption (max) 2.3 W 2.2 W 2.3 W 2.2 W 3.0 W 2.2 W 3.5 W 4.5 W 2.2 W 3.5 W 1.5 W 1.0 W 1.0 W 1.0 W
38The 39The
power supply module has been discontinued. interface module has been discontinued.
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Unit or Module HSSI-M39 LTE-M39 Mini LAN Module OTE-LED-M SMU-M VCM-M-M VCM-V-M VCM-VM-M V24-DCE-M39 V24-DTE-M39 V35-M V35/V24-M39 V36-M39 X21-M
Description High-Speed Serial interface module Line terminal 1/2 Mbit/s 10Base-T Ethernet interface module Optical line interface module 2/8 Mbit/s Tellabs 8120 mini M base unit V-series interface base unit VF-series interface base unit V/VF-series interface base unit V.24 interface module V.24/V.28 DTE interface module V.35 interface module V.35/V.24 DCE interface module V.36 interface module X.21 interface module
Power Consumption (max) 3.9 W 1. 1W 2.0 W 3.7 W 5.0 W 1.5 W 1.0 W 1.5 W 1.5 W 1.5 W 1.5 W 1.5 W 1.5 W 1.5 W
6.9
Mechanics
Width Depth Height Weight, max. 352 mm 278 mm 75 mm 4.5 kg, depends on furnishing
6.10 Environmental Conditions

6.10.1 Climatic/Mechanical Compatibility
Tellabs 8120 mini Node (SBM 2048) HW version 6.1 or later Storage ETS 300 019-1-1:1992-02 Class1.1 Weather protected, partly temperature controlled storage locations -5C...+45C ETS 300 019-1-2:1992-02 Class2.3 Public transportation -25C...+70C Rain is not allowed ; -25C maximum ETS 300 019-1-3:1992-02 Class 3.1 Temperature-controlled locations +5C...+40C (-5C+45C)
Transport
In use
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6.11 Safety Compatibility

Tellabs 8120 mini node (SBM 2048) HW version 6.1 or later Safety EN 60950-1:2001
When AC power supply is used, Tellabs 8120 mini M must be connected to a wall socket-outlet with protective earth contact.
When DC power supply is used, Tellabs 8120 mini node M must be permanently connected to earth using the supplied grounding earth wire.
6.12 Electromagnetic Compatibility

Tellabs 8120 mini Node (SBM 2048) HW version 6.1 or later EMC EN 300 386:2005
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Appendix 1: Frame Structures

Frame Structures at Bit Rates 482048 Kbit/s
Frames Not Supporting CRC Checking and Plesiochronous Clocking
The rate adaptation and multiplexing schemes used in the basic operation mode (no CRC check or independent clocking) are as follows. 48 kbit/s CCITT V.110/X.30
V.110 Rate Adaptation 48 kbit/s 64 kbit/s Octet no. Bit no. 1 1 2 3 4 1 0 1 1 2 D1 D7 D13 D19 3 D2 D8 D14 D20 4 D3 D9 D15 D21 5 D4 D10 D16 D22 6 D5 D11 D17 D23 7 D6 D12 D18 D24 8 S1 X S3 S4
FSW: 1011 Dn: data bits S1, S3: SA =108/107 signal S4: SB = 105/109 signal X: X = 106 signal X.30: SA+SB = C/I (105/109) signal Frame length: 500 s 56 kbit/s CCITT V.110 Tables b and c
V.110 Rate Adaptation 56 kbit/s 64 kbit/s Octet no Bit no. 1 1 2 3 4 D1 D8 D15 D22 2 D2 D9 D16 D23 3 D3 D10 D17 D24 4 D4 D11 D18 D25 5 D5 D12 D19 D26 6 D6 D13 D20 D27 7 D7 D14 D21 D28 8C 0 X S3 S4 8B 1 1 1 1
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Octet no 5 6 7 8
Bit no. D29 D36 D43 D50 D30 D37 D44 D51 D31 D38 D45 D52 D32 D39 D46 D53 D33 D40 D47 D54 D34 D41 D48 D55 D35 D42 D49 D56 1 1 1 1 1 1 1 1
V.110 denes two types of frames at 56 kbit/s. Bit 8 is used as 8B in frame mode 1 (CCITT V.110 table 7b) and as 8C in mode 2 (CCITT V.110 table 7c). FSW0 - - - 1111 Dn: data bits S3: SA =108/107 signal S4: SB = 105/109 signal X: X = 106 signal Frame length: 1 ms 72, 80, 144 and 160 kbit/s
Mapping of 72, 80, 144, 160 kbit/s Data rate 64 kbit/s bit no. 1 72 80 144 160 D1 D1 D1 D10 D1 D11 2 D2 D2 D2 D11 D2 D12 3 D3 D3 D3 D12 D3 D13 4 D4 D4 D4 D13 D4 D14 5 D5 D5 D5 D14 D5 D15 6 D6 D6 D6 D15 D6 D16 7 D7 D7 D7 D16 D7 D17 8 D8 D8 D8 D17 D8 D18 8 kbit/s chan no40 A D9 D9 D9 D9 B D10 D18 D10 C D19 D D20
Di: User data bits. The index shows sequence order. The frame length is 125 s.
Frames Supporting CRC Checking and Plesiochronous Clocking

The rate adaptation and multiplexing schemes supporting CRC checking or/and plesiochronous data clocking are shown below. The CRC checking procedure is based on the CRC-4 method used in G.704. The transfer of clock phase and stufng bits is based on the method in V.110.
40A,
B, C, D: 8 kbit/s channels used to transport the n x 8 kbit/s capacity
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48 kbit/s Modied CCITT V.110/X.30

Rate Adaptation of 48 kbit/s 64 kbit/s when Supporting CRC Check and Independent Clocking Octet no Bit no. 1A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 X CFE 1 0 1 1 1 1 E4 E5 E6 C1 C2 C3 C4 1B 0 X CFE 1 0 1 1 1 1 1 1 1 C1 C2 C3 C4 1C 0 X 1 1 0 1 1 1 1 E4 E5 E6 1 1 1 1 2 D1 D7 D13 D19 D25 D31 D37 D43 D49 D55 D61 D67 D73 D79 D85 D91 3 D2 D8 D14 D20 D26 D32 D38 D44 D50 D56 D62 D68 D74 D80 D86 D92 4 D3 D9 D15 D21 D27 D33 D39 D45 D51 D57 D63 D69 D75 D91 D87 D93 5 D4 D10 D16 D22 D28 D34 D40 D46 D52 D58 D64 D70 D76 D82 D88 D94 6 D5 D11 D17 D23 D29 D35 D41 D47 D53 D59 D65 D71 D77 D83 D89 D95 7 D6 D12 D18 D24 D30 D36 D42 D48 D54 D60 D66 D72 D78 D84 D90 D96 8 S1 X S3 S4 S1 X S3 S4 S1 X S3 S4 S1 X S3 S4
56 kbit/s Modied CCITT V.110

Rate Adaptation of 56 kbit/s 64 kbit/s when Supporting CRC Check and Independent Clocking Octet no Bit no. 1 1 2 3 4 5 6 7 8 9 10 D1 D8 D15 D22 D29 D36 D43 D50 D57 D64 2 D2 D9 D16 D23 D30 D37 D44 D51 D58 D65 3 D3 D10 D17 D24 D31 D38 D45 D52 D59 D66 4 D4 D11 D18 D25 D32 D39 D46 D53 D60 D67 5 D5 D12 D19 D26 D33 D40 D47 D54 D61 D68 6 D6 D13 D20 D27 D34 D41 D48 D55 D62 D69 7 D7 D14 D21 D28 D35 D42 D49 D56 D63 D70 8A 0 X CFE S4 0 1 1 1 1 E4 8B 0 X CFE S4 0 1 1 1 1 X 8C 0 X S3 S4 0 1 1 1 1 E4 8D 0 X S3 S4 0 1 1 1 1 X
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Octet no 11 12 13 14 15 16
Bit no. D71 D78 D85 D92 D99 D106 D72 D79 D86 D93 D100 D107 D73 D80 D87 D94 D101 D108 D74 D91 D88 D95 D102 D109 D75 D82 D89 D96 D103 D110 D76 D83 D90 D97 D104 D111 D77 D84 D91 D98 D105 D112 E5 E6 C1 C2 C3 C3 S3 S4 C1 C2 C3 C4 E5 E6 1 1 1 1 S3 S4 1 1 1 1
8A: both CRC checking and plesiochronous clocking are used 8B: only CRC checking in use 8C: only plesiochronous clocking in use 8D: neither CRC check nor plesiochronous clocking in use FSW: 0 - - -01111 Dn: data bits S3: SA = 108/107 signal S4: SB = 105/109 signal X: X = 106 signal CFE: CRC bit from remote end Ci: bits for transfer of the CRC word Ei: bits for transfer of clock phase and stufng bits E6: transfers an extra D bit at positive justication inserted between D72 - D73 or D84 - D85 D73: is set to 1 when performing negative justication Frame length: 2 ms 72, 80 kbit/s
Adaptation of 72 and 80 kbit/s when Supporting CRC Check and Plesiochronous Clocking Set no 64 kbit/s bit no 1 1 2 3 4 5 6 D1 D1 D1 D1 D1 D1 2 D2 D2 D2 D2 D2 D2 3 D3 D3 D3 D3 D3 D3 4 D4 D4 D4 D4 D4 D4 5 D5 D5 D5 D5 D5 D5 6 D6 D6 D6 D6 D6 D6 7 D7 D7 D7 D7 D7 D7 8 D8 D8 D8 D8 D8 D8 8 kbit/s chan41 A D9 D9 D9 D9 D9 D9 B D10 D10 D10 D10 D10 D10 C 0 X CFE S4 0 1
418 kbit/s channel no B is not used at 72 kbit/s. Channel C uses a 16-bit long frame carrying the CRC check sum and phasing and stufng data for plesiochronous clocking.
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Set no 7 8 9 10 11 12 13 14 15 16
64 kbit/s bit no D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D8 D8 D8 D8 D8 D8 D8 D8 D8 D8
8 kbit/s chan41 D9 D9 D9 D9 D9 D9 D9 D9 D9 D9 D10 D10 D10 D10 D10 D10 D10 D10 D10 D10 1 1 1 E4 E5 E6 C1 C2 C3 C4
Set: group of data bits transmitted each 125 s FSW: 0 - - -01111 Dn: data bits S3: SA = 108/107 signal S4: SB = 105/109 signal X: X = 106 signal CFE: CRC bit from far-end Ci: bits for transfer of the CRC word Ei: bits for transfer of clock phase and stufng bits E6: transfers an extra D bit at positive justication inserted before bit D1 of set 14 D8 of set 13: is set to 1 when performing negative justication Frame length: 2 ms 144, 160 kbit/s
Adaptation of 144 and 160 kbit/s when Supporting CRC Check and Plesiochronous Clocking Set no42 64 kbit/s bit no 1 1a 1b 2a 2b D1 D11 D1 D11 2 D2 D12 D2 D12 3 D3 D13 D3 D13 4 D4 D14 D4 D14 5 D5 D15 D5 D15 6 D6 D16 D6 D16 7 D7 D17 D7 D17 8 D8 D18 D8 D18 8 kbit/s no43 A D9 D9 B D10 D10 D19 D20 X D19 D20 0 C D E
sets a and b are transmitted during the same G.704 frame (125 s). kbit/s channels B and D are not used at 160 kbit/s. Channel E uses a 16-bit long frame carrying the CRC check sum and phasing and stufng data for plesiochronous clocking.
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Set no42 3a 3b 4a 4b 5a 5b 6a 6b 7a 7b 8a 8b 9a 9b 10a 10b 11a 11b 12a 12b 13a 13b 14a 14b 15a 15b 16a 16b
64 kbit/s bit no D1 D11 D1 D11 D1 D11 D1 D11 D1 D11 D1 D11 D1 D11 D1 D11 D1 D11 D1 D11 D1 D11 D1 D11 D1 D11 D1 D11 D2 D12 D2 D12 D2 D12 D2 D12 D2 D12 D2 D12 D2 D12 D2 D12 D2 D12 D2 D12 D2 D12 D2 D12 D2 D12 D2 D12 D3 D13 D3 D13 D3 D13 D3 D13 D3 D13 D3 D13 D3 D13 D3 D13 D3 D13 D3 D13 D3 D13 D3 D13 D3 D13 D3 D13 D4 D14 D4 D14 D4 D14 D4 D14 D4 D14 D4 D14 D4 D14 D4 D14 D4 D14 D4 D14 D4 D14 D4 D14 D4 D14 D4 D14 D5 D15 D5 D15 D5 D15 D5 D15 D5 D15 D5 D15 D5 D15 D5 D15 D5 D15 D5 D15 D5 D15 D5 D15 D5 D15 D5 D15 D6 D16 D6 D16 D6 D16 D6 D16 D6 D16 D6 D16 D6 D16 D6 D16 D6 D16 D6 D16 D6 D16 D6 D16 D6 D16 D6 D16 D7 D17 D7 D17 D7 D17 D7 D17 D7 D17 D7 D17 D7 D17 D7 D17 D7 D17 D7 D17 D7 D17 D7 D17 D7 D17 D7 D17 D8 D18 D8 D18 D8 D18 D8 D18 D8 D18 D8 D18 D8 D18 D8 D18 D8 D18 D8 D18 D8 D18 D8 D18 D8 D18 D8 D18
8 kbit/s no43 D9 D9 D9 D9 D9 D9 D9 D9 D9 D9 D9 D9 D9 D9 D10 D10 D10 D10 D10 D10 D10 D10 D10 D10 D10 D10 D10 D10 D19 D20 C4 D19 D20 C3 D19 D20 C2 D19 D20 C1 D19 D20 E6 D19 D20 E5 D19 D20 E4 D19 D20 1 D19 D20 1 D19 D20 1 D19 D20 1 D19 D20 1 D19 D20 S4 D19 D20 CFE
FSW: 0 - - -01111 Dn: data bits S3: SA = 108/107 signal S4: SB = 105/109 signal X: X = 106 signal CFE: CRC bit from far-end Ci: bits for transfer of the CRC word Ei: bits for transfer of clock phase and stufng bits
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E6: transfers an extra D bit before D1 of set 13a at positive justication D8 of set 13a: is set to 1 when performing negative justication Frame length: 2 ms Adaptation of n x 64 kbit/s when Supporting CRC Check and Plesiochronous Clocking
Frame No 8 kbit/s no A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 E4 E5 E6 1 E4 E5 E6 1 E4 E5 E6 1 E4 E5 E6 B 0 X CFE S4 0 1 1 1 1 E4 E5 E6 C1 C2 C3 C4 C SB SB SB SB SB SB SB SB SB SB SB SB SB SB SB SB
The 8 kbit/s channel A carries the clock phasing and justication data at bit rates exceeding 512 kbit/s. When no independent clocking is needed or when bit rates are below 512 kbit/s, channel B is sufcient. If required, the 8 kbit/s channel C is used to carry signal SB transferring signal 105/109 or C/I FSW: 0 - - -01111 S4: SB = 105/109 signal X: X = 106 signal CFE: CRC bit from far-end Ci: bits for transfer of the CRC word Ei: bits for transfer of clock phase and stufng bits E6: transfers an extra D bit at positive justication The n x 64 kbit/s data is chopped into bytes. At positive justication the bit E6 is inserted after the last bit of the rst byte received in frame 13. A negative justication takes place by deleting the last bit of the rst byte received in frame 13.
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Frame Structures at Bit Rates below 48 Kbit/s

Bit rates below 48 kbit/s are rate adapted to n x 8 kbit/s (XB rate) according to CCITT Recommendation V.110/X.30.
Relation between Data Rates and Adapted XB Rates Data rate 1.2 kbit/s 2.4 kbit/s 9.6 kbit/s 19.2 kbit/s 38.4 kbit/s XB rate 8 kbit/s 8 kbit/s 16 kbit/s 32 kbit/s 64 kbit/s
The octet structured V.110 frame is 80 bits long.
User Rates n x 4.8 kbit/s

V.110 Frame for Adaptation of n x 4800 b/s to n x 8 kbit/s Octet no Bit no 1 1 2 3 3 5 6 7 8 9 10 0 1 1 1 1 1 1 1 1 1 2 0 D1 D7 D13 D19 E1 D25 D31 D37 D43 3 0 D2 D8 D14 D20 E2 D26 D32 D38 D44 4 0 D3 D9 D15 D21 E3 D27 D33 D39 D45 5 0 D4 D10 D16 D22 E4 D28 D34 D40 D46 6 0 D5 D11 D17 D23 E5 D29 D35 D41 D47 7 0 D6 D12 D18 D24 E6 D30 D36 D42 D48 8 0 S1 X S3 S4 E7 S1 X S3 S4
FSW: 00000000111111111 Dn: data bits S1, S3, S6, S8: SA = 108/107 signal S4, S9: SB = 105/109 signal X: X = 106 signal E1-E3: user data rate information code E4-E6: bits for transfer of clock phase information and stufng bits at plesiochronous operation. They are set to 1 when not used
157
E7: alignment bit for the four frame multiframe (MFSW=1110). E7 is set to 1 when not used E6: transfers an extra D bit at positive justication. The bit is inserted between D24 and D25 D25 : is set to 1 when performing negative justication Frame length: 2.5, 5 or10 ms, depending on bit rate The rates 600, 1200 and 2400 are mapped to the frame of the previously presented table Adaptation of n x 64 kbit/s when Supporting CRC Check and Plesiochronous Clocking as follows: Each 600 b/s bit occupies eight consecutive Dn bit positions starting from D1 (e.g. bit 1 = D1+D2+D3+D4+D5+D6+D7+D8) Each 1200 b/s bit occupies four consecutive Dn bit positions starting from D1 (e.g bit 1 = D1+D2+D3+D4, bit2 = D5+D6+D7+D8) Each 2400 b/s bit occupies two consecutive Dn bit positions (e.g. bit 1 = D1+D2, bit2 = D3+D4, bit3 = D5+D6). One V.110 frame transfers 6 bits at 600 bit/s, 12 bits at 1200 bit/s and 24 bits at 2400 bit/s.

V.110 Frame for Adaptation of n x 3600 bit/s to n x 8 kbit/s Octet no. Bit no 1 1 2 3 3 5 6 7 8 9 10 0 1 1 1 1 1 1 1 1 1 2 0 D1 D7 D11 F E1 D19 D25 D29 F 3 0 D2 D8 D12 F E2 D20 D26 D30 F 4 0 D3 D9 F D15 E3 D21 D27 F D33 5 0 D4 D10 F D16 E4 D22 D28 F D34 6 0 D5 F44 D13 D17 E5 D23 F D31 D35 7 0 D6 F D14 D18 E6 D24 F D32 D36 8 0 S1 X S3 S4 E7 S1 X S3 S4
Otherwise see the table User Rates n x 4.8 kbit/s. D19 corresponds to D25.
44F
= lling bit
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V.110 Frame for Adaptation of n x 3200 b/s to n x 8 kbit/s Octet no Bit no 1 1 2 3 3 5 6 7 8 9 10 0 1 1 1 1 1 1 1 1 1 2 0 D1 D7 D11 F E1 D17 D23 D27 F 3 0 D2 D8 D12 F E2 D18 D24 D28 F 4 0 D3 D9 F D15 E3 D19 D25 F D31 5 0 D4 D10 F D16 E4 D20 D26 F D32 6 0 D5 F D13 F E5 D21 F D29 F 7 0 D6 F D14 F E6 D22 F D30 F 8 0 S1 X S3 S4 E7 S1 X S3 S4

V.110 Frame for Adaptation of n x 3000 b/s to n x 8 kbit/s Octet no Bit no 1 1 2 3 3 5 6 7 8 9 10 0 1 1 1 1 1 1 1 1 1 2 0 D1 D7 D11 F E1 D16 D22 D26 F 3 0 D2 D8 D12 F E2 D17 D23 D27 F 4 0 D3 D9 F D15 E3 D18 D24 F D30 5 0 D4 D10 F F E4 D19 D25 F F 6 0 D5 F D13 F E5 D20 F D28 F 7 0 D6 F D14 F E6 D21 F D29 F 8 0 S1 X S3 S4 E7 S1 X S3 S4
Bit Rate Information Code E1-E3

The bit rate information is coded as follows.
Bit Information Code E1-E3 Bit rate bit/s 600 1200 E1 E2 E3 100 010
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Bit rate bit/s 2400 4800 9600 19200 38400 3600 7200 14400 28800 3000 6000 12000 24000 3200 6400 12800 25600
E1 E2 E3 110 011 011 011 011 101 101 101 101 011 011 011 011 001 001 001 001
Use of Clock Phase and Stufng Information Bits E4-E6

Network independent timing (plesiochronous) is supported at user data rates 3000 b/s and above. The E4-E6 bits are used as follows.
Clock Phase and Stufng Information Clock displacement, % 0 +20 +40 -40 -20 E4 E5 E6 111 000 001 010 011
Stufng control Positive justication of a 1 Positive justication of a 0 Negative justication 101 100 110
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Modied V.110 Frame for Transfer of CRC Check Sum Octet no Bit no 1 1 2 3 3 5 6 7 8 9 10 0 1 1 1 1 CFE C1 C2 C3 C4 2 0 D1 D7 D13 D19 E1 D25 D31 D37 D43 3 0 D2 D8 D14 D20 E2 D26 D32 D38 D44 4 0 D3 D9 D15 D21 E3 D27 D33 D39 D45 5 0 D4 D10 D16 D22 E4 D28 D34 D40 D46 6 0 D5 D11 D17 D23 E5 D29 D35 D41 D47 7 0 D6 D12 X D18 D24 E6 D30 D36 D42 D48 S3 S4 E7 S1 X S3 S4 8 0 S1
FSW: 000000001111 Dn: data bits S1, S3: SA = 108/107 signal S4: SB = 105/109 signal X: X = 106 signal E1-E3: user data rate information code E4-E6: bits for transfer of clock phase information and stufng bits at plesiochronous CFE: CRC check sum indication to the far-end Ci: CRC check sum F: lling bits (not shown) are used for adaptation of n x 3600, n x 3000 and n x 3200 b/s to n x 8 kbit/s as in the tables of the Frame Structures at Bit Rates below 48 Kbit/s presented earlier in Appendix 1.
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Appendix 2: G.704 Frame Structures

8448 kbit/s Frame Structure
Fig. 80 Frame Structure of G.704 8448 kbit/s Tellabs 8100 Managed Access System Tellabs 8120 Mini Node M Operating Manual
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2048 kbit/s Frame Structure
Fig. 81 Frame Structure of G.704 2048 kbit/s
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N x 64 kbit/s Frame Structure
Fig. 82 Frame Structure of G.704 n x 64 kbit/s; n 17
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Fig. 83 Frame Structure of G.704 n x 64 kbit/s; n > 17
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Multiframe Structure in Signalling Time Slot

(8 Mbit/s frame TS67, 68, 69, 70. 2 Mbit/s frame and n x 64 kbit/s frame with n >17 TS16. N x 64 kbit/s frame with n17 TSn-1.)
45Frame
SigTSbits1234abcd 0000 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15
SigTSbits5678abcd SASS TS17 TS18 TS19 TS20 TS21 TS22 TS23 TS24 TS25 TS26 TS27 TS28 TS29 TS30 TS31
Use 0000=M-FSW, A=FEA (1-active), S=spare abcd bits for TS1 and TS17 of the group . . . . . . . . . . . . . abcd bits for TS15 and TS31 of the group
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
45Multiframe
length is 16 frames/125 s = 2 ms (500 Hz)
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CRC Multiframe Structure in TS0 for 2 Mbit/s and n x 64 kbit/s Frames

Frame # Block #1 0 1 2 3 4 5 6 7 Block #2 8 9 10 11 12 13 14 15 C1 1 C2 1 C3 E1 C4 E2 0011011 1ASHHHH 0011011 1ASHHHH 0011011 1ASHHHH 0011011 1ASHHHH E2 = BlockII FEA (0-active) E1 = BlockI FEA (0-active) C1 0 C2 0 C3 1 C4 0 0011011 1ASHHHH 0011011 1ASHHHH 0011011 1ASHHHH 0011011 1ASHHHH
46C1C4
TS0 bits1
2345678
Use
= CRC-4 bits
A = FEA (1-active), S = spare 0011011 = FSW, H = reserved for the HDLC link 001011 = CRC M-FSW
46The
CRC multiframe length is 16 frames/125 s = 2 ms (500Hz)
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8120 M Tellabs Node Operating Manual

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Tellabs 8100 Managed Access System Tellabs 8120 Mini Node M Operating Manual

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Terms and Abbreviations

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About This Manual .............................................................................................................. 9

Tellabs 8120 Mini Node M as Tellabs 8100 Network Element.................................. 13

3.3 3.4 3.5

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Faults and Actions .................................................................................................... 123

Technical Specications of Tellabs 8120 Mini Node M .......................................... 136

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Appendix 1: Frame Structures ...................................................................................... 150

Appendix 2: G.704 Frame Structures............................................................................ 162

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About This Manual

About This Manual

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About This Manual

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Fig. 1 Tellabs 8120 Mini Node M Front Panel

Fig. 2 Example of Tellabs 8120 Mini Node M Back Panel Connectors

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2 Tellabs 8120 Mini Node M as Tellabs 8100 Network Element

2 Tellabs 8120 Mini Node M as Tellabs 8100 Network Element

Fig. 3 Architecture of Tellabs 8120 Mini Node M

2 Tellabs 8120 Mini Node M as Tellabs 8100 Network Element

Fig. 4 XB and XD Channels

Framed Interfaces IF1 and IF2

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2 Tellabs 8120 Mini Node M as Tellabs 8100 Network Element

BTE-320-M2 BTE-576-M2 BTE-10882W-M2 BTE-2048-M2 BTE-20482W-M2 BTE-1088-M2 BTE-2304-M2 BTE-4096-M2 LTE-M2, 3

V35-G704-SM2 X21-G704-SM2 OTE-LED-M

V.36/V.11 V.11 Optical LED

n x 64 kbit/s n = 233 n x 64 kbit/s n = 233 2048 kbit/s 8448 kbit/s

G703-75-M G703-120-M G703-8M-M2

G.703 G.703 G.703

2048 kbit/s 2048 kbit/s 8448 kbit/s

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2 Tellabs 8120 Mini Node M as Tellabs 8100 Network Element

User Access Ports

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2 Tellabs 8120 Mini Node M as Tellabs 8100 Network Element

Framed Interface as User Access Port

Rules for Mixing Different Interface Types

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2 Tellabs 8120 Mini Node M as Tellabs 8100 Network Element

Fig. 5 Tellabs 8120 Mini Node M Trunk Lines

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2 Tellabs 8120 Mini Node M as Tellabs 8100 Network Element

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2 Tellabs 8120 Mini Node M as Tellabs 8100 Network Element

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2 Tellabs 8120 Mini Node M as Tellabs 8100 Network Element

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2 Tellabs 8120 Mini Node M as Tellabs 8100 Network Element

Network Independent Clocking ON

User Rate 512 kbit/s Frame Rate kbit/s 16 16 8

User Rate >512 kbit/s Frame Rate kbit/s 24 24 24

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2 Tellabs 8120 Mini Node M as Tellabs 8100 Network Element