Syllabus Applied Electronics PDF

SATHYABAMA UNIVERSITY
(Established under section 3 of UGC Act, 1956) Jeppiaar Nagar, Rajiv Gandhi Salai, Chennai - 119.
SYLLABUS MASTER OF ENGINEERING PROGRAMME IN APPLIED ELECTRONICS (4 SEMESTERS) REGULATIONS 2010
FACULTY OF ELECTRONICS ENGINEERING
SATHYABAMA UNIVERSITY REGULATIONS 2010

Effective from the academic year 2010-2011 and applicable to the students admitted to the Master of Engineering / Technology / Architecture /Science (Four Semesters) 1. Structure of Programme 1.1 Every Programme will have a curriculum with syllabi consisting theory and practical such as: (i) (ii) (iii) (iv) 1.2 General core courses like Mathematics Core course of Engineering / Technology/Architecture / Science Elective course for specialization in related fields Workshop practice, Computer Practice, laboratory Work, Industrial Training, Seminar Presentation, Project Work, Educational Tours, Camps etc.
Each semester curriculum shall normally have a blend of lecture course not exceeding 7 and practical course not exceeding 4.
2.
1.3 The medium of instruction, examinations and project report will be English. Duration of the Programme A student is normally expected to complete the M.E/M.Tech./M.Arch/M.Sc Programme in 4 semesters but in any case not more than 8 consecutive semesters from the time of commencement of the course. The Head of the Department shall ensure that every teacher imparts instruction as per the number of hours specified in the syllabus and that the teacher teaches the full content of the specified syllabus for the course being taught.
3.
Requirements for Completion of a Semester A candidate who has fulfilled the following conditions shall be deemed to have satisfied the requirement for completion of a semester. 3.1 3.2 He/She secures not less than 90% of overall attendance in that semester. Candidates who do not have the requisite attendance for the semester will not be permitted to write the University Exams.
4.
Examinations The examinations shall normally be conducted between October and December during the odd semesters and between March and May in the even semesters. The maximum marks for each theory and practical course (including the project work and Viva Voce examination in the Fourth Semester) shall be 100 with the following breakup. (i) Theory Courses
Internal Assessment : University Exams : 20 Marks 80 Marks
(ii)
Practical courses
Internal Assessment : University Exams : - 100 Marks
M.E (APPLIED ELECTRONICS)
REGULATIONS 2010
5.
Passing requirements: (i) A candidate who secures not less than 50% of total marks prescribed for the course (For all courses including Theory, Practicals and Project work) with a minimum of 40 marks out of 80 in the University Theory Examinations, shall be declared to have passed in the Examination. If a candidate fails to secure a Pass in a particular course, it is mandatory that he/she shall reappear for the examination in that course during the next semester when examination is conducted in that course. However the Internal Assessment marks obtained by the candidate in the first attempt shall be retained and considered valid for all subsequent attempts.
(ii)
6.
Eligibility for the Award of Degree A student shall be declared to be eligible for the award of the M.E/M.Tech./M.Arch./M.Sc degree provided the student has successfully completed the course requirements and has passed all the prescribed examinations in all the 4 semesters within the maximum period specified in clause 2.
7.
Award of Credits and Grades: All assessments of a course will be done on absolute marks basis. However, for the purpose of reporting the performance of a candidate, Letter Grades will be awarded as per the range of total marks (out of 100) obtained by the candidate as given below:
RANGE OF MARKS FOR GRADES

Range of Marks 90-100 80-89 70-79 60-69 50-59 00-49 ABSENT Grade A++ A+ B++ B+ C F W Grade Points (GP) 10 9 8 7 6 0 0
CUMULATIVE GRADE POINT AVERAGE CALCULATION

The CGPA calculation on a 10 scale basis is used to describe the overall performance of a student in all courses from first semester to the last semester. F and W grades will be excluded for calculating GPA and CGPA.
CGPA = i C i GP i i Ci
where Ci - Credits for the subject

GP i - Grade Point for the subject
i - Sum of all subjects successfully cleared during all the semesters

M.E (APPLIED ELECTRONICS) ii REGULATIONS 2010
8.
Classification of the Degree Awarded 1 A candidate who qualifies for the award of the Degree having passed the examination in all the courses of all the semesters in his/her first appearance within a maximum period of 4 consecutive semesters after commencement of study securing a CGPA not less than 9.0 shall be declared to have passed the examination in First Class Exemplary. A candidate who qualifies for the award of the Degree having passed the examination in all the courses of all the semesters in his/her first appearance within a maximum period of 4 consecutive semesters after commencement of study, securing a CGPA not less than 7.5 shall be declared to have passed the examination in First Class with Distinction. A candidate who qualifies for the award of the Degree having passed the examination in all the courses of all the semesters in his/her first appearance within a maximum period of 4 consecutive semesters after commencement of study securing a CGPA not less than 6.0 shall be declared to have passed the examination in First Class. All other candidates who qualify for the award of the Degree having passed the examination in all the courses of all the 4 semesters within a maximum period of 8 consecutive semesters after his/her commencement of study securing a CGPA not less than 5.0 shall be declared to have passed the examination in Second Class. A candidate who is absent in semester examination in a course/project work after having registered for the same, shall be considered to have appeared in that examination for the purpose of classification of degree. For all the above mentioned classification of Degree, the break of study during the programme, will be counted for the purpose of classification of degree. A candidate can apply for revaluation of his/her semester examination answer paper in a theory course, within 1 week from the declaration of results, on payment of a prescribed fee along with prescribed application to the Controller of Examinations through the Head of Department. The Controller of Examination will arrange for the revaluation and the result will be intimated to the candidate concerned through the Head of the Department. Revaluation is not permitted for practical courses and for project work.
2.
3.
Final Degree is awarded based on the following :

CGPA 9.0 CGPA 7.50 < 9.0 CGPA 6.00 < 7.50 CGPA 5.00 < 6.00 First Class - Exemplary First Class with Distinction First Class Second Class
Minimum CGPA requirements for award of Degree is 5.0 CGPA. 9. Discipline Every student is required to observe disciplined and decorous behaviour both inside and outside the University and not to indulge in any activity which will tend to bring down the prestige of the University. If a student indulges in malpractice in any of the University theory / practical examination, he/she shall be liable for punitive action as prescribed by the University from time to time. 10. Revision of Regulations and Curriculum The University may revise, amend or change the regulations, scheme of examinations and syllabi from time to time, if found necessary.
iii
REGULATIONS 2010
M.E. - APPLIED ELECTRONICS REGULATIONS 2010 CURRICULUM SEMESTER I

Sl.No. THEORY 1. 2. 3. 4. 5. PRACTICAL 6. SECX6509 Electronic System Design Lab I 0 0 4 2 12 TOTAL CREDITS: 19 SECX5070 SCSX5035 SECX5071 SECX5017 SECX5072 Theory of Transforms and Probabilities Computer Architecture and Parallel Processing Advanced Analog Integrated Circuits Advanced Digital System Design Advanced Micro Controllers and Embedded Systems 3 3 3 3 3 1 0 1 0 0 0 0 0 0 0 4 3 4 3 3 1 2 3 4 5 SUBJECT CODE SUBJECT TITLE L T P C Page No.
SEMESTER II
Sl.No. SUBJECT CODE THEORY 1. 2. 3. 4. 5. PRACTICAL 6. SECX6510 Electronic System Design Lab - II 0 0 4 2 12 SECX5073 SECX5074 SECX5075 Advanced Digital Signal Processing CMOS Circuits Design Advanced Digital Image Processing Elective I Elective II 3 3 3 3 3 1 0 0 0 0 0 0 0 0 0 4 3 3 3 3 6 7 8 SUBJECT TITLE L T P C Page No.
TOTAL CREDITS: 18
SEMESTER III
Sl.No. 1. 2. 3. 4. 5. PRACTICAL 6. SECX6511 Electronic System Design Lab - III 0 0 4 2 12 TOTAL CREDITS: 18
M.E (APPLIED ELECTRONICS) iv REGULATIONS 2010
SUBJECT CODE THEORY SECX5084 SECX5076 SECX5051
SUBJECT TITLE Fuzzy Logic & Neural Networks Modelling of Communication Systems & Networks RF MEMS and Its Applications Elective III Elective IV
L 3 3 3 3 3
T 0 1 0 0 0
P 0 0 0 0 0
C 3 4 3 3 3
Page No. 9 10 11
SEMESTER IV
Sl.No. 1. SUBJECT CODE S35XPROJ SUBJECT TITLE Project Work & Viva Voce L 0 T 0 P 30 C 15
TOTAL CREDITS: 15 TOTAL CREDITS FOR THE COURSE: 70
LIST OF ELECTIVE SUBJECTS

Sl.No. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SUBJECT CODE SECX5077 SECX5078 SECX5079 SECX5080 SECX5081 SECX5082 SECX5067 SECX5005 SECX5013 SECX5014 SECX5031 SECX5004 SICX5010 SICX5015 SCSX5020 SPHX1003 SUBJECT TITLE VLSI Digital Signal Processing Advanced Wireless Communications Wireless Sensor Networks High Performance Networks Applied Cryptography and Data Security Reliability Engineering for Electronics Low power CMOS Design Embedded System Design DSP Integrated Circuits Embedded Control Systems Electromagnetic Interference & Compatibility Real Time Operating Systems Advanced Robotics & Automation Advanced Digital Control Systems Grid Computing Condensed Matter Physics L 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Page No. 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
L - Lecture hours; T - Tutorial hours; P - Practical hours; C - Credits
REGULATIONS 2010
SECX5070
THEORY OF TRANSFORMS AND PROBABILITIES
L 3
T 1
P 0
Credits 4
Total Marks 100
UNIT I 1-D AND 2-D TRANSFORMS
10 hrs.
Review of 1D transform, FFT, DIT FFT & DIF FFT- 2D DFT, 1D & 2D Z transforms-2D Orthogonal and Unitary transforms.
UNIT II IMAGE TRANSFORMS
10 hrs.
Introduction properties Applications of Walsh- Hadamard- Haar- Discrete Sine- Discrete Cosine- Slant,-SVD & KL transforms.
UNIT II WAVELET TRANSFORMS
10 hrs.
1D & 2D wavelet transforms: Basis and Orthogonal Basis, Time and frequency decompositions, STFT, CWT, DWT, Harr wavelet and Shannon wavelet, Fast wavelet transform, Wavelet packets.
UNIT III PROBABILITY & RANDOM VARIABLES
10 hrs.
Probability Joint & Conditional- Random variable-Distribution- Moment generation function( discrete types, continuous types) 2D variables, random variables Marginal, -Conditional-Correlation function- Probability distributions Binomial, Poisson, Uniform, Normal and Exponential distributions.
UNIT V QUEUING THEORY
10 hrs.
Markovian Queues-Single and Multiple server models- machine interference model-steady state analysis-self service queue- queuing applications.
REFERENCE BOOKS:
1. 2. 3. 4. 5. 6. 7. Arne Jensen and Anders La Cour-Harbo, Ripples in Mathematics: The Discrete Wavelet Transform, Springer, 2001 Raghuveer M Rao and Ajit.S.Bopardikar, Wavelet Transform Introduction to Theory and Applications, PHI, 1998 Soman.K.P, Resmi.N.G, Ramachandran.K.I, Insight into wavelets from theory to Practice, 3 rd edition, PHI, 2010 Gonzales.R.C, R.E. Woods, Digital Image Processing, Addison-Wesley Publishing Company, 2003 Richard Johnson, Miller & Freund, Probability and Statistics for Engineers, 7th Edition, PHI, 2007 Peyton Z.Peebles, Probability, Random Variables and random signal principles, 4th edition, TMH publication, 2001 Donald Gross and Carl M. Harris, Fundamentals of Queuing theory, 2nd edition, John Wiley and Sons, New York, 1985
UNIVERSITY EXAM QUESTION PAPER PATTERN

Max. Marks : 80 Exam Duration: 3 hrs. PART A : 6 Questions of 5 marks each without choice 30 marks PART B : (80% Problems & 20% Theory) 2 Questions from each unit of internal choice, each carrying 10 marks 50 marks
M.E (APPLIED ELECTRONICS) 1 REGULATIONS 2010
SCSX5035
COMPUTER ARCHITECTURE AND PARALLEL PROCESSING
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I REVIEW OF COMPUTER ARCHITECTURE
10 hrs.
Computer architecture evolution-Multiprocessors and Multicomputers Multivector and SIMD computers PRAM and VLSI models Architectural development tracks Conditions of parallelism Program partitioning and scheduling System interconnect architectures Parallelism in uniprocessor systems Parallel computer structures.
UNIT II PROCESSOR AND MEMORY
10 hrs.
Advanced processor technology Super scalar and vector processors Memory hierarchy Virtual memory technology Cache memory organization Shared memory organization Principles of designing pipelined processors Design of pipelined instruction unions.
UNIT III ARRAY PROCESSORS
10 hrs.
SIMD array processors SIMD computer organizations Masking and data routing mechanisms SIMD interconnect networks Barrel shifter and data manipulator shuffle Exchange and omega networks Parallel algorithms for array processors Associative array processing Performance enhancement methods (SIMD computers).
UNIT IV MULTIPROCESSOR ARCHITECTURE AND MULTIPROCESSING CONTROL
10 hrs.
Functional structures (Loosely and tightly coupled multiprocessors) multistage networks for multiprocessorsmultiprocessor operating system inter process communication system system deadlocks and protection parallel algorithms for multiprocessors.
UNIT V PARALLEL PROGRAM DEVELOPMENT AND ENVIRONMENTS
10 hrs.
Parallel programming environments software tools and environments visualization and performance tuning synchronization and multiprocessing model shared variable program structures message passing program development mapping programs onto multicomputers.
REFERENCE BOOKS:
1. Kai Hwang, Advanced computer architecture (parallelism scalability programmability), Tata McGrawHill, 2009 2. Kai Hwang Faye A.Briggs, Computer Architecture and Parallel Processing, Tata McGraw Hill, 1996 3. Terence Fountain, Peter Kacsuk, De zso Sigma, Advanced Computer Architectures (A design space approach), Pearson Education Asia, 1997

Max. Marks : 80 PART A : 6 Questions of 5 marks each without choice PART B : 2 Questions from each unit of internal choice, each carrying 10 marks
M.E (APPLIED ELECTRONICS) 2
Exam Duration: 3 hrs. 30 marks 50 marks

REGULATIONS 2010
SECX5071
ADVANCED ANALOG INTEGRATED CIRCUITS
L 3
T 1
P 0
Credits 4
Total Marks 100
UNIT I MODEL FOR INTEGRATED-CIRCUIT ACTIVE DEVICES
10 hrs.
Small-Signal Model of the Bipolar and MOS Transistor -Parasitic Elements, Specification of Transistor Frequency Response - Body Transconductance - Parasitic Elements - MOS Transistor Frequency Response .Short channel Effects, Weak Inversion and Substrate Current Flow in MOS Transistors
UNIT II SINGLE-TRANSISTOR AND MULTIPLE-TRANSISTOR AMPLIFIERS
10 hrs.
Review of Single Transistor Amplifier Stages CE and CS configuration. Amplifier with Emitter and Source Degeneration.- Cascode Configuration of Bipolar and MOS- Active Cascode - Super Source Follower- Small signal Analysis of -Differential Amplifiers , Balanced Differential Amplifiers -Device Mismatch Effects-Frequency Response and Stability of Feedback Amplifiers- Gain bandwidth relation - Instability and the Nyquist Criterion Compensation methods
UNIT III CURRENT MIRRORS, ACTIVE LOADS, AND OPERATIONAL AMPLIFIERS
10 hrs.
Bipolar and MOS models of - Simple Current Mirror , cascade current mirrors, Wilson Current Mirror- Differential pair with current mirror Load - Widlar Current Source, Supply and Temperature Insensitive Biasing, Basic Two-Stage MOS Operational Amplifiers Input Resistance, voltage Gain - Output Swing - Input Offset Voltage - CMRR- PSRREffect of Overdrive Voltages - Frequency Response analysis of the 741 Op Amp - HF Equivalent Circuit -3 dB frequency -Slew Rate - Limitations, Origin, Effect on Large Signal Sinusoidal Performance. Methods of Improving Slew rate in bipolar and MOS OP Amps Concepts of Quad OP-AMP IC
UNIT IV NONLINEAR ANALOG CIRCUITS AND NOISE IN INTEGRATED CIRCUITS
10 hrs.
Introduction - Precision Rectification - Bipolar Analog Multipliers Simple Emitter coupled Multiplier - A Complete Analog Multiplier - Gilbert Multiplier Cell DC analysis , as an Analog multiplier - as a Balanced Modulator and Phase detector. Phase-Locked Loops (PLL) Concepts- PLL in the Locked Condition - Integrated circuit PLLs - Nonlinear Function Symbols -Noise- Sources of Noise - Noise models of integrated circuit components - Noise in Operational Amplifiers - Noise Bandwidth - Noise Figure - Noise Temperature
UNIT V IC FABRICATION TECHNOLOGY
10 hrs.
Review of Integrated circuit fabrication - Photolithography - Epitaxial Growth Ion Implantation - Local Oxidation Poly silicon Deposition- Advanced Bipolar IC fabrication NPN & PNP Transistor fabrication-Passive Components in Bipolar integrated Circuits- Diffused Resistors IC capacitors - Zener Diodes-Junction Diodes MOS-Integrated circuit Fabrication - N-Channel and P-Channel Transistors - Passive Components in MOS Technology- Resistors , Capacitors and Latch up -BiCMOS Technology Hetero junction Bipolar Transistors - Interconnect Delay - Packaging Considerations for IC - Maximum Power Dissipation - Reliability Considerations in IC Packaging.
REFERENCE BOOKS:
1. 2. 3. 4. Gray & Mayer, Analysis and Design of Analog Integrated Circuits, Wiley 2005. David A.Johns and Ken Marting, Analog Integrated Circuit Design, Wiley 2002 Allen Holberg, CMOS Analog Circuit Design, 2nd edition 2002 Behzad Razavi, Design of Analog CMOS Integrated Circuits, TMH 2003


REGULATIONS 2010
SECX5017
ADVANCED DIGITAL SYSTEM DESIGN (Common to Appl. Elec., Embedded, VLSI)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I SEQUENTIAL LOGIC CIRCUITS
10 hrs.
Mealy machine, Moore machine, Trivial/Reversible/Isomorphic sequential machines, State diagrams, State table minimization, Incompletely specified sequential machines, State assignments, Design of synchronous and asynchronous sequential logic circuits working in fundamental and pulse mode.
UNIT II SYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN
10 hrs.
Analysis of clocked synchronous sequential Networks (CSSN), Modeling of CSSN-State table assignment and reduction Design of CSSN-Design of iterative circuits- ASM Chart- ASM Realization.
UNIT III ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN
10 hrs.
Analysis of Asynchronous sequential Circuits (ASC)-Flow table reduction -Races in ASC--State assignmentProblem and the Transition table-Design of ASC-Static and Dynamic hazards-Data synchronizers-Designing of Vending machine controller-Mixed operating mode Asynchronous circuits.
UNIT IV PROGRAMMABLE LOGIC DEVICES
10 hrs.
Basic concepts, programming technologies, Programmable Logic Element(PLE),Programmable Logic Array(PLA),Programmable Array Logic(PAL),Structure of standard PLDs,Complex PLDs(CPLD)-System design using PLDs-Design of combinational and sequential circuits using PLDs,Programmable PAL device using PALASM,Design of state machine using Algorithmic State Machines(ASM) chart as design tool.
UNIT V STUDY OF FPGA AND XILINX
10 hrs.
Introduction to Field Programmable Gate Arrays-Types of FPGA Xilinx XC3000 series, Logic Cell Array(LCA),Configurable Logic Blocks(CLB),Input/Output Block(IOB)-Programmable Interconnect Point(PIP),Introduction to ACT2 family and Xilinx XC4000 families, Design examples.
REFERENCE BOOKS:
1. 2. 3. 4. Donald G.Givone, Digital Principles and Design, Tata McGraw Hill, 2002 John M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2001 Nripendra N Biswas, Logic Design Theory, Prentice Hall of India, 2001 Charles H Roth Jr, Fundamentals of Logic Design, Thomson Learning, 2004

Max. Marks : 80 Exam Duration: 3 hrs. PART A : 6 Questions of 5 marks each without choice 30 marks PART B : (60% Problems & 40% Theory) 2 Questions from each unit of internal choice, each carrying 10 marks 50 marks
SECX5072
ADVANCED MICROCONTROLLERS & EMBEDDED SYSTEMS
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT 1 ADVANCED MICROCONTROLLERS

PIC Microcontroller:
10 hrs.
PIC 16C62A CPU Architecture, Registers, Instruction sets , Addressing modes, Timers, Interrupts., I2C Bus Operation, Serial EEPROM, Analog to Digital converter. Atmel AVR Microcontroller: ATmega16Architectureoverview-Nonvolatile and data Memories - Port system-Peripheral features (internal subsystems) - Programming the atmega16 Atmel AVR Operating Parameters
UNIT II ARM PROCESSOR

ARM processor fundamentals Registers - Current Program Status Register - Pipeline
10 hrs.
Exceptions, Interrupts, and the Vector Table - Core Extensions - Architecture Revisions - ARM Processor Families-ARM instruction set Thumb instruction set.
UNIT III EMBEDDED SYSTEM CONCEPTS
10 hrs.
Introduction- Components of embedded system hardware- Embedded software in a system-Process of conversion of assembly language and High level language into ROM image-Soft ware tools for designing an embedded systemEmbedded System on Chip (SoC)- Design process in embedded system-Challenges in embedded system design Design examples Smart card, Digital camera
UNIT IV EMBEDDED SYSTEM SOFTWARE
10 hrs.
Survey of software architecture: Round robin Round robin with interrupts Function queue scheduling architecture Real time operating system architecture Selecting architecture RTOS:Tasks and task states - Tasks and data Semaphores and shared data Message queues , Mail boxes and Pipes-Interrupt routine in an RTOS environment - Encapsulating semaphores and queues. Embedded software development tools: Host and Target machines Linker / locators for Embedded software Getting embedded software into the target system
UNIT V RTOS PROGRAMMING MICROCOS (COS) II
10 hrs.
Basic functions and Types of RTOSes Features and Goals of C/OS II Requirements of C/OS II Support Devices for C/OS II File Structure in C/OS II RTOS COS- system level functions time delay functions Memory allocation related functions-Semaphore related functions Mail box and queue related functions-Case study of embedded system design using COS RTOS.
REFERENCE BOOKS:
1. 2. 3. 4. 5. 6. Raj Kamal, Embedded System Architechture Programming and Design, Second Editiion, TMH Publishers, 2006 John B Peatman, Design with Microcontroller, Pearson education Asia, 1997 David E Simon, An Embedded Software Primer, Pearson education Asia, 2001 Andrew N. Sloss, ARM System Developers Guide Designing and Optimizing System Software, Morgan Kaufmann Publishers, 2005 Steven F. Barrett and Daniel J. Pack, Atmel AVR Microcontroller Primer: Programming and Interfacing, Morgan & Claypool, 1905 Jean J. Labrosse, MicroC/OS II The Real Time Kernel, Pub Group West (c), 1998


REGULATIONS 2010
SECX5073
ADVANCED DIGITAL SIGNAL PROCESSING
L 3
T 1
P 0
Credits 4
Total Marks 100
UNIT I DISCRETE RANDOM SIGNAL PROCESSING
10 hrs.
Discrete Random Processes, Expectations, Variance, Co -Variance, Scalar Product, Energy of Discrete Signals-Parsevals Theorem, Wiener Khintchine Relation- Power Spectral Density-Periodogram Sample AutocorrelationSum Decomposition Theorem, Spectral Factorization Theorem - Discrete Random Signal-Processing by Linear Systems - Simulation of White Noise - Low Pass Filtering of White Noise.
UNIT II SPECTRUM ESTIMATION
10 hrs.
Non-Parametric Methods-Correlation Method - Co-Variance Estimator- Performance Analysis of Estimators -Unbiased, Consistent Estimators-Periodogram Estimator-Barlett Spectrum Estimation-Welch Estimation-Model based Approach - AR, MA, ARMA Signal Modeling-Parameter Estimation using Yule-Walker Method
UNIT III ESTIMATION & PREDICTION
10 hrs.
Introduction-estimators_ Maximum Likelihood Estimators-Estimation of Autocorrelation sequence-Parametric and non parametric estimators--Wiener filter-Discrete Wiener Hoff equations-Recursive estimators-Kalman filter-Linear prediction, prediction errorwhiteningfilter, inverse filter-Levinson recursion, Lattice realization, and Levinson recursion algorithm forsolving Toeplitz system of equations.
UNIT IV ADAPTIVE FILTERS
10 hrs.
Introduction-Examples of adaptive filters-Method of steepest descent-LMS Algorithm- LMS Lattice algorithm-Recursive least Squares Fast Least Square-RLS Algorithm-RLS Lttice Filters-Adaptive channel equalization-Adaptive echo & noise cancellation
UNIT V MULTIRATE SIGNAL PROCESSING
10 hrs.
The change of sample rate -time domain characterization- frequency domain characterization -Cascade equivalences, filters in sampling rate alteration systems, digital filter banks and their analysis and applications, multi level filter banks- Wavelet transform and filter bank implementation of wavelet expansion of signals.
REFERENCE BOOKS:
1. 2. 3. 4. 5. Ifeachor.E.C., Jarvis.B.W., Digital Signal Processing: A Practical Approach, 2nd edition, Prentice Hall, 2002 Glenn Zelinkar, Fred J. Taylor, Advanced digital Signal processing, Theory and Applications, Mc Graw Hill, 2000 Sopocles J.Orfanidis, Optimum Signal Processing, McGraw Hill, 2000 John G.Proakis, Dimitris G.Manolakis, Digital Signal Processing, Prentice Hall of India, 2000 Monson H.Hayes, Statistical Digital Signal Processing and Modeling, John Wiley and Sons, Inc., New York, 2002


REGULATIONS 2010
SECX5074
CMOS CIRCUITS DESIGN
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I CMOS PROCESSING AND TECHNOLOGY AND MOS TRANSISTOR THEORY
10 hrs.
Silicon semiconductor technology an overview-CMOS technology n-well p-well process-Silicon on insulator and interconnect - Threshold voltage equation and second order effects-MOS models-small signal AC characteristics.
UNIT II THE MOS INVERTERS AND LAYOUT DESIGN
10 hrs.
The MOS invertors, CMOS AND NMOS inverters, Inverter ratio, DC and transient characteristics-Scaling of MOS circuits- combinational logic implementation using NMOS and CMOS - Design rules-Stick diagram and Layout design, NAND-NAND, NOR- NOR, and AOI Logic.
UNIT III CMOS CIRCUIT AND LOGIC IMPLEMENTATION
10 hrs.
CMOS logic design- Fan in and fan out. Typical CMOS NAND and NOR delays.Transistor sizing. CMOS logic structures. Complementary logic BICMOS logic. Pseudo NMOS logic. Dynamic CMOS logic. Clocked CMOS logic. Pass transistor logic. CMOS domino logic. NP domino logic. Cascade voltage switch logic. Source follower pull up logic(SFPL).Clocking strategies- I/O structures.
UNIT IV CMOS TESTING
10 hrs.
The need for testing-Manufacturing test principles, Fault models, observability, controllability, fault coverage, automatic test pattern generation, Delay fault Testing, Statistical fault analysis, Fault sampling-Design strategies for test-Chip level Test Techniques, System level test techniques-Layout design for improved testability
UNIT V CMOS SUBSYSTEM DESIGN
10 hrs.
Data path operations. Addition/subtraction. Parity generations. Comparators. Zero/one detectors. Binary Counters. ALUs. Multiplication Array. Radix-n. Wallace tree and Serial Multiplication Shifters. Memory. Control. FSM, PLA Control Implementation.
REFERENCE BOOKS:
1. Neil. H. E. Weste and K.Eshragian, Principles of CMOS VLSI Design, 2nd Edition, Addison-Wesley, 2000 2. Eugene D Fabricius, Introduction to VLSI Design, Mc Graw Hill, 2000 3. Douglas A. Pucknell and K.Eshragian, Basic VLSI Design, 3 rd Edition PHI, 2000


REGULATIONS 2010
SECX5075
ADVANCED DIGITAL IMAGE PROCESSING
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I REVIEW OF DIGITAL IMAGE PROCESSING
10 hrs.
Digital Image Representation - Fundamental Steps in Image Processing - Elements of Digital Image Processing System - Elements of Visual Perception - Image Model Sampling and Quantization Basic Relationship between Pixels.
UNIT II IMAGE ENHANCEMENT
10 hrs.
Image Enhancement Spatial Domain Gray level transformations Enhancement by Point Processing Image Subtraction Image Averaging Spatial Filtering smoothing sharpening Fourier Transform Frequency Domain filters
UNIT III IMAGE RESTORATION AND IMAGE COMPRESSION
10 hrs.
Image Restoration Image Degradation Model Noise Models Inverse Filtering Geometric Transformation Image Compression compression model error free compression lossy compression.
UNIT IV IMAGE SEGMENTATION AND DESCRIPTORS
10 hrs.
Image Segmentation Detection of Discontinuities Region Based Segmentation The Use of Motion in Segmentation Representation boundary descriptors regional descriptors use of principal components for description.
UNIT V COLOR IMAGE PROCESSING
10 hrs.
Color Image Processing color fundamentals Color Models Pseudo Color Image Processing Color Image Transformation Smoothening and Sharpening color segmentation color image compression.
REFERENCE BOOKS:
1. 2. 3. 4. Rafael C. Gonzalez, Richard E. Woods, Digital Image Processing, PHI, 2008 Anil K. Jain, Fundamentals of Digital Image Processing, Prentice Hall, 1989 William K. Prat, Digital Image Processing, Wiley Publications, 1991 Rafael C. Gonzalez, Richard E. Woods, Digital Image Processing using MATLAB, PHI, 2009


REGULATIONS 2010
SECX5084
FUZZY LOGIC AND NEURAL NETWORKS (Common to Appl. Elec., Embedded, VLSI)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I FUNDAMENTALS OF ANN
10 hrs.
Introduction Neuron Physiology Specification of the brain Eye neuron model - Fundamentals of ANN Biological neurons and their artificial models Learning processes different learning rules types of activation functions training of ANN Perceptron model ( both single & multi layer ) training algorithm problems solving using learning rules and algorithms Linear seperability limitation and its over comings
UNIT II ANN ALGORITHM
10 hrs.
Back propagation training algorithm Counter propagation network structure & operation training applications of BPN & CPN -Statistical method Boltzmann training Cauchy training Hop field network and Boltzmann machine Travelling sales man problem - BAM Structure types encoding and retrieving Adaptive resonance theory Introduction to optical neural network Cognitron & Neocognitron
UNIT III APPLICATION OF ANN
10 hrs.
Hand written and character recognition Visual Image recognition - Communication systems call processing Switching Traffic control routing and scheduling Articulation Controller - Neural Acceleration Chip (NAC )
UNIT IV INTRODUCTION TO FUZZY LOGIC
10 hrs.
Introduction to fuzzy set theory membership function - basic concepts of fuzzy sets Operations on fuzzy sets and relations, classical set Vs fuzzy set properties of fuzzy set fuzzy logic control principles fuzzy relations fuzzy rules Defuzzification Time dependent logic Temporal Fuzzy logic ( TFC ) Fuzzy Neural Network ( FANN ) - Fuzzy logic controller Fuzzification & defuzzification interface.
UNIT V APPLICATION OF FUZZY LOGIC
10 hrs.
Application of fuzzy logic to washing machine Vaccum cleaner Water level controller temperature controller - Adaptive fuzzy systems Fuzzy filters Sub band coding Adaptive fuzzy frequency hoping.
REFERENCE BOOKS:
1. 2. 3. 4. Freeman & Skapura, Neural Networks, Addison - Wesley, 1991 Zurada.J.M., Introduction to Artificial Neural Systems, West, 1992 Simon Haykin, Macmillan, Neural Networks, 1994 Yagnanarayana.B., Artificial Neural Networks, Prentice Hall of India, 2006


REGULATIONS 2010
SECX5076
MODELLING OF COMMUNICATION SYSTEMS & NETWORKS
L 3
T 1
P 0
Credits 4
Total Marks 100
UNIT I MODELLING OF COMMUNICATION SYSTEM
10 hrs.
Model of speech and picture signals, Pseudo noise sequences, Non-linear sequences, Analog channel model, Noise and fading, Digital channel model-Gilbert model of bustry channels, HF, Troposcatter and satellite channels, Switched telephone channels, Analog and Digital communication system models, Light wave system models
UNIT II SIMULATION OF RANDOM VARIABLES AND RANDOM PROCESS
10 hrs.
Univariate and multivaraiate models, Transformation of random variables, Bounds and approximation, Random process models-Markov AND a ARMA Sequences, Sampling rate for simulation, Computer generation and testing of random numbers
UNIT III ESTIMATION OF PERFORMANCE MEASURES
10 hrs.
Quality of an estimator, estimator for SNR, Probability density functions of analog communication system, BER of digital communication systems, Montre carlo method and Importance sampling method, estimation of power spectral density of a process
UNIT IV QUEUING
10 hrs.
Queuing models, M/M/I and M/M/I/N queues, Little formula, M/G/I queue, Poisson process-Properties, Characterization, Adding and Splitting, PASTA ,MMPP,Embedded Markov chain analysis of TDM systems, Polling, Random access systems
UNIT V NETWORK OF QUEUES
10 hrs.
Introduction- model of a message switched node, Reversibility-Burkes Theorem, Feed Forward Networks, Open and closed Jackson networks, Overview of BCMP Networks, Network of BCMP queues
REFERENCE BOOKS:
1. 2. 3. 4. Jeruchim.M.C., Philip Balaban and K.Sam Shanmugam, Simulation of communication systems, Plenum Press, New York Law.A.M., David Kelton, Simulation Modelling and analysis, Mc Graw Hill Inc., New York Hayes.J.F., Modelling and Analysis of Computer Communication networks, Plenum Press, New York Jerry Banks and John S.Carson, Discrete-event system Simulation, Prentice Hall,Inc., New Jersey


REGULATIONS 2010
SECX5051
RF MEMS AND ITS APPLICATIONS (Common to NanoTech, Appl. Elec.)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION
10 hrs.
MEMS-Microfabrications for MEMS -Surface micromachining of silicon -Wafer bonding for MEMS-LIGA process Micromachining of polymeric MEMS devices - Three-dimensional microfabrications.Transducers: Electromechanical transducers-Piezoelectric transducers - Electrostrictive transducers -Magnetostrictive transducers -Electrostatic actuators-Electromagnetic transducers - Electrodynamic transducers- Actuators: Electrothermal actuators-Comparison of electromechanical actuation schemes.
UNIT II MICRO SENSING FOR MEMS
10 hrs.
Piezoresistive sensing - Capacitive sensing - Piezoelectric sensing - Resonant sensing - Surface acoustic wave sensors. Materials: Materials for MEMS - Metal and metal alloys for MEMS - Polymers for MEMS - Other materials for MEMS.Metals : Evaporation Sputtering. Semiconductors :Electrical and chemical properties-Growth and deposition.Thin films for MEMS and their deposition techniques -Oxide film formation by thermal --oxidation -Deposition of silicon dioxide and silicon nitride Polysilicon film deposition -Ferroelectric thin films. Materials for polymer MEMS: Classification of polymers -UV radiation curing -SU-8 for polymer MEMS.
UNIT III MICRO MACHINING AND LITHOGRAPHY
10 hrs.
Micromachning : Bulk micromachining for silicon-based MEMS -Isotropic and orientation-dependent wet etching - Dry etching -Buried oxide process -Silicon fusion bonding -Anodic bonding -Silicon surface micromachining Sacrificial layer technology - Material systems in sacrificial layer technology - Surface micromachining using plasma etching -Combined integrated-circuit technology and anisotropic wet etching .Lithography : Microstereolithography for polymer MEMS -Scanning method - Two-photon microstereolithography Surface micromachining of polymer MEMS -Projection method -Polymeric MEMS architecture with silicon, metal and ceramics -Microstereolithography integrated with thick film lithography.
UNIT IV MEMS INDUCTORS AND CAPACITORS
10 hrs.
Introduction- MEMS/micromachined passive elements: pros and cons. MEMS inductors : Self-inductance and mutual inductance - Micromachined inductors - Effect of inductor layout - Reduction of stray capacitance of planar inductors-Approaches for improving the quality factor Folded inductors - Modeling and design issues of planar inductors Variable inductors Polymer based inductors.MEMS capacitors: MEMS gap-tuning capacitors - MEMS area-tuning capacitors Dielectric tunable capacitors. Micromachined antennae : Introduction - Overview of microstrip antennae- Basic characteristics of microstripeantennae - Design parameters of microstrip antennae - Micromachining techniques to improve antenna performance - Micromachining as a fabrication process for small antennae - Micromachined reconfigurable antennae.
UNIT V APPLICATIONS
10 hrs.
Switching: Introduction- Switch parameters- Basics of switching - Mechanical switches-Electronic switches- Switches for RF and microwave applications - Mechanical RF switches - PIN diode RF switches - Metal oxide semiconductor field effect transistors and monolithic microwave integrated circuits. RF MEMS switches : Integration and biasing issues for RF switches -Actuation mechanisms for MEMS devices-Electrostatic switching - Approaches for low-actuation-voltage switches - Mercury contact switches -Magnetic switching - Electromagnetic switching - Thermal switching.Dynamics of the switch operation : Switching time and dynamic response - Threshold voltage. MEMS switch design, modeling and evaluation:Electromechanical finite element analysis - RF design - MEMS switch design considerations.
REFERENCE BOOKS:
1. 2. 3. 4. 5. 6. Vijay K.Varadan, Vinoy.K.J and Jose.K.A, RF MEMS and Their Applications, 1st edition, John Wiley & Sons Ltd., 2003 Rai-choudhury.P, MEMS and MOEMS Technology and Applications, SPIE - The International Society for Optical Engineers, 2003 Senturia.S, Microsystem Design, Kluwer, Academic Publishers, 2001. Gardner.J.W , Varadan .V.K., Awadelkarim.O.O, Microsensors, MEMS & Smart Devices, John Wiley Sons, 2001. Campbell.S, The Science and Engineering of Microelectronic Fabrication, Oxford Univ. Press, 2001 Maluf.N, An Introduction to Microelectromechanical Systems Engineering, Artech House.


REGULATIONS 2010
SECX6509
ELECTRONIC SYSTEM DESIGN LAB - I
L 0
T 0
P 4
Credits 2
Total Marks 100
Experiments based on Advanced Analog Integrated Circuits

- Analog System Design using op-amp
Experiments based on Advanced Digital System Design

- Combinational Circuits design - Sequential Circuits Design
Experiments based on Advanced Microcontrollers & Embedded Systems

- System Design using PIC Microcontroller - System Design using AVR Microcontroller - ARM Processor based experiments
SECX6510
ELECTRONIC SYSTEM DESIGN LAB II
L 0
T 0
P 4
Credits 2
Total Marks 100
Experiments based on Advanced Digital Signal Processing

- Sampling of signals, study of aliasing error , multi-rate sampling - Adaptive filter design - Spectral Analysis of signals
Experiments based on CMOS circuit Design

- CMOS circuit Design ( Inverter, Source follower Pull up logic) & analysis of characteristics - CMOS Sub system Design
Experiments based on Advanced Digital Image Processing

- Image Enhancement Using Point Operators, neighborhood Operators - Image Restoration In presence of noise and wiener filer - Point detection, Line detection, edge detection
SECX6511
ELECTRONIC SYSTEM DESIGN LAB - III
L 0
T 0
P 4
Credits 2
Total Marks 100
Experiments based on Fuzzy Logic and Neural Networks

- Character Recognition - Prediction of parameters using BPN - Neuro Fuzzy Controller
Experiments based on Modelling of Communication Systems & Networks

- Modeling of Communication systems - Modeling of random Process model - Study of Queuing model
Experiments based on RF MEMS and its Applications

- Heat transfer module - Structural mechanic module - Microsensor module
SECX5077
VLSI DIGITAL SIGNAL PROCESSING
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION TO DSP SYSTEMS AND PROCESSING OF FIR FILTERS
10 hrs.
Introduction to DSP systems: Typical DSP algorithms, Data flow graphs - critical path, Loop bound, iteration bound, longest path matrix algorithm, Pipelining and parallel processing of FIR filters, Pipelining and parallel processing for low power.
UNIT II RETIMING, FOLDING AND UNFOLDING ALGORITHMS
10 hrs.
Retiming: definitions and properties, unfolding: unfolding algorithm, properties of unfolding, sample period reduction and parallel processing application, Folding: Folding transformation, register minimization in folded architecture, Algorithmic strength reduction in filters and transforms: 2-parallel FIR filter, 2-parallel fast FIR filter, DCT architecture, rank-order filters.
UNIT III FAST CONVOLUTION, PIPELINING AND PARALLEL PROCESSING OF IIR FILTERS
10 hrs.
Fast convolution: Cook-Toom algorithm, Winograd Algorithm, Iterated and cyclic convolution, Pipelined and parallel recursive filters: Pipeline interleaving in IIR filters, Look-Ahead pipelining in first-order IIR filters, Look-Ahead pipelining with power-of-2 decomposition, Clustered look-ahead pipelining, Parallel processing for IIR filters, combined pipelining and parallel processing for IIR filters.
UNIT IV SCALING, ROUND-OFF NOISE, BIT-LEVEL ARITHMETIC ARCHITECTURES
10 hrs.
Scaling and round-off noise: Scaling and round-off noise scaling operation, round-off noise, state variable description of digital filters, scaling and round-off noise computation, round-off noise in pipelined IIR filters, Bit-level arithmetic architectures: parallel multipliers with sign extension, parallel carry-ripple and carry-save multipliers, Design bit-serial multipliers, bit-serial FIR filter design and implementation, Canonic Sign Digit(CSD) arithmetic and CSD multiplication using Horners rule for precision improvement, Distributed Arithmetic fundamentals.
UNIT V NUMERICAL STRENGTH REDUCTION, SYNCHRONOUS, WAVE AND ASYNCHRONOUS 10 hrs. PIPELINING
Numerical strength reduction: sub-expression elimination, multiple constant multiplications, sub-expression sharing in digital filters, additive and multiplicative number splitting Synchronous pipelining: Synchronous pipelining and clocking styles, Wave pipelining: Wave pipelining, constraint space diagram and degree of wave pipelining, implementation of wave-pipelined systems, Asynchronous pipelining: asynchronous pipelining, signal transition graphs (STG)
REFERENCE BOOKS:
1. Keshab K.Parhi, VLSI Digital Signal Processing Systems- Design and implementation, Wiley Interscience Publications, 2007 2. Meyer.U., Baese, Digital Signal Processing with Field Programmable Gate Arrays, Springer, Second Edition, 2004


REGULATIONS 2010
SECX5078
ADVANCED WIRELESS COMMUNICATIONS
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I SYSTEMS AND STANDARDS OF WIRELESS COMMUNICATION
10 hrs.
Introduction, History of Mobile cellular: AMPS system (first generation)-second generation system-3G system-4G system. International standard bodies for wireless communication: ITU standard-IMT 2000 standardization structure in ITU-IEEE standard-various standard of IEEE802. Spectrum allocation for wireless: ITU spectrum for 3G. Spectrum efficiency considerations, Cellular systems: Circuit switched system-Analog system-Digital system-Packet switched system, Frequency reuse concept. Handoff: Inter BS handoff-Inter system handoff-Mobile controlled handoff-N/W controlled handoff- Mobile assisted handoff.
UNIT II DIGITAL CELLULAR SYSTEM(2G) AND B2G SYSTEMS
10 hrs.
Digital Technologies: Digital detection- carrier recovery-carrier phase tracking using PLL-phase equalization circuits. ARQ techniques (Different types):The expected number of transmission- transmission efficiency-undetected error rate. GSM Architecture: The mobile station-the base station subsystem-Network & switching subsystem-radio resource management-mobility management-network management. General Packet Radio Interface (GPRS): GPRS air interfaceGPRS network architecture- transmission plane & signaling plane- GPRS traffic performance. EDGE (Enhanced Data Rate for Global Evaluation): Network architecture-Network control.
UNIT III WIRELESS APPLICATION PROTOCOL AND WIRE REPLACEMENT DEVICES
10 hrs.
WAP: WAP model WAP Gateway WAP Protocols-Wireless Datagram protocol(WDP)- Wireless Transport layer security(WTLS)- Wireless Transaction protocol(WTP)- Wireless Session protocol(WSP)- Wireless Application Environment(WAE)- WAP user Agent profile and caching model- WAP protocol stack over GPRS- WAP Developer tool kits. Wire Replacement Devices: Blue tooth - Terminology and technologies- architecture- protocol stack-technical features. Description- technologies & technical features of Zigbee - Ultra wideband (UWB) - IrDA (Infrared Data Association - RFID(Radio Frequency Identification - Comparison of wire Replacement devices
UNIT IV 3G SYSTEMS
10 hrs.
3GNetworks/IMT 2000-list of 3G features and Performance. WCDMA-UMTS(UTRA FDD):Physical layer-transport channels-Transmission characteristics. UMTS network architecture: Description-MAC layer-RLC layer-RRc layer. VoIP technology (3GPP Release 4):VoIP protocol layers-H.323 protocol layer-H.323 call establishment and Release. CDMA 2000:Radio Interface parameters of CDMA 2000 FDD-channel structure-chip rates-modulation and spreading(single carrier)-Transmission characteristics(single carrier)-1xEV-DO-1xEV-DV.
UNIT V INTELLIGENT NETWORK FOR WIRELESS COMMUNICATION
10 hrs.
Advanced Intelligent Network (AIN): Intelligent Network Evolution-AINs Network characteristics- AIN ElementsAIN Interface. SS7 Network for AIN:SS7 protocol model-SS7 Network link deployment for AIN.AIN for mobile communication Asynchronous transfer mode (ATM) technology: LAN application-connectionless services-ATM packet switching technology ATM connection oriented service-switch fabrics-buffering strategies-convention resolution. Wireless Information Superhighway.
REFERENCE BOOKS:
1. 2. 3. 4. William C.Y.Lee, Wireless and Cellular Telecommunications, 3rd edition, McGraw Hill, 2005. Yi bing Lin, Wireless and mobile Network architecture, Wiley John Schiller, Mobile Communications, 2005 David Tse, Pramod Viswanath, Fundamentals of wireless communications, 2004


REGULATIONS 2010
SECX5079
WIRELESS SENSOR NETWORKS (Common to Appl. Elec., Embedded, CSE)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I SENSOR NETWORK ARCHITECTURE

Concept of sensor network Introduction, Applications, sensors
10 hrs.
Single node architecture: hardware and software components of a sensor node, Tiny OS operating system, nesC language. Wireless Sensor Network architecture: typical network architectures, data relaying strategies, aggregation, role of energy in routing decisions.
UNIT II ADDRESSING & SYNCHRONISATION
10 hrs.
MAC layer strategies: MAC layer protocols, scheduling sleep cycles, energy management, contention-based protocols, schedule-based protocols, 802.15.4 standard. Naming and addressing: Addressing services publish-subscribe topologies. Clock Synchronization: clustering for synchronization, sender-receiver and receiver-receiver synchronization, error analysis. Power Management per node, system-wide, sentry services, sensing coverage
UNIT III LOCALIZATION
10 hrs.
Node Localization: absolute and relative localization, triangulation, multi-hop localization and error analysis, anchoring, geographic localization, target tracking, localization and identity management, Walking GPS, range free solutions. Data Gathering - Tree construction algorithms and analysis - Asymptotic capacity- Lifetime optimization formulationsStorage and retrieval. Deployment & Configuration - Sensor deployment, scheduling and coverage issues, self configuration and topology control.
UNIT IV ROUTING TECHNIQUES
10 hrs.
Routing: Agent-based routing, random walk, trace routing data centric, hierarchical, location-based, energy efficient routing Querying - data collection and processing, collaborative information processing and group connectivity. Distributed Computation - Detection, estimation, and classification problems - Energy-efficient distributed algorithms
UNIT V SENSOR NETWORK PLATFORMS & TOOLS
10 hrs.
Sensor node hardware, programming challenges, node level software platforms, node level simulators, programming beyond individual nodes. Security - Privacy issues - Attacks and countermeasures.
REFERENCE BOOKS:
1. Feng Zhaoand, Leonidas J Guibas, Wireless Sensor Networks Morgan Kaufmann Publishers and imprint of Elsevier, 2004 2. Raghavendra.C.S, Krishna M. Sivalingam, Taieb F. Znati, Wireless Sensor Networks, 2nd edition, Springer, 2004 3. Holger Karl, Andreas Willig, Protocols and Architectures for Wireless Sensor Networks, John Wiley and Sons, 2005


REGULATIONS 2010
SECX5080
HIGH PERFORMANCE NETWORKS (Common to Appl. Elec., CSE, E&C)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I HIGH SPEED LAN
10 hrs.
Fast Ethernet technology, FDDI, SONET and SDH standards, performance of high speed LAN Throughput, delay and reliability, wavelength division multiplexed LAN Routing and switching in WDM networks, Gigabit LAN
UNIT II ISDN
10 hrs.
Overview of ISDN user interface, architecture and standards, packet switched call over ISDN,B and D channels, Link access procedure (LAPD),ISDN layered architecture, signaling, limitations of Narrow band ISDN(N-ISDN) and evolution of Broadband ISDN(B- ISDN)
UNIT III ASYNCHRONOUS TRANSFER MODE NETWORKS
10 hrs.
TM protocol architecture, ATM adaption layer, fast packet switching techniques and VP/VC encapsulation, source characteristics.
UNIT IV ATM TRAFFIC MANAGEMENT
10 hrs.
Traffic management issues in ATM- resource management, connection management, policing and reactive control principles, discrete time queue analysis and application to CAC, leaky bucket and ECN/ICN.
UNIT V ATM SIGNALING AND DATA COMMUNICATION OVER ATM
10 hrs.
ATM signaling fundamentals and Meta signaling, TCP/IP over ATM, challenges and proposals, LAN emulation over ATM, performance of data communication over ATM.
REFERENCE BOOKS:
1. 2. 3. 4. Onvural.R.O., Asyncronous Transfer Mode Networks Performance Issues, 2nd Edition, Artech House Stallings.W, High Speed Networks, TCP/IP and ATM Design Principles, PHI Craig Partridge, Gigabit Networking, Addison Wesley Stallings, ISDNB ISDN with Frame Relay and ATM, 4th Edition, PHI


REGULATIONS 2010
SECX5081
APPLIED CRYPTOGRAPHY AND DATA SECURITY
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I CONCEPTS AND PROTOCOLS
10 hrs.
Terminology Steganography Substitutional ciphers- Ceaser, Mono alphabetic, poly alphabetic, Hill , Vigenere, Playfair Transposition ciphers- rail fence, One time pad Protocols-Key exchange, authentication, secret splitting, Secret sharing, Time stamping services, subliminal channel, Digital signature, proxy signature, group signature, bit commitment, Fair coin flips
UNIT II CRYPTOGRAPHIC ALGORITHMS
10 hrs.
Algorithm types and modes- Over view of symmetric key cryptography- Data Encryption Standard (DES)- IDEA RC4-RC5-Blow fish-AES
UNIT III ASYMMETRIC / PUBLIC KEY ENCRYPTION
10 hrs.
Number theory-Prime numbers-Fermats and Eulers theorem Testing for primality -The Chinese remainder theorem- Discrete logarithms, Public key crypto systems- requirements applications The RSA algorithm- Key management Diffe Hellman key exchange- Elliptic curve cryptography.
UNIT IV HASH FUNCTIONS AND DIGITAL SIGNATURE
10 hrs.
Message authentication- requirements functions codes Hash functions, Hash algorithms- MD5 message digest algorithm Secure Hash algorithm HMAC, Digital signature- Digital Signature Standard DSS Approach Digital Signature algorithm
UNIT V DATA SECURITY
10 hrs.
Internet security protocols- basic concepts Secure socket layer(SSL)- transport layer security(TLS) Secure HTTP Time Stamping protocol Secure electronic transaction (SET)- SSL Versus SET- Email security WAP Security- Security in GSM Security in 3G - Bio metric authentication Kerberos- Single sign on (SSO) approaches.
REFERENCE BOOKS:
1. 2. 3. 4. Bruce Schneier, Applied Cryptography, 2nd Edition, John Wiley & Sons Atul Kahate, Cryptography and Network Security, 2nd Edition, Tata McGraw Hill, 2009 William Stallings, Cryptography and Network Security, 3rd Edition, Pearson Education, 2003 Douglas R Stinson, Cryptography Theory and Practice, CRC press

Max. Marks : 80 PART A : 6 Questions of 5 marks each without choice (30% Problems & 70% Theory) PART B : 2 Questions from each unit of internal choice, each carrying 10 marks

REGULATIONS 2010
SECX5082
RELIABILITY ENGINEERING FOR ELECTRONICS
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I PROBABILITY PLOTTING AND LOAD-STRENGTH INTERFERENCE
10 hrs.
Statistical distribution, statistical confidence and hypothesis testing, probability plotting techniques Weibull, extreme value, hazard, binomial data; Analysis of load strength interference, Safety margin and loading roughness on reliability.
UNIT II RELIABILITY PREDICTION, MODELLING AND DESIGN
10 hrs.
Statistical design of experiments and analysis of variance Taguchi method, Reliability prediction, Reliability modeling, Block diagram and Fault tree Analysis, petric Nets, State space Analysis, Monte carlo simulation, Design analysis methods quality function deployment, load strength analysis, failure modes, effects and criticality analysis.
UNIT III ELECTRONICS AND SOFTWARE SYSTEMS RELIABILITY
10 hrs.
Reliablity of electronic components, component types and failure mechanisms, Electronic system reliability prediction, Reliability in electronic system design, software errors, software structure and modularity, fault tolerance, software reliability, prediction and measurement, hardware/software interfaces.
UNIT IV RELIABILITY TESTING AND ANALYSIS
10 hrs.
Test environments, testing for reliability and durability, failure reporting, Pareto analysis, Accelerated test data analysis, CUSUM charts, Exploratory data analysis and proportional hazards modeling, reliability demonstration, reliability growth monitoring.
UNIT V MANUFACTURE AND RELIABILITY MANAGEMENT
10 hrs.
Control of production variability, Acceptance sampling, Quality control and stress screening, Production failure reporting; preventive maintenance strategy, Maintenance schedules, Design for maintainability, Integrated reliability programmes, reliability and costs, standard for reliability, quality and safety, specifying reliability, organization for reliability.
REFERENCE BOOKS:
1. Patrick D.T. OConnor, David Newton and Richard Bromley, Practical Reliability Engineering, 4th edition, John Wiley & Sons, 2002 2. David J. Klinger, Yoshinao Nakada and Maria A. Menendez, Von Nostrand Reinhold, AT & T Reliability Manual, 5th Edition, New York, 1998 3. Gregg K. Hobbs, Accelerated Reliability Engineering - HALT and HASS, John Wiley & Sons, New York, 2000 4. Lewis, Introduction to Reliability Engineering, 2nd Edition, Wiley International, 1996


REGULATIONS 2010
SECX5067
LOW POWER CMOS DESIGN
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I
10 hrs.
Introduction- Need for Low power VLSI design Charging and Discharging Capacitance- Short circuit current in CMOS CMOS leakage current- Static current- Principles of Low power design- Low power figure of Merits.
UNIT II
10 hrs.
Simulation power analysis- SPICE circuit analysis- Discrete Transistor Modeling and analysis - Gate level Logic simulation - Basics of Gate level Analysis- Capacitive Power Dissipation Internal switching Energy Static state power- Gate level Capacitance Estimation Gate level Power Analysis.
UNIT III
10 hrs.
Architecture level analysis Power model based on Activities and Component Operations - Data Correlation analysis in DSP systems - Monte Carlo Simulation Probabilistic Power Analysis - Random Logic signals- Probability and Frequency-Probability Power analysis techniques- Transition Density Signal Model Gate level Power Analysis using Transition Density - Signal entropy- Power estimation using Entropy.
UNIT IV
10 hrs.
Transistor and gate sizing-Equivalent Pin Ordering -Network Restructuring and Reorganization- special latches and Flip-flops-Self gating Flip flops Combinational Flip flop Double Edge Triggered Flip flop - Low power digital cell library Adjustable Device Threshold Voltage Gate Reorganization- Signal Gating Logic Encoding -Binary versus Gray code Counting Bus invert Encoding - -State Machine encoding- Precomputation Logic.
UNIT V
10 hrs.
Special Techniques- Power reduction in clock networks- Clock Gating Reduced Swing Clock- Oscillator circuit for Clock Generation Other clock power reduction techniques - CMOS floating node Tristate Keeper Circuit Blocking Gate -Low power Bus Low swing bus Charge Recycling bus -Delay Balancing- Low power techniques for SRAM- Memory Bank partitioning Pulsed wordline and Reduced Bitline swing- Design of an FIFO buffer.
REFERENCE BOOKS:
1. 2. 3. 4. 5. 6. Gary Yeap, Practical Low Power Digital VLSI design, 2009 Sharat Prasad and Kaushik Roy, CMOS Low power VLSI design, John Wiley Publications, 2000 Randall L, Geigar and Allence VLSI Design for Analog and Digital circuits, Mc Graw Hill, 1990 Fabricious.E, Design Introduction to VLSI Design, Mc Graw Hill, 1990 Jan M . Rabaey, Digital Integrated Circuits, Pearson Education, 1998 Pucknell, Basic VLSI Design, Prentice Hall India, 1994


REGULATIONS 2010
SECX5005
EMBEDDED SYSTEM DESIGN (Common to Appl. Elec., Embedded, VLSI, E&C, Power)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION
10 hrs.
Embedded system- characteristics of embedded system- categories of embedded system- requirements of embedded systems- challenges and design issues of embedded system- trends in embedded system- system integration- hardware and software partition- applications of embedded system- control system and industrial automationbiomedical-data communication system-network information appliances- IVR systems- GPS systems.
UNIT II DEVELOPMENT OF SOFTWARE ARCHITECTURE
10 hrs.
Development of software architecture simple round robin architecture- design and implementation of digital multimeter- round robin with interrupt architecture- implementation of communication bridge- function queue scheduling architecture- RTOS architectur.
UNIT III HARDWARE ARCHITECTURE
10 hrs.
Hardware architecture- block schematic of a typical hardware architecture- CPU-memeory-I/O Devices- design with microprocesors development-ADC- DAC interfacing LED/LCD interfacing. Case study of processor- 16 bit and 32 bit processor-DSP processor.
UNIT IV EMBEDDED SYSTEM PLATFORM AND DEVELOPMENT TOOLS
10 hrs.
Inter process communication- UART-IEEE 1394-IRDA-USB-PCI development tools- EPROM ERASER-signature validator- accelerated design for video accelerator.
UNIT V OVERVIEW OF DESIGN TECHNOLOGIES
10 hrs.
Design methodologies and tools- designing hardware and software components- system analysis and architecture design- system integration- structural and behavioral description smart cards.
REFERENCE BOOKS:
1. 2. 3. 4. Wayne Wolf, Computers as Components, Morgan Kaufmann publishers , 2nd Edition, 2008 Jean J.Labrosse, Embedded System Building Blocks, CMP, 2nd Edition, 1999 Arnold berger, Embedded System Design, CMP books, 1st Edition, 2001 Narayan and Gong, Specifications and Design of Embedded Systems, Pearson education, 2nd Edition, 1999


REGULATIONS 2010
SECX5013
DSP INTEGRATED CIRCUITS (Common to Appl. Elec., Power, Embedded)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I DSP INTEGRATED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES
10 hrs.
Standard digital signal processors, Application specific ICs for DSP, DSP systems, DSP system design, Integrated circuit design. MOS transistors, MOS logic, VLSI process technologies, Trends in CMOS technologies.
UNIT II DIGITAL SIGNAL PROCESSING
10 hrs.
Digital signal processing, Sampling of analog signals, Selection of sample frequency, Signal-processing systems, Frequency response, Transfer functions, Signal flow graphs, Filter structures, Adaptive DSP algorithms, DFT-The Discrete Fourier Transform, FFT-The Fast Fourier Transform Algorithm, Image coding, Discrete cosine transforms.
UNIT III DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS
10 hrs.
FIR filters, FIR filter structures, FIR chips, IIR filters, Specifications of IIR filters, Mapping of analog transfer functions, Mapping of analog filter structures, Multirate systems, Interpolation with an integer factor L, Sampling rate change with a ratio L/M, Multirate filters. Finite word length effects -Parasitic oscillations, Scaling of signal levels, Round-off noise, Measuring round-off noise, Coefficient sensitivity, Sensitivity and noise.
UNIT IV DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES
10 hrs.
DSP system architectures, Standard DSP architecture, Ideal DSP architectures, Multiprocessors and multicomputers, Systolic and Wave front arrays, Shared memory architectures. Mapping of DSP algorithms onto hardware, Implementation based on complex PEs, Shared memory architecture with Bit serial PEs.
UNIT V ARITHMETIC UNITS AND INTEGRATED CIRCUIT DESIGN
10 hrs.
Conventional number system, Redundant Number system, Residue Number System. Bit-parallel and Bit-Serial arithmetic, Basic shift accumulator, Reducing the memory size, Complex multipliers, Improved shift-accumulator. Layout of VLSI circuits, FFT processor, DCT processor and Interpolator as case studies.
REFERENCE BOOKS:
1. 2. 3. 4. Lars Wanhammer, DSP Integrated Circuits, Academic Press, New York, 1999 Oppenheim A.V., Discrete-time Signal Processing, Pearson Education, 3 rd Edition, 2009 Emmanuel C. Ifeachor, Barrie W. Jervis, Digital Signal Processing A Practical Approach, Pearson Education, 2nd Edition, 2009 Keshab K.Parhi, VLSI Digital Signal Processing Systems Design and Implementation, John Wiley & Sons, 2nd Edition, 1999


REGULATIONS 2010
SECX5014
EMBEDDED CONTROL SYSTEMS (Common to Appl. Elec., Power, E&C, Embedded)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION
10 hrs.
Controlling the hardware with software Data lines Address lines - Ports Schematic representation Bit masking Programmable peripheral interface Switch input detection 74 LS 244
UNIT II INPUT-OUTPUT DEVICES
10 hrs.
Keyboard basics Keyboard scanning algorithm Multiplexed LED displays Character LCD modules LCD module display Configuration Time-of-day clock Timer manager - Interrupts - Interrupt service routines IRQ - ISR - Interrupt vector or dispatch table multiple-point - Interrupt-driven pulse width modulation.
UNIT III D/A AND A/D CONVERSION
10 hrs.
R 2R ladder - Resistor network analysis - Port offsets - Triangle waves analog vs. digital values - ADC0809 Auto port detect - Recording and playing back voice - Capturing analog information in the timer interrupt service routine - Automatic, multiple channel analog to digital data acquisition.
UNIT IV ASYNCHRONOUS SERIAL COMMUNICATION
10 hrs.
Asynchronous serial communication RS-232 RS-485 Sending and receiving data Serial ports on PC Low-level PC serial I/O module - Buffered serial I/O.
UNIT V CASE STUDIES: EMBEDDED C PROGRAMMING
10 hrs.
Multiple closure problems Basic outputs with PPI Controlling motors Bi-directional control of motors H bridge Telephonic systems Stepper control Inventory control systems.
REFERENCE BOOKS:
1. 2. 3. 4. Jean J. Labrosse, Embedded Systems Building Blocks: Complete and Ready-To-Use Modules in C, CMP, 2nd Edition, 2009 Ball S.R., Embedded microprocessor Systems Real World Design, Prentice Hall, 2nd Edition, 1996 Herma K, Real Time Systems Design for distributed Embedded Applications, Kluwer Academic, 1st Edition, 1997 Daniel W. Lewis, Fundamentals of Embedded Software where C and Assembly meet, PHI, 2nd Edition, 2002


REGULATIONS 2010
SECX5031
ELECTROMAGNETIC INTERFERENCE & COMPATIBILITY (Common to Appl. Elec., E&C, VLSI, Embedded)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I EMI ENVIRONMENT
10 hrs.
Introduction to EMI/EMC-Basics of electro Magnetic interference (EMI) Fundamentals of electromagnetic compatibility (EMC)-Radiation hazards Transients and other EMI sources Transients Electrostatics discharge (ESD)-Tempest- Lightning
UNIT II EMI COUPLING
10 hrs.
EMI from apparatus and circuits: Introduction-Electromagnetic emission-Appliances-noise from relays and switches-nonlinearities in circuits-Passive inter modulation-Cross talk in transmission lines-Transmission in power supply lines-Electromagnetic interference.
UNIT III EMI SPECIFICATION/STANDARDS AND MEASUREMENTS
10 hrs.
Units of specification - civilian standards and military standards. Basics of EMI measurements-EMI measurement tools-TEM cell-measurement using TEM cell-Reverberating chamber-GTEM cell-Anechoic chamber-Open area test site-RF absorbers-conducted interference measurements-conducted EMI from equipments-Experimental setup for measuring conducted EMI-Measurement of DM interferences.
UNIT IV EMI CONTROL TECHNIQUE

Shielding technique-Filter techniques-Grounding components-Isolation transformer-Transient suppressor techniques-Bonding techniques-Cable
10 hrs.
connectors and
UNIT V EMC DESIGN OF PCB
10 hrs.
Designing for EMC:Introduction-Different techniques involved in designing for EMC-EMC guide lines for PCB designs-EMC design guide line for audio and control circuit design-EMC guide lines for RF design-EMC guidelines for power supply design-Mother board designs and propagation delay performance models
REFERENCE BOOKS:
1. 2. 3. 4. 5. 6. Bernhard Keiser, Principles of Electromagnetic Compatibility, Artech House, 3rd Edition 1987 Henry W.Ott, Noise Reduction Techniques in Electronics Systems, John Wiley and Sons. New York, 1976 DonWhite, Consultant incorporate-Handbook of EMI/EMC, Vol 1, 1985 Clayton R. Pau, Introduction to EMC, Wiley & Sons, 2006 Sathyamurthy.S, Basics of Electro Magnetic Compatibility, Society of EMC Engineerirs (India), 2003 Kodali.V.P., Engineering EMC Principles, Measurements and Technologies, IEEE Press, 2001


REGULATIONS 2010
SECX5004
REAL TIME OPERATING SYSTEMS (Common to Appl. Elec., Embedded)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I REVIEW OF OPERATING SYSTEMS
10 hrs.
Basic Principles - system calls - Files - Processes - Design and implementation of processes - Communication between processes - operating system structures.
UNIT II DISTRIBUTED OPERATING SYSTEMS

Topology-Network Types-Communication-RPC-Client server model-Distributed file systems
10 hrs.
UNIT III REAL TIME MODELS AND LANGUAGES
10 hrs.
Event based Process based - Graph models - Pettrinet models - RTOS tasks - RT scheduling - Interrupt processing-Synchronization - Control blocks-Memory requirements.
UNIT IV REAL TIME KERNEL
10 hrs.
Principles - Polled loop systems - RTOS porting to a target - Comparison and Study of RTOS - VxWorks and mCoS, Introduction to POSIX and OSEK standards
UNIT V RTOS AND APPLICATION DOMAINS
10 hrs.
RTOS for image processing - Embedded RTOS for voice over IP-RTOS for fault tolerant applications - RTOS for control systems
REFERENCE BOOKS:
1. 2. 3. 4. 5. Hermann K, Real time systems-design principles for distributed embedded Applications, kluwer academic, 1995 Charles Crowley, Operating systems - A design oriented approach, McGraw Hill Raj Buhr, Beily.D.L., An introduction to real time systems, PHI, 1999 Krishna.C.M.,Kang G. Shin, Real time Systems, Mc Graw Hill, 1997 Raymond J.A., Donald L Baily, An introduction to real time operating systems, PHI, 1999


REGULATIONS 2010
SICX5010
ADVANCED DIGITAL CONTROL SYSTEMS (Common to Appl. Elec., E&C)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I PRINCIPLES OF CONTROLLERS
10 hrs.
Review of frequency and time response analysis - specification of control system - need for controller - continuous time compensation - continuous time PI, PD, PID controllers, Digital PID Controllers
UNIT II SIGNAL PROCESSING IN DIGITAL CONTROL
10 hrs.
Sampling and holding Sample and hold devices D/A and A/D conversion Reconstruction Z transform Inverse Z transform Properties Pulse transfer function and state variable approach Review of controllability and observability.
UNIT III DESIGN USING TRANSFORM AND STATE SPACE TECHNIQUES
10 hrs.
Methods of discretisation Comparison Direct design Frequency response methods State space design Pole assignment Optimal control State estimation in the presence of noise Effect of delays.
UNIT IV COMPUTER BASED CONTROL
10 hrs.
Selection of processors Mechanization of control algorithms PID control laws predictor merits and demerits Application to temperature control Control of electric drives Data communication for control.
UNIT V QUANTIZATION EFFECTS AND SAMPLE RATE SELECTION
10 hrs.
Analysis of round off error Parameter round off Limit cycles and dither Sampling theorem limit Time response and smoothness Sensitivity to parameter variations Measurement noise and anti aliasing filter Multirate sampling.
REFFERENCE BOOKS:
1. Gopal.M., Digital control Engineering, Wiley Eastern Ltd., 1989 2 Franklin.G.F., David Powell.J., Michael Workman, Digital control of Dynamic Systems, 3rd Edition, Addison Wesley, 2000 3. Paul Katz, Digital control using Microprocessors, Prentice Hall International, 1982 4. Forsytheand.W., Goodall.R.N., Digital Control, McMillan,1991 5. Chesmond, Wilson, Lepla, Advanced Control System Technology, Viva low price edition, 1998


REGULATIONS 2010
SICX5015
ADVANCED ROBOTICS AND AUTOMATION (Common to Appl. Elec., Embedded, E&C)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION
10 hrs.
Geometric configuration of robots - manipulators - drive systems - internal and external sensors - end effectors control systems - robot programming languages and applications - Introduction to robotic vision.
UNIT II ROBOT ARM KINEMATICS
10 hrs.
Direct and Inverse Kinematics - rotation matrices - composite rotation matrices - Euler angle representation homogeneous transformation - Denavit Hattenberg representation and various arm configurations.
UNIT III ROBOT ARM DYNAMICS
10 hrs.
Lagrange - Euler formulation, joint velocities - kinetic energy - potential energy and motion equations - generalized DAlembert equations of motion.
UNIT IV ROBOT APPLICATONS

Material Transfer & Machine Loading / Unloading General Consideration in robot material handling transfer applications Machine loading and unloading. Processing Operations Spot welding Continuous arc welding - spray coating other processing operations using robots.
10 hrs.
UNIT V ASSEMBLY AND INSPECTION
10 hrs.
Assembly and robotic assembly automation Parts presentation methods assembly operation Compliance and the Remote Center Compliance(RCC) device Assembly system Configurations Adaptable, Programmable assembly system Designing for robotic assembly Inspection automation.
REFFERENCE BOOKS:
1. 2. 3. 4. 5. Fu, Gonazlez.K.S., R.C. and Lee, C.S.G., Robotics (Control, Sensing, Vision and Intelligence), McGraw Hill, 1968 Wesley.E, Snyder.R, Industrial Robots, Computer Interfacing and Control, Prentice Hall International Edition, 1988 Asada and Slotine, Robot analysis and Control, John Wiley and sons, 1986 Philippe Coiffet, Robot technology - Vol.II (Modelling and Control), Prentice Hall Inc., 1983 Groover.M.P., Mitchell, Weiss, Industrial Robotics Technology Programming and Applications, Tata McGraw Hill, 1986


REGULATIONS 2010
SCSX5020
GRID COMPUTING (Common to Appl. Elec., IT, CSE)
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I INTRODUCTION
10 hrs.
High Performance Computing- Cluster Computing-Grid Computing- Grid Computing Models- Types of Grids An overview of Grid Business Areas- Grid Applications Grid Protocols
UNIT II GRID COMPUTING SYSTEMS AND ARCHITECTURES
10 hrs.
Grid architecture Grid architecture and relationship to other Distributed Technologies Concept of virtual organizations- Grid Computing road map
UNIT III THE NEW GENERATION OF GRID COMPUTING APPLICATIONS

Merging the Grid services Architecture with the Web Services Architecture
10 hrs.
UNIT IV OPEN GRID SERVICES

Architecture: OGSA Sample use cases OGSA platform components - OGSA Basic Services Infrastructure: Technical details of OSGI- OGSI/OGSA service elements and layered model
10 hrs.
UNIT V GRID COMPUTING TOOL KITS
10 hrs.
Globus Toolkit Architecture, Programming model, High level services OGSI .Net middleware Solutions
REFERENCE BOOKS:
1. 2. 3. 4. 5. 6. Joshy Joseph & Craig Fellenstein, Grid Computing, PHI, PTR-2003 Ahmar Abbas, Grid Computing: A Practical Guide to technology and Applications, Charles River media 2003 Ian Foster, Carl Kesselman, The Grid2: Blueprint for a New Computing Infrastructure, New Delhi, 2004 Fran Bermn, Geoffrey Fox, Anthony Hey J.G., Grid Computing: Making the Global Infrastructure a Reality, Wiley & sons. 2000 Maozhen Li, Mark Baker, The Grid: Core Technologies, John Wiley & Sons, 2005 www.globus.org and glite.web.cern.ch


REGULATIONS 2010
SPHX1003
CONDENSED MATTER PHYSICS
L 3
T 0
P 0
Credits 3
Total Marks 100
UNIT I
10 hrs.
Crystal binding: Force between atoms-cohesive energy-calculation of cohesive energy bonding in solids-iconic, covalent, metallic, molecular-hydrogen bonded crystals-binding energy of ionic crystals-Madelung constant-Born Heber Cycle.
UNIT II
10 hrs.
Lattice dynamics: Reciprocal space: Brolliouin Zones-vibration modes of mono of mono and diatomic lattices-quantization of lattice vibration-phonon momentum-scattering of neurons by phonons-neutron diffraction.
UNIT III
10 hrs.
Condensed matter under High pressure :Elastic constants Measurements Mechanical properties Tension and compression Fatigue creep-Hydrostatic extrution, material synthesis super hard materials Diamond oxides and other compounds Water jet.
UNIT IV
10 hrs.
Optical Properties: Index of refraction-damping constant characteristic penetration depth-absorbance-reflectivity and transmissivity-point defect-color centers-luminescence-exciton-polaron-interband-intra band transitions-dispersion relation.
UNIT V
10 hrs.
Atomic molecular structure: Central field approximation-Thomas Fermi model and its application-Hartree and Hartree Fock equations hydrogen molecules-Heitler London model-LCAO-Hybridization.
REFERENCE BOOKS:
1. 2. 3. 4. Kittel.C, Introduction to solid stae physics, 7th, Edition, Wiley Eastern, 1996 Chandra.A.K., Quantum Chemistry, Prentice Hall, 1990 Hummel.R.E., Electronic properties of materials, Narosa, 1993 Raimes.S, The wave mechanics of electrons in metals, North Holland, 1967


REGULATIONS 2010

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SATHYABAMA UNIVERSITY

SYLLABUS MASTER OF ENGINEERING PROGRAMME IN APPLIED ELECTRONICS (4 SEMESTERS) REGULATIONS 2010

FACULTY OF ELECTRONICS ENGINEERING

SATHYABAMA UNIVERSITY REGULATIONS 2010

M.E (APPLIED ELECTRONICS)

FACULTY OF ELECTRONICS ENGINEERING

RANGE OF MARKS FOR GRADES

CUMULATIVE GRADE POINT AVERAGE CALCULATION

where Ci - Credits for the subject

i - Sum of all subjects successfully cleared during all the semesters

FACULTY OF ELECTRONICS ENGINEERING

Final Degree is awarded based on the following :

M.E (APPLIED ELECTRONICS)

FACULTY OF ELECTRONICS ENGINEERING

M.E. - APPLIED ELECTRONICS REGULATIONS 2010 CURRICULUM SEMESTER I

SUBJECT CODE THEORY SECX5084 SECX5076 SECX5051

FACULTY OF ELECTRONICS ENGINEERING

TOTAL CREDITS: 15 TOTAL CREDITS FOR THE COURSE: 70

LIST OF ELECTIVE SUBJECTS

L - Lecture hours; T - Tutorial hours; P - Practical hours; C - Credits

M.E (APPLIED ELECTRONICS)

FACULTY OF ELECTRONICS ENGINEERING

THEORY OF TRANSFORMS AND PROBABILITIES

Total Marks 100

UNIT I 1-D AND 2-D TRANSFORMS

UNIT II IMAGE TRANSFORMS

UNIT II WAVELET TRANSFORMS

UNIT III PROBABILITY & RANDOM VARIABLES

UNIT V QUEUING THEORY

UNIVERSITY EXAM QUESTION PAPER PATTERN

FACULTY OF ELECTRONICS ENGINEERING

COMPUTER ARCHITECTURE AND PARALLEL PROCESSING

Total Marks 100

UNIT I REVIEW OF COMPUTER ARCHITECTURE

UNIT II PROCESSOR AND MEMORY

UNIT III ARRAY PROCESSORS

UNIT IV MULTIPROCESSOR ARCHITECTURE AND MULTIPROCESSING CONTROL

UNIT V PARALLEL PROGRAM DEVELOPMENT AND ENVIRONMENTS

UNIVERSITY EXAM QUESTION PAPER PATTERN

Exam Duration: 3 hrs. 30 marks 50 marks

FACULTY OF ELECTRONICS ENGINEERING

ADVANCED ANALOG INTEGRATED CIRCUITS

Total Marks 100

UNIT I MODEL FOR INTEGRATED-CIRCUIT ACTIVE DEVICES

UNIT II SINGLE-TRANSISTOR AND MULTIPLE-TRANSISTOR AMPLIFIERS

UNIT III CURRENT MIRRORS, ACTIVE LOADS, AND OPERATIONAL AMPLIFIERS

UNIT IV NONLINEAR ANALOG CIRCUITS AND NOISE IN INTEGRATED CIRCUITS

UNIT V IC FABRICATION TECHNOLOGY

UNIVERSITY EXAM QUESTION PAPER PATTERN

Exam Duration: 3 hrs. 30 marks 50 marks

FACULTY OF ELECTRONICS ENGINEERING

ADVANCED DIGITAL SYSTEM DESIGN (Common to Appl. Elec., Embedded, VLSI)

Total Marks 100

UNIT I SEQUENTIAL LOGIC CIRCUITS

UNIT II SYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN

UNIT III ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN

UNIT IV PROGRAMMABLE LOGIC DEVICES

UNIT V STUDY OF FPGA AND XILINX

UNIVERSITY EXAM QUESTION PAPER PATTERN

FACULTY OF ELECTRONICS ENGINEERING

ADVANCED MICROCONTROLLERS & EMBEDDED SYSTEMS

Total Marks 100