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VLSI-eCAD (VeCAD) Research Laboratory Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai, Johor. Malaysia Tel: +607-5535268 Email: hauyuanwen@gmail.com
Design Flow
RTL (.v) Testbench (.v)
Frontend
ASIC / FPGA Library
Pre-synthesis Simulation
Synthesis
Intermediate Netlist / Post-layout model (.v)
Post-synthesis Simulation
HDL Language
HDL Language (VHDL / Verilog)
Synthesis
Simulation
A HDL code that can be simulated correctly does not mean it is synthesizable!!!
2010 Jasmine Hau Yuan Wen 3
stimulus
monitor
Simulation
Testbench (top-level module) Design Under Test
stimulus
monitor
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Testbench
Simulation software
2010 Jasmine Hau Yuan Wen 5
b) adder4_tb.v
module adder4_tb(); reg [3:0] inputA, inputB; wire [4:0] outputC; integer i; initial begin //a verilog process which only executed once for (i=0; i < 10; i=i+1) begin inputA = i; inputB = i + 5; #10; // wait 10 time unit end // testbench
assign C = A + B; endmodule
end
If you compile your design in Quartus II, you will get following error: Error: Can't synthesize current design -Top partition does not contain any logic
2010 Jasmine Hau Yuan Wen
Project Name, without any space Browse to your working directory, in this example is c:/TB. Make sure dont have any space in the directory path
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You can double-click any .v file to view the file content or correct the syntax error.
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The testbench (adder4_tb) and its DUT (adder4_inst) are loaded into simulator The signals within the testbench module
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Stimulus (reg)
monitor (wire)
end
//a verilog process which only executed once for (i=0; i < 10; i=i+1) begin inputA = i; inputB = i + 5; #10; // wait 10 time unit end
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clock period = 20 ns
If the simulator is suspended due to $stop, you can continue the simulation by: Menu bar: simulate >> run >> continue
rst
op
ALU
C
2010 Jasmine Hau Yuan Wen 27
(b) Testbench
`timescale 10ns/1ns module simple_tb(); reg reg reg reg [3:0] wire [4:0] integer initial begin clk = 1'b0; forever #1 clk = ~clk; end initial begin rst = 1'b1; end initial begin for (i=0; i < 10; i=i+1) begin op = $random; #2; inputA = $random; inputB = $random; //rst signal #2; rst = 0'b0; //clock with period 20 ns clk; rst; op; inputA, inputB; outputC; i; //clk generator
//regA always @ (posedge rst or posedge clk) begin if (rst) reg_A <= 4'b0000; else reg_A <= A; end //regB always @ (posedge rst or posedge clk) begin if (rst) reg_B <= 4'b0000; else reg_B <= B; end //adder/subtractor assign C = op? {2'b00, reg_A[3:1]} : reg_A + reg_B; endmodule
$display(Time %d: A = %d, B = %d, C = %d", $time, inputA, inputB, outputC); end $stop; end simple_design DUT ( .clk (clk), .rst (rst),.op (op),.A (inputA),.B (inputB),.C(outputC)); endmodulle
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Example Output
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(b) Testbench
module adder4_tb(); reg [3:0] inputA, inputB; wire [4:0] outputC; integer i, file1; initial begin file1 = $fopen("file.out"); for (i=0; i < 10; i=i+1) begin inputA = $random; inputB = $random; #10; //open a file
assign C = A + B; endmodule
A B adder4 C
outputC
end
//close a file
endmodule
(b) Testbench
module adder4_tb(); integer i; reg [3:0] inputA, inputB; wire [4:0] outputC; reg [3:0] memA [0:15]; reg[3:0] memB [0:15];
assign C = A + B; endmodule
initial begin $readmemh("memA.vec", memA); $readmemh("memB.vec", memB); end initial begin for (i=0; i < 16; i=i+1) begin inputA = memA[i]; inputB = memB[i]; #10;
// load the value from memA // load the value from memB
$display(%d: inputA = %d inputB = %d outputC = %d", i, inputA, inputB, outputC); end end adder4 adder4_inst ( endmodule .A (inputA), .B (inputB), .C(outputC));
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(d) memB.vec
//Comments are allowed @0 // from address 0 5 // address 0 = 0x5 9 // address 1 = 0x9 C // address 2 = 0xC 3 // address 3 = 0x3 D // address 4 = 0xD @5 // from address 5 6 // address 5 = 0x6 7 // address 6 = 0x7 8 // address 7 = 0x8 9 // address 8 = 0x9 A // address 9 = 0xA @A 8 7 C 8 7 C // from address 10 // address 10 = 0x8 // address 11 = 0x7 // address 12 = 0xC // address 13 = 0x8 // address 14 = 0x7 // address 15 = 0xC
(e) Output
Due to address 10 to address 12 of memA are uninitialized, the outputs are undetermined
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(b) Testbench
module adder4_tb(); reg [3:0] inputA, inputB; wire [4:0] outputC; integer i; initial begin for (i=0; i < 10; i=i+1) begin inputA = $random; inputB = $random; #10; $display("%d: inputA = %d inputB = %d outputC = %d", i, inputA, inputB, outputC); $dumpflush;
assign C = A + B; endmodule
A B adder4 C
outputC
end end initial begin $dumpfile ("adder4.vcd"); $dumpvars(0, adder4_tb); end adder4 adder4_inst ( endmodule .A (inputA), .B (inputB), .C(outputC));
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(b) Testbench
module adder4_tb(); reg [3:0] inputA, inputB; wire [4:0] outputC; integer i; initial begin for (i=0; i < 10; i=i+1) begin inputA = $random; inputB = $random; #10; $display("%d: inputA = %d inputB = %d outputC = %d", i, inputA, inputB, outputC); $dumpflush;
assign C = A + B; endmodule
A B adder4 C
outputC
end end initial begin $dumpfile ("adder4.vcd"); $dumpvars(0, adder4_tb); end adder4 adder4_inst ( endmodule .A (inputA), .B (inputB), .C(outputC));
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