Limitations in Scaling

Shrihari, K.Sudha, Sureka, S.Suvetha , Tharun Yadhav and A.Uthra Abstract: The scaling of CMOS transistors has driven the tremendous growth of the semiconductor industry for the last four decades. However, scaling of CMOS has some limiting conditions. This paper discuss about the limtations in CMOS. Index terms- scaling,subthreshold currents, miniaturization

I.

INTRODUCTION In 1965, Gordon Moore wrote a paper entitled Cramming more Components onto Integrated Circuits where he first proposed that transistor density on chips would grow exponentially . This became known as Moore's law. Remarkably the industry has kept pace with this exponential growth for that last four decades. There is however a problem with exponential growth: it rapidly approaches infinity, while physical systems generally cannot run to infinity. As Moore himself pointed out in 2003, No exponential change of a physical quantity can, however, continue forever. This paper examines briefly what issues are preventing CMOS scaling from approaching infinity. a hard limit that cannot be overcome. That limit is the size of the atom and molecule. Clearly devices cannot be fabricated smaller than the dimension of a single molecule and some dimensions will need to be more than a molecule wide. It should also be pointed out here that lithographic equipment costs have also grown exponentially , and this is beginning to limit the profitability of increased scaling. Thus there is a rapidly approaching limit to how small transistors can actually be fabricated When the dimensions of a MOSFET are scaled down, both the voltage level and the gate-oxide thickness must also be reduced . Since the electron thermal voltage, kT/q, is a constant for room-temperature electronics, the ratio between the operating voltage and the thermal voltage inevitably shrinks. This leads to higher source to- drain leakage currents stemming from the thermal diffusion of electrons. At the same time, the gate oxide has been scaled to a thickness of only a few atomic layers ,where quantummechanical tunneling gives rise to a sharp increase in gate leakage currents [3]. The effects of these fundamental factors on CMOS scaling are quantified below. Power supply and threshold voltage shows the scaling trend of power-supply voltage (Vdd), threshold voltage (Vt), and gate-oxide thickness (tox) as a function of CMOS channel length [2]. It is seen that the power-supply voltage has not been decreasing at a rate proportional to the channel length. This means that

II.

LIMITING FACTORS IN CMOS Since the 1970's people have been predicting the end of CMOS . Despite these predictions, the monetary benefit of growth has driven massive research, which has overcome all previous barriers . However, many experts are now claiming that the industry is reaching limits that no amount of research can push past. There are three key factors limiting continued scaling in CMOS: 1. Minimum dimensions that can be fabricated 2. Diminishing returns in switching performance 3. Off-state leakage So far the primary limitations to chip scaling have been lithographic issues. Simply, how small can a transistor can be fabricated? However, transistor dimensions are approaching

the field has been gradually rising over the generations between 1-_m and 0.1-_m channel lengths. Fortunately, thinner oxides are more reliable at high fields, thus allowing operation at the reduced but nonscaled supply voltages. Below 0.1 _m, threshold voltage deviates even further from the past scaling behavior, as depicted in Figure 1. MOSFET threshold voltage is defined as the gate voltage at which significant current begins to flow from the source to the drain . Below the threshold voltage, the current does not drop immediately to zero. Rather, it decreases exponentially, with a slope on the logarithmic scale inversely proportional to the thermal energy kT. This is because some of the thermally distributed electrons at the source of the transistor have high enough energy to overcome the potential barrier controlled by the gate voltage and flow to the drain (Figure 2 inset). Such a subthreshold behavior follows directly from fundamental thermodynamics and is independent of powersupply voltage and channel length. The standby power of a CMOS chip due to source-todrain subthreshold leakage is given [4] by Poff _ WtotVdd Ioff _ WtotVdd I0 exp__ qVt mkT_ , (1) where Wtot is the total turned-off device width with Vdd across the source and drain, Ioff is the average off-current per device width at 100_C (worst-case temperature), I0 is the extrapolated current per width at threshold voltage

(of the order of 110 _A/_m for 0.1-_m devices), m is a dimensionless ideality factor typically _1.2 (to be discussed later), and Vt is the threshold voltage at 100_C. Even if Vt is kept constant, the leakage current of turnedoff devices will increase in proportion to 1/tox and (Wtot/L) because the current at threshold condition I0 is proportional to the inversion charge density at threshold, Qi _ (12)(kT/q)Cox [4], where Cox _ _ox/tox is the gateoxide capacitance per unit area. The off-state leakage current would further increase by about ten times for every 0.1-V reduction of Vt. For a chip with an integration level of 100 million transistors, the average leakage current of turned-off devices should not exceed a few times 10_8 A. This constraint holds the threshold voltage to a minimum of about _0.2 V at the operating temperature (100_C worst case). The saturation of threshold voltage leads to a saturation of the power-supply voltage as well, at a minimum value of about _1.0 V, as shown in Figure 1. This is because CMOS performance, measured by the largesignal transconductance Ion/Vdd (slope of the dotted lines in Figure 2), degrades rapidly with an increasing ratio of Vt/Vdd. For high-performance CMOS, a Vt/Vdd ratio of _0.3 is desired [4]. A nonscaled Vdd means more aggressive device designs at higher electric fields. More significantly, it drives up the active power of a CMOS chip (crossover currents are usually negligible), given by

Pac _ CswVdd 2 f, (2) where Csw is the total node capacitance being charged and discharged in a clock cycle, and f is the clock frequency. As CMOS technology advances, clock frequency goes up. The total switching capacitance is likely to increase as well, as one tries to integrate more circuits into the same or an even larger chip area. The active power of todays high-end microprocessors is already in the 50 100-W range. Barring a major breakthrough in powermanagement systems via architectural innovation, expensive packaging solutions will very soon be required in order to dissipate the heat generated by the chip. There are other schemes for meeting leakage power requirements. For example, one can fabricate multiplethresholdvoltage devices on a chip [5]. Low-threshold devices could be used in critical logic paths for speed, while high-threshold devices would be used everywhere else, including memory arrays, for low standby power. One can also sense the circuit activity and cut off the power supply to logic blocks that are not switchingan approach known as sleep mode. Other possibilities include dynamicthreshold devices, for which the threshold voltage is controlled by a back-gate bias voltage in either bulk or silicon-on-insulator device structures. Yet another option is low-temperature CMOS. Low-temperature operation not only steepens the subthreshold slope and improves mobility (Section 4), but also reduces wire resistance.

However, all of these solutions generally carry a cost in density and complexity. Gate-oxide tunneling To keep adverse 2D electrostatic effects on threshold voltage (i.e., short-channel effects) under control (discussed in more detail in Section 3), gateoxide thickness is reduced nearly in proportion to channel length, as shown in Figure 1. This is necessary in order for the gate to retain more control over the channel than the drain. For CMOS devices with channel lengths of 100 nm or less, an oxide thickness of _3 nm is needed. This thickness comprises only a few layers of atoms and is approaching fundamental limits. While it is amazing that SiO2 can carry us this far without being limited by extrinsic factors such as defect density, surface roughness, or large-scale thickness and uniformity control, oxide films this thin are subject to quantum-mechanical tunneling, giving rise to a gate leakage current that increases exponentially as the oxide thickness is scaled down. Tunneling currents for oxide thicknesses ranging from 3.6 to 1.0 nm are plotted versus gate voltage in Figure 3 [3]. In the direct-tunneling regime, the current is rather Figure 3 Measured and calculated oxide tunneling currents vs. gate voltage for different oxide thicknesses. Labels on the right, from the bottom up, mark the order of magnitude of offcurrents at room and worst-case temperatures, source-to-drain current at Vg _ Vt

(Vds _ Vdd ), and on-current at Vg _ Vds _ V dd. The inset shows the

band diagram for tunneling in a turned-on nMOSFET.