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Design and Characterization of Parallel Prefix Adders using FPGAs AIM: The main aim of the project is to design

Design and Characterization of Parallel Prefix Adders using FPGAs. AB !"AC!: Parallel-prefix adders (also known as carry tree adders) are known to have the best performance in VL ! designs" #owever$ this performance advantage does not translate directly into %P&' implementations d(e to constraints on logic block config(rations and ro(ting overhead" This paper investigates three types of carrytree adders (the )ogge- tone$ sparse )ogge- tone$ and spanning tree adder) and compares them to the simple *ipple +arry 'dder (*+') and +arry kip 'dder (+ ')" These designs of varied bit-widths were implemented on a ,ilinx partan -. %P&' and delay meas(rements were made with a high-performance logic analy/er" 0(e to the presence of a fast carry-chain$ the *+' designs exhibit better delay performance (p to 123 bits" The carry-tree adders are expected to have a speed advantage over the *+' as bit widths approach 245"

V.Mallikarjuna (Project manager)

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B#$C% DIAG"AM:

%ig6 panning Tree +arry Look ahead 'dder (15 bit)"

!$$# : ,ilinx 7"2! .$ 8odelsim5"9c" APP#ICA!I$& AD'A&!AG( : The binary adder is the critical element in most digital circ(it designs incl(ding digital signal processors (0 P) and microprocessor data path (nits"
V.Mallikarjuna (Project manager)

ISO: 9001- 2000 CERTIFIED COMPANY


Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

%P&' offers improved performance in terms of speed and power over 0 Pbased and microprocessor-based sol(tions for many practical designs involving mobile 0 P and telecomm(nications applications and a significant red(ction in development time and cost over 'pplication pecific !ntegrated +irc(it (' !+) designs" "(F("(&C( : :" #" ." ;este and 0" #arris$ +8< VL ! 0esign$ 9 th edition$ Pearson= 'ddison-;esley" *" P" >rent and #" T" )(ng$ ?' reg(lar layo(t for parallel adders$@ !... Trans" +omp(t"$ vol" +--1$ pp" 25A-259" 0" #arris$ ?' Taxonomy of Parallel Prefix :etworks$@ in Proc" -Bth 'silomar +onf" ignals ystems and +omp(ters$ pp" 221-=B" P" 8" )ogge and #" " tone$ ?' Parallel 'lgorithm for the .fficient

ol(tion of a &eneral +lass of *ec(rrence .C(ations$@ !... Trans" on +omp(ters$ Vol" +-22$ :o 3" P" :dai$ " L($ 0" omesekhar$ and )" *oy$ ?%ine- &rained *ed(ndancy in 'dders$@ !nt" ymp" on D(ality .lectronic 0esign$ pp" -1B--21"

V.Mallikarjuna (Project manager)

ISO: 9001- 2000 CERTIFIED COMPANY


Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

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