Embedded Hardware Design ECE 225

Dr. Shubhajit Roy Chowdhury, Centre for VLSI and Embedded Systems Technology, IIIT Hyderabad, India Email: src.vlsi@iiit.ac.in
Dr. Shubhajit Roy Chowdhury
CVEST, IIIT HYDERABAD

What is an Embedded System?

Embedded system: any device that includes a programmable computer but is not itself a generalpurpose computer. Take advantage of application characteristics to optimize the design: dont need all the general-purpose bells and whistles.
Dr. Shubhajit Roy Chowdhury
CVEST, IIIT HYDERABAD

Embedded Hardware
output analog analog

CPU

input

embedded computer

mem

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD

Example embedded computing systems

Motorola

Siemens

Apple

BMW

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD

Examples
Personal digital assistant (PDA). Printer. Cell phone. Automobile: engine, brakes, dash, etc. Television. Household appliances. PC keyboard (scans keys).
Dr. Shubhajit Roy Chowdhury
CVEST, IIIT HYDERABAD

Some common characteristics of embedded systems

Single-functioned
Executes a single program, repeatedly

Tightly-constrained
Low cost, low power, small, fast, etc.

Reactive and real-time

Continually reacts to changes in the systems environment Must compute certain results in real-time without delay
Dr. Shubhajit Roy Chowdhury
CVEST, IIIT HYDERABAD

Early history
Late 1940s: MIT Whirlwind computer was designed for real-time operations.
Originally designed to control an aircraft simulator.

First microprocessor was Intel 4004 in early 1970s. HP-35 calculator used several chips to implement a microprocessor in 1972.
Dr. Shubhajit Roy Chowdhury
CVEST, IIIT HYDERABAD

Early history, contd.

Automobiles used microprocessor-based engine controllers starting in 1970s.
Control fuel/air mixture, engine timing, etc. Multiple modes of operation: warm-up, cruise, hill climbing, etc. Provides lower emissions, better fuel efficiency.

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD

 Common metrics

Design challenge optimizing design metrics

Unit cost: the monetary cost of manufacturing each copy of
the system, excluding NRE cost

NRE cost (Non-Recurring Engineering cost):

The one-time monetary cost of designing the system

Size: the physical space required by the system Performance: the execution time or throughput of the
system

Power: the amount of power consumed by the system Flexibility: the ability to change the functionality of the
system without incurring heavy NRE cost
Dr. Shubhajit Roy Chowdhury
CVEST, IIIT HYDERABAD

Design challenge optimizing design metrics

Common metrics (continued)
Time-to-prototype: the time needed to build a working
version of the system

Time-to-market: the time required to develop a system to

the point that it can be released and sold to customers

Maintainability: the ability to modify the system after its

initial release

Correctness, safety, many more

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD

Time-to-market: a demanding design metric

Time required to develop a product to the point it can be sold to customers Market window Period during which the product would have highest sales Average time-to-market constraint is about 8 months Delays can be costly
CVEST, IIIT HYDERABAD

Revenues ($)

Time (months)

Dr. Shubhajit Roy Chowdhury

Losses due to delayed market entry

Peak revenue

Revenues ($)

Peak revenue from delayed entry On-time Market rise Delayed Market fall

W Time

2W

On-time entry

Delayed entry

Simplified revenue model Product life = 2W, peak at W Time of market entry defines a triangle, representing market penetration Triangle area equals revenue Loss The difference between the on-time and delayed triangle areas
CVEST, IIIT HYDERABAD

Dr. Shubhajit Roy Chowdhury

Processors
How much should be the processor?
Flexibility Performance Cost

Hardware software Co-design

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD

Processors
Design Choices: General Purpose Vs ASIPs Vs ASICs
Datapath: Circuitry for transforming data and storing intermediate results ALU, Muxes and Registers Size of processor -- bit width of data path Pipelined and non-pipelined datapaths Controller: Circuitry to perform fetch, decode, execute automaton Microprogram controlled and hardwire controlled

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD

General Purpose Processors

Control

Reg. file

IR

PC

Gen. ALU

Program Memory
Total=0; for I=1 to n loop total+= M[I]; end loop

Data Memory

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD

Application Specific Instruction Set Processors

Control

Reg. file Custom. ALU

IR

PC

Program Memory
Total=0; for I=1 to n loop total+= M[I]; end loop

Data Memory

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD

Single Purpose Processors (ASICs)

Datapath Control State reg. + index total

Data Memory

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD

Choice of IC: Custom and Semi custom ICs

An IC consists of number of layers Transistors - gates - connection of gates masking - depositing photo sensitive material on chip surface Set of masks --> Layout Feature size - narrowest line we can create on a chip , presently submicron Full custom ICs -all layers optimized for performance high NRE cost

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD

Semi-custom ICs
In a semi-custom ASIC the lower layers are fully or partially built leaving us to finish the upper layers. Gate array: Masks for the array of gates and the transistors are already built - remaining task is to establish interconnection to achieve the implementation. Standard cell technology: Logic level cells, such as AND gate or (AND-OR-NOT) combinations have masks pre-designed. Remaining task - Arrange these portions into complete masks for the gate level and connect the cells.
Dr. Shubhajit Roy Chowdhury
CVEST, IIIT HYDERABAD

Programmable Logic Devices (PLDs)

All layers already exist - layers implement a programmable circuit (creating/destroying links between gates by fusing links or by setting programmable bits) PLAs: Programmable Logic Arrays programmable array of AND gates + programmable array of OR gates FPGAs: offers more general connectivity among blocks of logic rather than arrays of gates
Xilinx, Actel ; rapid prototyping
Dr. Shubhajit Roy Chowdhury
CVEST, IIIT HYDERABAD

 Trend is to design and simulate on general purpose Implement on Semi custom for reducing time to market window Refine from experience Move to Custom design Also, first map to older tested design (say 0.2 micron) before moving to new technology (say 0.08 micron) - clock speed improves over time
Dr. Shubhajit Roy Chowdhury
CVEST, IIIT HYDERABAD

Some issues in Processor Design for Embedded Systems

ASICs Op/Watt DSPs and ASIPs

Processors

Technology
Dr. Shubhajit Roy Chowdhury
CVEST, IIIT HYDERABAD

Power and Energy

Both P and E are important P affects size of power supply, voltage regulators, cooling E affects battery life
Dependent on code efficiency Memory issues

E = Pdt

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD

Dynamic Power Management

Processor

Power Supply

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD

Run (400mW) 90musec 10musec Dormant(50 mW) 10musec 160 musec Resting (160 mu W) 90 musec

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD

Clock network power model

Clock is a major power sink in modern designs. Major elements of the clock power model:
Global clock lines. Global drivers. Loads on the clock network.

Must handle gated clocks.

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD

Books
Embedded System Design: A unified hardware / software introduction, Frank Vahid and Tony Givargis (Wiley) Embedded Systems, Raj Kamal Computers as Components, Wayne Wolf VHDL Primer, J. Bhasker FPGA based System Design, Wayne Wolf Advanced Digital System Design using VHDL, Charles H. Roth

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD

Evaluation Weightages
Mid Semester Examination 1: 10% Mid Semester Examination 2: 15% End Semester Examination: 20% Assignments: 10% Surprise Test / Quiz: 5% Practical: 30% Project: 10%
Dr. Shubhajit Roy Chowdhury
CVEST, IIIT HYDERABAD

Criteria for Passing

A student shall be declared pass if he/she satisfies ALL the following criteria: A. He/she should score minimum 40% marks in mid semester 1, 2 and end semester examinations taken together B. He/she scores minimum 50% marks in lab C. Scores minimum 50% marks in project D. Scores 50% marks in aggregate E. Submits all the assignments on time Copying of any assignment or part thereof if detected is liable to be marked ZERO.
Dr. Shubhajit Roy Chowdhury
CVEST, IIIT HYDERABAD

Thank you

Dr. Shubhajit Roy Chowdhury

CVEST, IIIT HYDERABAD