FPGA IMPLEMENTATION OF A PHASE LOCKED LOOP BASED ON RANDOM
SAMPLING
Maximiliano 0. Sonnaillon* and Fabian J
Balseiro Institute
Cavitation and Biotechnology Lab
Bariloche Atomic Center, Argentina
Email: msonnaillonging.unrc.edu.ar
ABSTRACT
A Phase Locked Loop (PLL) based on digital signal
processing and random sampling is proposed in this paper.
Field Programmable Gate Array (FPGA) technology is used
to implement a prototype. The random sampling scheme is
used to reduce the sampling frequency requirements
without aliasing effects. The possibility of sampling and
processing at lower frequencies allows the implementation
of complete-digital high-frequency systems, without
limitations imposed by the analog to digital converter and
the signal processing unit. The basic principles are
presented, and the implemented algorithms are described.
Experimental results show the PLL performance.
1. INTRODUCTION
Phase locked loops (PLL) are electronic systems widely
used in different fields of applications. Their main task is
synchronizing an internal oscillator with an external
periodic signal. Typical applications of PLLs are
communications systems, instrumentation and electric
power systems.
At first, PLLs were built with analog electronics, based on
discrete components or integrated circuits (IC), this type of
PLL is also called Analog-PLL or APLL. When digital
elements are used as part of the PLL, they are called
Digital-PLL, or DPLL. These two types of PLLs are used in
most applications.
The increasing computing capacity of microprocessors
digital signal processors (DSPs) and customizable devices
(e.g. field programmable gate array, FPGA, or application
specific integrated circuit, ASIC) makes convenient, for
many applications, the implementation of software based
PLLs, or SPLLs. These PLLs are implemented entirely
based on digital signal processing (DSP).
SPLLs have many advantages with respect to hardware-
*CONICET
tCNEA and CONICET
1-4244-0606-4/07/$20.OO ©)2007 IEEE. 1
Bonettot
based PLLs, such as their immunity to weather conditions,
accuracy, simplicity of fabrication, and their
reconfiguration capability.
SPLLs are only suitable for low-frequency applications
because, at high-frequency, the amount of required
mathematical operations is prohibitive. Also the analog to
digital converter (ADC) restricts the speed of DSP based
systems.
The uniform sampling scheme (i.e. sampling at a constant
frequency) is limited by the well-known Nyquist theorem
[1]. This theorem says that the sampling frequency must be
more than twice the maximum frequency present in the
analog spectrum. If this condition is not satisfied, the
resulting digital spectrum is aliased. Aliasing corrupts the
signal and is not-desired in most DSP applications.
Alternative sampling schemes have been proposed to avoid
the aliasing effects, such as non-uniform periodic sampling
[2] and random sampling [3]. The first allows selecting a
certain spectrum that will be free of alias, but requires
analog filtering to avoid the aliasing of other parts of the
spectrum. Random sampling (RS) removes the aliasing
effects without the necessity of any analog pre-processing.
Using RS, high-frequency analog signals can be digitally
processed at frequencies much lower than the Nyquist
frequency without aliasing effects. However, only particular
digital signal processing tasks (e.g [4]) can be efficiently
implemented using random sampling. As far as the authors
know, RS has not been applied to the signal processing of a
PLL.
In this paper, a SPLL based on RS is proposed and
implemented using FPGA technology. These devices are
suitable for implementing RS based signal processing. The
random period generation can be efficiently implemented
using programmable logic. Furthermore, the high
computing power available in modern FPGAs, makes
possible an efficient implementation of high accuracy
SPLLs.
The implemented PLL has applications in high frequency
instrumentation, such as lock-in amplifiers [4].
Furthermore, the proposed PLL can be suitable for wireless
communication systems [5] (e.g software radio).
2. THEORETICAL BACKGROUND
2.1. PLL basics
A block diagram of a basic PLL is shown in Fig. 1. The
main components are the input signal, the phase detector
(PD), the loop filter F(s), the voltage controlled oscillator
(VCO) and the output signal.
The input signal must be a periodic signal, usually a
sinewave or a square wave. In this paper, only sinewaves
are used as input signals.
The PD compares the input signal with the local signal and
generates a phase error signal. There are different
implementations of PD, such as product-based PDs,
tangent-based PDs, XOR-based PDs, and sequential PDs.
The PD based on a product is the simplest to implement in
a SPLL and has a performance good enough for most
applications.
The PD produces a signal composed by the phase error plus
other non-desired components, such as high frequency
harmonics coming from the non-linear elements (i. e.
multiplication) and random noise. The loop filter (F(s))
must filter-out these components and keep only the phase
error signal. Also, the filter works as a controller in the
closed loop system, which tries to reduce the phase error to
zero.
A filter that efficiently meets these requirements is the
proportional-integral filter (PI) [6]. The PI constants (KP
and KI) determine the PLL characteristics, such as its time
response, its frequency ranges, its noise immunity and the
output signal quality. For more details, consult the
suggested bibliography [6].
The VCO can be implemented accurately in a DSP system.
The~~~ ~
mos aprpit meho use inFPA based
ipe mnta is dire digita synthesi (dDS)
[7], wh
i describedineimplementations syeio n
7
wi.
2.2. Random sampling
The sampling scheme used in this work is called additive
random sampling (ARS) [3][5]. The input signal is sampled
at random instants defined by the following equation:
ti+1=ti+ (1)
where t4 is the ith sampling time and T1 are random periods
defined by:
Ti = (M + 1i ) 3 (2)
2
PD
Reference F(s)
input
Output VCO0
Fig. 1: Basic PLL block diagram.
where S is the minimum time step (time quantization),
which is defined by hardware limitations (the input clock in
the present implementation). The variable r is an integer
random number, with a uniform probability mass function,
given by:
f[r> R+t 0 r.R
O (3)
anyother case
It can be demonstrated [4][5] that the time quantization a
determines the maximum frequency without aliasing. This
frequency is generally much higher than the Nyquist
frequency of the traditional uniform sampling scheme. The
product MS is the minimum sampling period, which
depends on the ADC conversion time and the DSP
computing speed.
This RS scheme has the property of reducing significantly
the aliasing effects if it is properly used. The analytical
demonstration of this fact is beyond the scope of this paper,
the reader can consult the suggested bibliography for
further details [3][4][5].
The RS scheme requires certain modifications in the DSP
operations of a PLL. Since the sampling times are not
equidistantly spaced, each sampling period must be used to
compute the variables that depend on time.
3.1. Random period generation
There are two basics parts in the random period generator
a) random (or pseudo-random) number generation,
b) high speed programmable timer.
Both parts can be implemented efficiently using digital
logic.
The pseudo-random number (PN) generation is a common
task in wireless communications systems, because it iS
required to generate codes in CDMA (code division
multiple access). The architecture of modemn FPGAs allows
an efficient implementation of LFSR (linear feedback shift
registers) [8]. These registers can be used to generate PN as
 0,15 . * 14 . * 13 -0 1215. 14
>+3 .W 0l ~~~~~~~~~~~~~
l l ~ ~~~~e1
~piin(t(i)6)
where in(ti) is the analog input signal sampled at instant ti.

Fig. 2: Logic diagram of a 16bit pseudo-random number 3.4. PI filter

generator. The other operation that must take into account the
is shown in Fig. 2. An adequate feedback assures a sampling periods is the integrator of the PI filter. The
sequence with* **
maximum * * (2
period z n, where
*. n is the word. expression used to compute the integral term iS:
size) [9].
I, = II_, + KI T, ei (7)
3.2. Voltage controlled oscilattor
The proportional term computation is identical to the
The VCO, implemented using the DDS, must take into uniform sampling case:
account each sampling period to compute the phase
increment. Hence, the expression of the phase computation
for each cycle is: pi = Kp ei (8)

61 =61-1 +C T, (4) The PI filter output is computed as the sum of both terms:

where 0i is the phase accumulator, an unsigned integer Pi = Ii + P (9)

variable that represents the minimum phase with a zero and
the maximum phase (2ic) with its maximum value (2n-1, 3.5. Lock detector
where n is the word size in bits). The variable co is the
waveform frequency, and T, is the sampling period. The lock detector (LD) is used to identify the PLL state.
In RS based DSP, usually the sampling frequency is below The implemented LD computes the following expression:
the VCO frequency. Hence, the phase increment (coT) is
greater than the phase accumulator maximum limit. The
most significant bits (MSBs) of the phase increment are LD, q1 in(t) (10)
ignored, and the addition is computed only with the phase
accumulator word sisize.
Thccumulato
sToes
woup computed u
(or nle 1o
sinwavsymmetrWhen
where qi is the quadrature component (shifted 900) of the

poeriodsithethe samples
compte
a VCO signal, Pi,. and LDi is the lock detector output signal.
samplesofacompletesinewave the PLL is locked, this signal is composed by DC a
component and high frequency AC components. When it is
not locked, its DC value is zero. Hence, a low-pass filter
pi = table [6, >> SHIFT] (5) (LPF) is used to filter-out the AC components and keep
only the DC value.
The implemented LPF is a first order IIR (infinite impulse
where Pi is the VCO output al instant 4i, table[*] is a vector response) filter, whose mathematical expression is:
that holds the sine table, with a power of 2 number of
elements (e.g. 1024). The symbol >> indicates an arithmetic
right shift. For more details, refer to [7]. Yi = boxi + blxi- (11l)

3.3. Phase detector

The PD is implemented as a scalar product, which produces
a nonlinear (sinusoidal) phase response. There are better
PDs, with linear phase responses but with much higher
computational cost (e.g. tangent detector).
The phase error is computed as:
where x and y are the filter input at output signals.
Constants al, bo and b1 are the filter coefficients.
The DC component of the LD output depends on the input
signal amplitude, and the stability of the lock state.
Assuming an input signal with unitary amplitude, the
maximum output ofthe filtered LD signal is 1/2. When the
PLL output frequency has noise or AC components, the

3
PLL output signal is modulated in frequency and the LD Spartan3E FPGA
signal amplitude is modified. Hence, the LD signal level -------------------------------------
can be used as an indication ofhow well is the PLL locked. D
.DCM K r MicroBlaze
#1 ~32bit processor]
4. IMPLEMENTATION
50MHz ++ OPB bus
The implementation is based on a Xilinx board (Spartan3E
Starter Kit). This board has the following features, relevant
clock |+DCM r 1
to the presented implementation: D2 PLL UART
* Spartan3E FPGA with 500000 equivalent gates I
(XC3S5500E),
* 50MHz crystal oscillator,
* asynchronous serial port, with RS232 drivers,
* expansion connector with 100 1O pins, Fig. 4: Simplified block diagram of the system architecture.
* flash memory for bitstream storage,
* USB port for FPGA configuration and memory parameters and read the PLL signals by using these
progBporammi
prgamig registers.
protocol
The PC communicates with the MB using a
that allows the following actions:
For more details, refer to the board datasheet [10].
The XC3S500E has 20 embedded 18bit multipliers [11]
p otlhtlo the fLL actios:
* Configure the PLL parameters: PI constants,peR
which make it a powerful chip for performing DSP tasks. coefficients, initial frequency and random period
The advanced architecture and high gate count made generation.
possible the implementation of the high-speed PLL and an * Configure the interrupt frequency.
embedded microprocessor in a single chip. * Read the PLL outputs.
Fig. 3 shows a simplified block diagram of the * Read the PLL internal signals.
implemented system. The FPGA board is connected to a The MB receives periodic interrupt requests (IRQs) from
personal computer (PC) through a serial port. The PC the PLL, which are synchronized with the processing clock.
configures the PLL parameters and monitors the PLL state. The interrupt service reads the PLL output signals and
An ADC board is used to digitize the PLL input signal. stores them in a temporal buffer for a posterior transference
This board contains a high speed amplifier and an ADC to the PC.
from Texas Instruments (ADC8342), with on-chip sample Fig. 5 shows a simplified block diagram of the algorithms
and hold circuit. This ADC is a SAR (successive implemented in the FPGA. The ADC converter is triggered
approximation register) type, and is suitable for by Timerl at the random sampling times. When a
undersampling applications (i.e. the input bandwidth, conversion is available, it is latched and used as an input of
166MHz, is higher than the maximum sampling frequency, the PLL block, which is detailed in Fig. 6. Timerl is fed by
250ksps). the sampling period generator (TsGen), based on the ARS
The FPGA reads the ADC conversions through an 8bit bus, scheme, and shown in Fig. 7. A second timer (Timer2) is
controls the sampling instants with a trigger signal, and used to generate periodical interrupts, with programmable
synchronizes the ADC sequential logic with a clock signal. frequency. The MicroBlaze (MB) processor is used to set
The digital logic programmed in the FPGA is described in the PLL and TsGen parameters, and to read the PLL signals
Fig. 4. A MicroBlaze (MB) [12] embedded processor is (e.g. fUt and LD).
used to control the whole system. The on-chip peripheral
bus (OPB) is used to connect the MB to the on-chip PLL param.
peripherals, such as an UART [13]. The PLL is built as S erial
another MB peripheral, connected to the OPB using the ADC PLL LD MB
IPIF (intellectual property interface) [14]. ADC IADC Pl
The PLL constants and variables are available to the MB as F-F +
external registers. Thus, the MB can modify the PLL ADC P

|
PC 1. d ADC
signals
. npu| ADC_elk
.~~~~~~~~~~~~~~~~~~~~~~~Tclock~rigerTSMBcl
Timer_elk param.:
~~~~~~~CnrL Ext. DC2Tmr mt erio DC

Fig. 3: Simplified block diagram of the implemented

hardware. Fig. 5: Block diagram ofthe implemented algorithms.

4
Clock 5. EXPERIMENTAL RESULTS
Input
. . C Pi The experimental tests consist on applying different input
frequencies to the PLL and study its dynamic and stationary
vco response. The output variables used to monitor the PLL
y state are the output frequency (f11t) and the LD signal. The
X LD LD signal level is used as an indicator of the PLL
synchronization.
The PI constants determine the PLL characteristics. Higher
Fig. 6: PLL block diagram. constants set higher loop bandwidths and faster lock times.
A higher bandwidth deteriorates the PLL output signal
Clock quality and frequency stability, as is shown in the
.P--- genexperimental results.
PN gn +, M+r The first test consists on analyzing the PLL output signals
M g / at steady state, locked with a 1MHz input signal. Three
Ts par Const. different PI constants pairs are compared to show its effects
in the fout and LD signals. Fig. 8 shows the PLL output
Fig. 7: Block diagram of the ARS period generator. signals and Table 2 shows the statistical properties of these
Table 1 shows the most relevant data of the FPGA resource signals.
utilization. The dedicated multipliers utilization is high The second test shows the dynamic response of the PLL.
because of the signal processing required by the PLL. The The input signal frequency varies as a periodic square-
number of bits used in each arithmetic operation was wave. Fig. 9 shows the PLL output signals. Plots a) and b)
optimized to reduce the number of used multipliers, while show the response for a low loop bandwidth (K,=0. 1,
keeping high accuracy in the signal processing. Some _ _ _ _ _ _ _
multiplications do not require high resolution (e.g. PD) and s 1.05
were implemented using a single 18x18 multiplier. Other . is
products need higher resolution (e.g. IIR filter), and were °
implemented using more multipliers in order to reach a 0.95 LI
higher word size. x 1.05
The maximum operating frequency of the PLL signal I
processing block is 25MHz. An equivalent DSP 1
implementation would require a clock frequency of more ' 0.95 ___
than 600MHz, only for the PLL signal processing. x .05
The ADC limits the maximum processing speed of the I.
implemented prototype. The used ADC maximum
frequency is 250kHz, which limits the minimum value of 0.95 -_
the M constant in (2), and the maximum clock frequency is 0.5 _
5MHz (which limits the a value). Hence, the maximum 0
input frequency of the implemented PLL is 2.5Mhz with a 0.2
mean sampling frequency of 140kHz. _,_, _1
0.1 0.15 0.2 0.25
Table 1: FPGA resource utilization. Time [s]

AvailabiliTy Utilization
Availability [MB only MB+PLL
Fig. 8: Fixed input frequency test. Output frequency (a, b
Resource
Resource
and c) and LD signals for three different loop bandwidths.
Dedicated
multipliers 20 0 15 Table 2: Results of the fixed input frequency test.
RAM blocks 20 16 16 PT constants 1f0ut mean1 f0ut std.dev. [LD mean
[MHzI | t[kHz] [ n.u.I
Slices 4656 1153 2200 Kj=,K=. 1.00 19.1 0.382
DCM 4 1 2 FK,,0.5,Kr0.05 1.00 8.17 0.459
[ External inputs 232 | 4 15 | Kp=0.1, Kr0.01 1.00 1.49 0.492

5
KrO.O 1) and plots c) and d) for a higher loop bandwidth convenient than DSPs for RS-based signal processing
(Kp=0.5, KI0.05). because some RS specific tasks can be efficiently
The last figure shows the PLL response to an input signal implemented using programmable logic. Moreover, the
modulated in frequency with a sinusoidal. The first plot (a) signal processing required for the PLL is suitable for FPGA
of Fig. 10 shows the response with the low loop bandwidth, implementations because many of its operations can be
and the second plot (b) with the higher bandwidth. executed in parallel.
The three tests show that the PLL is able to operate The presented experimental results show that the prototype
correctly. The PI constants determine the PLL speed and is able to work with frequencies much higher than the
frequency stability. sampling frequency (more than ten times). This allows the
implementation of very high frequency systems with digital
6. CONCLUSIONS signal processing.
Potential applications of the proposed PLL are high
In this paper a phase locked loop that uses random precision instruments [4] and software-based radio-
sampling was proposed. The proposed PLL is implemented frequency systems [5], allowing the implementation of
in a low-cost FPGA. completely reconfigurable systems using FPGAs.
The presented implementation shows that FPGAs are more
7. REFERENCES
N
x0.85,
0.85\ .
y \ [1] A.V. Oppenheim and R.W. Schafer, Discrete-Time Signal
° 0.8 Processing, Prentice-Hall, pp. 447-448, 1989.
0.5 [2] R.G. Vaughan, N.L. Scott and D.R. White, "The Theory of
0.5 / l l / llBandpass Sampling," EEE Trans. Signal Processing, Vol.
0.25 39, No. 9, pp. 1973-1984, 1991.
o1 \,l \ Vl \l[3] Processing,
I. Bilinskis and A. Mikelsons, Randomized Signal
Prentice Hall International, USA, 1992.
0.85 [4] M.O. Sonnaillon, R. Urteaga and F. J. Bonetto, "Random
Sampling in High-Frequency Digital Lock-In Amplifiers",
, 0.8 Latin America Applied Research (LAAR), Vol. 36, Issue 3,
-7 0.5 pp. 181-186, Jul 2006.
025
v[5] J.J. Wojtiuk, Randomized Sampling for Radio Design, PhD
S 0.25 Thesis, Univ. of de South Australia, Australia, 2000.
0 [6] R.E. Best, Phase-Locked Loops - Design, Simulation, and
0 0.05 0.1 0.15 0.2 0.25 Applications, 4th Ed., McGraw-Hill, 1996.
Time [s]
[7] Analog Devices Inc. (1999) A technical tutorial on Direct
Fig. 9: Square wave input frequency test. Output frequency Digital Synthesis. http://www.analog.com
(a and c) and LD signal (b and d) for two different loop [8] A. Miller and M. Gulotta, "PN Generators Using the SRL
bandwidths. Macro," Xilinx Application Note, XAPP211 vi.2, Jun. 2004.
1.05 [9] G. Maria and P. Alfke, "Linear Feedback Shift Registers in
Virtex Devices," Xilinx Application Note, XAPP210 vl.2,
Jan 2001.
0.95
u 0.9k W W W q [10] Xilinx Inc., "Spartan3E Starter Kit Board User Guide,"
< 0.85 UG230 vl.0, Mar. 2006.
1.05 t VW kl [11] Xilinx Inc., "Spartan3E FPGA Family: Complete
Datasheet," DS312, May. 2006.
0.95% | > | 1 /} [12] Xilinx Inc., "MicroBlaze Processor Reference Guide,"
4 0.9g v UG081 v5.4, Feb. 2006.
0.85 [13] Xilinx Inc., "OPB UART Lite v1.OOb," DS422, Dec. 2005.
0.15 0.2 0.25 [14] Xilinx Inc., "OPB JIPIIF Architecture," DS414 v1.3, Jan.
Time [s] 2003.

Fig. 10: Sinusoidal input frequency test. Output frequency

for two different loop bandwidth. The LD mean value for a)
0,46 is and for b) is 0,37.