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Gate
March 1988
CD4001BM CD4001BC Quad 2-Input NOR Buffered B Series Gate CD4011BM CD4011BC Quad 2-Input NAND Buffered B Series Gate
General Description
These quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors They have equal source and sink current capabilities and conform to standard B series output drive The devices also have buffered outputs which improve transfer characteristics by providing very high gain All inputs are protected against static discharge with diodes to VDD and VSS
Features
Y Y Y Y
Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS 5V 10V 15V parametric ratings Symmetrical output characteristics Maximum input leakage 1 mA at 15V over full temperature range
Schematic Diagrams
CD4001BC BM
TL F 5939 2
TL F 5939 1
CD4011BC BM
TL F 5939 6
TL F 5939
RRD-B30M105 Printed in U S A
Operating Conditions
Operating Range (VDD) Operating Temperature Range CD4001BM CD4011BM CD4001BC CD4011BC 3 VDC to 15 VDC
b 55 C to a 125 C b 40 C to a 85 C
700 mW 500 mW
b 0 5 VDC to a 18 VDC b 65 C to a 150 C
Units mA mA mA V V V V V V
Min
Max 0 25 0 50 10 0 05 0 05 0 05
Min
Max 0 25 0 50 10 0 05 0 05 0 05
Min
Max 75 15 30 0 05 0 05 0 05
VOL
VOH
VIL
VDD e 5V VO e 4 5V VDD e 10V VO e 9 0V VDD e 15V VO e 13 5V VDD e 5V VO e 0 5V VDD e 10V VO e 1 0V VDD e 15V VO e 1 5V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V VDD e 5V VO e 4 6V VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V VDD e 15V VIN e 0V VDD e 15V VIN e 15V 35 70 11 0 0 64 16 42
b 0 64 b1 6 b4 2
( (
l IO l k 1 m A l IO l k 1 m A
4 95 9 95 14 95
4 95 9 95 14 95 15 30 40 35 70 11 0 0 51 13 34
b 0 51 b1 3 b3 4 b 0 10
5 10 15 2 4 6 3 6 9 0 88 2 25 88
b 0 88 b 2 25 b8 8 b 10 b 5 b 0 10
4 95 9 95 14 95 15 30 40 35 70 11 0 0 36 09 24
b 0 36 b0 9 b2 4 b1 0
15 30 40
V V V V V V mA mA mA mA mA mA
VIH
IOL
IOH
IIN
0 10
10b5
0 10
10
mA mA
Connection Diagrams
CD4001BC CD4001BM Dual-In-Line Package CD4011BC CD4011BM Dual-In-Line Package
TL F 5939 4
Top View
TL F 59393
Top View 2
CD4011BC (Note 2)
b 40 C a 25 C a 85 C
Units mA mA mA V V V V V V
Min
Max 1 2 4 0 05 0 05 0 05
Min
Max 1 2 4 0 05 0 05 0 05
Min
Max 75 15 30 0 05 0 05 0 05
VOL
VOH
VIL
VDD e 5V VO e 4 5V VDD e 10V VO e 9 0V VDD e 15V VO e 13 5V VDD e 5V VO e 0 5V VDD e 10V VO e 1 0V VDD e 15V VO e 1 5V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V VDD e 5V VO e 4 6V VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V VDD e 15V VIN e 0V VDD e 15V VIN e 15V 35 70 11 0 0 52 13 36
b 0 52 b1 3 b3 6
( (ll
l IO l k 1 m A
IO k 1 m A 4 95 9 95 14 95
4 95 9 95 14 95 15 30 40 35 70 11 0 0 44 11 30
b 0 44 b1 1 b3 0 b 0 30
5 10 15 2 4 6 3 6 9 0 88 2 25 88
b 0 88 b 2 25 b8 8 b 10 b 5 b 0 30
4 95 9 95 14 95 15 30 40 35 70 11 0 0 36 09 24
b 0 36 b0 9 b2 4 b1 0
15 30 40
V V V V V V mA mA mA mA mA mA
VIH
IOL
IOH
IIN
0 30
10b5
0 30
10
mA mA
tPLH
tTHL tTLH
CIN CPD
AC Parameters are guaranteed by DC correlated testing Note 1 Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed Except for Operating Temperature Range they are not meant to imply that the devices should be operated at these limits The table of Electrical Characteristics provides conditions for actual device operation Note 2 All voltages measured with respect to VSS unless otherwise specified Note 3 IOL and IOH are tested one output at a time
tPLH
tTHL tTLH
CIN CPD
TL F 59397
TL F 5939 8
TL F 5939 9
TL F 5939 11 TL F 593910
TL F 5939 12
FIGURE 5
FIGURE 6
TL F 593913
TL F 5939 14
TL F 5939 15
FIGURE 7
FIGURE 8
FIGURE 9
TL F 593916
FIGURE 10 FIGURE 11
TL F 5939 18 TL F 5939 17
FIGURE 12
TL F 5939 19
TL F 5939 20
FIGURE 13
FIGURE 14
CD4001BM CD4001BC Quad 2-Input NOR Buffered B Series Gate CD4011BM CD4011BC Quad 2-Input NAND Buffered B Series Gate
Ceramic Dual-In-Line Package (J) Order Number CD4001BMJ CD4001BCJ CD40011BMJ or CD4011BCJ NS Package Number J14A
Molded Dual-In-Line Package (N) Order Number CD4001BMN CD4001BCN CD4011BMN or CD4011BCN NS Package Number N14A
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2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness
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National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications