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Experiment: 1

Conduction Date:
BJT AMPLIFIER

DESIGN & TESTING OF A RC COUPLED SINGLE STAGE

Aim: Wiring of a RC coupled single stage BJT amplifier and determination of the gainfrequency response, input and output impedances. Apparatus required Transistor BC107, power supply, capacitors 0.22F, 47F, resistors, connecting board, signal generator, digital multimeter and CRO. Theory: This is the most popular type of coupling because it is cheap and provides excellent audio fidelity over a wide range of frequency. It is usually employed for voltage amplification. Fig.3.1 shows the single stage of an RC coupled amplifier. The coupling does not affect the Q point of the next stage since the C 2 blocks the dc voltage of the first stage from reaching the base of the second stage or output. The function of C 1 is to couple the signal source vi to the base of the transistor. At the same time it prevents the dc current of Vcc from reaching the signal source v i and also prevents any dc component present in v i from reaching of base.The bypass capacitor C e is used to prevent the loss of gain due to negative feedback across the resistor Re .Resistors R1, R2, and Re are used to bias the transistor so that the operating point lie on the middle of the dc load line.The resistor R c acts as ac load for the amplifier.The RC network is broadband in nature. Therefore, it gives a wideband frequency response and hence used to cover AF range of amplifier. Procedure to obtain frequency response:
1) Before wiring the circuit, check all the components using multimeter. Connect the

circuit as shown in the figure. Set Vcc for the designed value, and check the DC biasing conditions such as VBE, VCE. VBE0.6V (for Silicon transistor), VCEVCC/2.
2) If the DC biasing conditions satisfy then set the signal generator (input-voltage) amplitude (peak-to-peak sine wave) so that the output remains sinusoidal. Note the maximum signal handling capacity (MSHC) of the amplifier. It is the input signal to

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the amplifier at which output remains just sinusoidal. This means that if the input increased beyond this value, output no longer remains sinusoidal.
3) Keep the input signal less than MSHC (do not change the input further) and vary the frequency of the input from lower range to higher range. Observe both input and output simultaneously on the CRO. Note the input value (peak to peak) and outputs across RL corresponding to the variation in frequencies of the input signal at different intervals. The output voltage remains constant at mid frequency range.

4) Plot the graph with frequency along X-axis and gain dB along Y-axis. 5) From graph determine bandwidth. Procedure to find input impedance: 1) Connect the circuit as shown in Fig 3.2.
2) Connect a resistance RS in series with the input signal and amplifier as shown in

the figure 3.2. 3) Set the signal generator (input voltage) amplitude (peak to peak sine wave) less than MSHC at a mid frequency band.
4) Measure and note down the input voltage Vi before RS and voltage Vi after RS.

5) Calculate the input impedance. Procedure to find output impedance 1) Connect the circuit as shown in Fig 3.3.
2) Connect a resistance RL across the output terminals of the amplifier as shown in

the figure 3.3. 3) Set the signal generator (input voltage) amplitude (peak to peak sine wave) less than MSHC at a mid frequency band.
4) Measure and note down the output voltage V o across output terminals when R L is

open circuited and output voltage V o when RL connected across the output terminals and calculate output impedance

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CIRCUIT DIAGRAM

DESIGN
Let : Vcc=20V, Ic=10Ma,VcE=Vcc/2=10V, Pd=VcEQ ICEQ=10*10*1e-3=100mw

VEVcc/10=20/10=2V ;IEIc ;RE=VE/IE=2/10*1e-3=200 select standard value RE=220 VE=2*10*1e-3=2.2V Rc=(Vcc-VcE-VE)/Ic =(20-10-2)/10*1e-3=780 select standard value Rc=820 R2 RE/10
=GFE=125(min)2750

select R2=2.7K VB=0.7+2.2=2.9V 2.9=(2.7*1e3*20)/(R1+2.7*1e3) = 15920 select standard value of 18K Lower cut off frequency f1=100Hz C20.22F,C1=C2=0.22F CF=1/(2f1Xc2) Xc2=hie/(1+hfe) hie=1.5K, hfe=60 =24.6 CF=64.69F Select standard value of 47F or 100F Circuit Diagram to Measure Input Impedance:

Fig.3.2

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Circuit Diagram to Measure Output Impedance:

Fig.3.3 Tabulation Maximum Signal Handling Capacity =___________mV Input Voltage Vi = _________mV Sl. No. Frequency f in Hz Output voltage
V0 in mV

Gain in dB= 20log(V0/Vi)

Calculations: Input Impedance

Zi = Vi`*RS/(Vi-Vi`)

Output Impedance ZO = (Vo-Vo`)RL/Vo` Current gain AI = -AV(Zi/RL) Av = Vo/Vi Voltage gain Result:-

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DESIGN AND TESTING O DAR!INGTON E"ITTER O!!O#ER Aim: Design and testing of Darlington emitter follower. Apparatus re$uired: Transistor (SL100), Resistor, DC regulated power supply, oltmeter, !mmeter, signal "enerator, CR# and $apa$itors. T%eor&:
A very popular connection of two BJTs for operation as one super beta transistor is the Darlington connection. The main feature of Darlington connection is that the composite transistor acts, as a single unit with a current gain is e ual to pro!uct of in!ivi!ual current gains.

i.e.

%D&%1'%(

if %1& %(& %

T)en %D& %( pair, t)e emitter terminal of t)e first

To ma*e t)e two transistors Darlington

transistor is $onne$ted to t)e +ase of t)e se$ond transistor and t)e $olle$tor terminals of t)e two transistors are $onne$ted toget)er. T)e result is t)at emitter $urrent of t)e first transistor is t)e +ase $urrent of t)e se$ond transistor. T)e +iasing analysis is similar to t)at for single transistor e'$ept t)at two ,-. drops are to +e $onsidered. /n a $ir$uit if t)e output oltage is appro'imately e0ual to t)e input oltage, su$) a $ir$uit is *nown as emitter follower. /n t)e transistor emitter follower $ir$uit t)e output is ta*en from t)e emitter terminal. T)e oltage gain is appro'imately e0ual to unity and output oltage is in p)ase wit) t)e input oltage. T)e emitter follower $onfiguration is fre0uently used for impedan$e mat$)ing and to in$rease t)e $urrent gain. Sometimes t)e $urrent gain and input impedan$e of emitter followers are insuffi$ient to meet t)e re0uirement. /n order to in$rease t)e o erall alues of $ir$uit $urrent gain (!i) and input impedan$e, two transistors are $onne$ted in series in emitter follower $onfiguration to o+tain Darlington $onne$tion. 'rocedure to o(tain )re$uenc& response: 1) -efore wiring t)e $ir$uit, all t)e $omponents using multimeter. () 1a*e t)e $onne$tion as s)own in $ir$uit diagram. 2) Set ,CC, measure t)e DC +iasing oltages using multimeter at,C( ($olle$tor Department Of Electronics and Communication Page !

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A E C Lab Manual

oltage), ,.( (emitter oltage) wit) respe$t to ground t)en erify ,C.(&,C(3,.( /C(&/.(&,.(4R. point& (,C.(, /C() 5) Set t)e signal generator (input oltage) amplitude to output remains sinusoidal and o+ser e t)e input and simultaneously on CR#. su$) t)at t)e output signals

6) -y arying t)e fre0uen$y of t)e input from low alue to )ig) alue note down pea*3to3pea* alues of output and $orresponding fre0uen$y. T)e output oltage ,o remains $onstant in mid fre0uen$y range. Ta+ulate t)e readings in ta+ular $olumn. 7) Cal$ulate t)e gain in d- and 8lot t)e ariation of gain in d- as a fun$tion of fre0uen$y in semi log s)eet. 9) :rom grap) determine t)e +andwidt). 'rocedure to )ind input impedance: 1) Conne$t t)e $ir$uit as s)own in :ig 2.(. () Conne$t a resistan$e RS in series wit) t)e input signal and amplifier as s)own in t)e figure 2.(. 2) Set t)e signal generator (input oltage) amplitude (pea* to pea* sine wa e) less t)an 1S;C at a mid fre0uen$y +and. 5) 1easure and note down t)e input oltage ,i +efore RS and oltage ,<i after RS. 6) Cal$ulate t)e input impedan$e. 'rocedure to )ind output impedance: 1) Conne$t t)e $ir$uit as s)own in :ig 2.2. () Conne$t a resistan$e RL a$ross t)e output terminals of t)e amplifier as s)own in t)e figure 2.2. 2) Set t)e signal generator (input oltage) amplitude (pea* to pea* sine wa e) less t)an 1S;C at a mid fre0uen$y +and. 5) 1easure and note down t)e output oltage ,o a$ross output terminals w)en RL is open $ir$uited and output oltage ,<o w)en RL $onne$ted a$ross t)e output terminals. Cal$ulate t)e output impedan$e. C/RC=/T: wit)out -ootstrapping Department Of Electronics and Communication Page "

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A E C Lab Manual

,CC&10, R1&7>0 R(&1*? R2&10*? R. &(.(*? C1&C(&0.1@:

C/RC=/T: Ait) -ootstrapping

C-&10u: Cir$uit Diagram to 1easure /nput /mpedan$e:

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Cir$uit Diagram to 1easure #utput /mpedan$e:

:ig.2.2 Ta+ulation: /nput ,oltage ,i & BBBBBBBBBm, Sl. Co. :re0uen$y f in ;D #utput oltage ,0 in m, "ain in d-& (0log(,04,i)

Cal$ulations: /nput /mpedan$e #utput /mpedan$e Ei & ,iFGRS4(,i3,iF) E# & (,o3,oF)RL4,oF

Current gain !/ & 3!,(Ei4RL) ,oltage gain ! & ,o4,i Results :Department Of Electronics and Communication Page $

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A E C Lab Manual

Experiment No* :+

Conduction Date :

TESTING O A SERIES ,O!TAGE EED-AC. A"'!I IER* Aim: Testing of a series oltage feed+a$* amplifier to o+tain fre0uen$y response wit) and wit) out feed+a$*. Apparatus re$uired: -HTs, Resistors, Capa$itors, Signal generators, DC power supply, $onne$ting +oard and CR#. T%eor&: :eed+a$* plays an important role in almost all ele$troni$ $ir$uits. /t is almost in aria+ly used in t)e amplifier to impro e its performan$e and to ma*e it more ideal. /n Department Of Electronics and Communication Page %

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A E C Lab Manual

t)e pro$ess of feed+a$*, a part of output is sampled and feed+a$* to t)e input of t)e amplifier. T)erefore, at input we )a e two signals. /nput signal and part of t)e output, w)i$) is feed+a$* to t)e input. :eed+a$* $an +e negati e or positi e and )en$e, depending on t)e sign of t)e feed+a$* signal, feed+a$* system $an +e $lassified as negati e feed+a$* system and positi e feed+a$* system.T)ere are four +asi$ ways of $onne$ting t)e negati e feed+a$* signal. -ot) oltage and $urrent $an +e fed +a$* to t)e input eit)er in series or parallel. Spe$ifi$ally, t)ere $an +e. 1) ,oltage I series feed+a$* () ,oltage I s)unt feed+a$* 2) Current I series feed+a$* 5) Current I s)unt feed+a$* /n t)e list a+o e, oltage refers to $onne$ting t)e output oltage as input to t)e feed+a$* networ*J $urrent refers to tapping off some output $urrent t)roug) t)e feed+a$* networ*J Series refers to $onne$ting t)e feed+a$* signal in series wit) t)e input signal oltageJs)unt refers to $onne$ting t)e feed+a$* signal in s)unt (parallel) wit) an input $urrent ur$e.Series feed+a$* $onne$tions tend to in$rease t)e input resistan$e w)ile s)unt feed+a$* $onne$tions tend to de$rease t)e input resistan$e, oltage feed+a$* tends to de$rease t)e output impedan$e w)ile $urrent feed+a$* tends to in$rease t)e output impedan$e.Typi$ally, )ig)er input and lower output impedan$es are desired for most $as$ade amplifiers. -ot) of t)ese are pro ided using t)e oltage3series feed+a$* $onne$tion. 'rocedure: 1) -efore wiring t)e $ir$uit, $)e$* t)e entire $omponent using multimeter. () 1a*e t)e $onne$tions as s)own in t)e $ir$uit diagram. 2) C)e$* t)e DC +iasing $onditions. 5) /f t)e DC +iasing $onditions are satisfa$tory, t)en apply t)e input a$ signal 6) ,ary t)e fre0uen$y of t)e input signal and note t)e $orresponding fre0uen$y of signal and output oltage a$ross t)e load resistor (RL) wit) respe$t to ground. 7) ,ary fre0uen$y so t)at t)e output oltage ,o remains $onstant in mid3fre0uen$y range and output oltage is lesser t)an mid fre0uen$y range at lower and )ig)er fre0uen$ies. 9) 8lot t)e grap) of gain in d- ,s fre0uen$y. >) :rom grap) determine +andwidt). !mplifier wit)out feed+a$*"

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K1&K(&-C109, ,CC&1(,, R1&59*?, R(&5(*?, R$&9>0?, R.&5.9*?, R2&((*?, R5&(9*? R$(&220?, R.(&(,9*?, Rf1&220?, C1&0.(6L:, C(&10L:, C2&10L:, C-(&C-&59L: !mplifier wit) feed+a$*:

K1&K(&-C109,,CC&1(, R1&59*? R(&5(*? R$&9>0? R.&5.9*? R2&((*? R5&(9*? R$(&220? R.(&(,9*? Rf1&220? Rf(&10*? Cf&10L: C1&0.(6L: C(&10L: C2&10L: C-(&C-&59L: Circuit Dia/ram to "easure Input Impedance:

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Circuit Dia/ram to "easure Output Impedance:

Ta(ulation: /nput ,oltage ,i & BBBBBBBBBm, Sl. :re0uen$y Co. f in ;D #utput oltage ,0 in m, "ain in d-& (0log(,04,i)

Calculations: /nput /mpedan$e Ei & ,iFGRS4(,i3,iF) #utput /mpedan$e E# & (,o3,oF)RL4,oF Current gain !/ & 3!,(Ei4RL) ,oltage gain ! & ,o4,i Result : Experiment No* :1 Conduction Date :

WIRING AND TESTING OF RC PHASE SHIFT OSCILLATOR Aim: Airing and testing of RC p)ase s)ift os$illator.

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Apparatus re$uired: 8ower supply (0320,), Transistor3-C109, Resistors: 1*?, >(*?, 16*?, 5.9*?, pot.:036*?, Capa$itors: 59L:, 0.01L:, Signal generator, CR# and multimeters.. T%eor&: #s$illator is a $ir$uit used to generate different wa e forms. T)e use of positi e feed+a$* w)i$) results in a feed+a$* amplifier )a ing $losed loop gain greater t)an 1 and satisfies p)ase $ondition will result in operation as an os$illator. T)e RC p)ase3s)ift os$illator $onsists of a $on entional C. amplifier and RC p)ase3s)ift networ* as a feed+a$* system. T)e oltage s)unt feed+a$* is pro ided using t)ree se$tions of RC. !t some parti$ular fre0uen$y for t)e p)ase s)ift in ea$) RC se$tion is 70o, so t)at total p)ase s)ift produ$ed +y t)e RC networ* is 1>0o. T)e fre0uen$y of os$illation is gi en +y fo&14((MRC 7 N5*) A)ere, *&RC4R 1 'rocedure: 1. Sele$t pot of 0310* resistor in t)e last se$tion of p)ase s)ifting networ* to get a o erall p)ase s)ift of 1>0o at t)e fre0uen$y of os$illation. (. Conne$t t)e $ir$uit as s)own in t)e figure and set ,CC& 10,. 2. T)en erify t)e DC +iasing $onditions: ,C.&,CC4( and ,-.&0.9 , 5. T)e 10O pot is adPusted to get a sta+le sinusoidal output wa e. 6. 1easure t)e fre0uen$y of os$illation of t)e output wa e using t)e CR#. 7. Cote t)e p)ase s)ift +etween 2 se$tions of RC networ* wit) respe$t to t)e output wa e. 9. S*et$) t)e output wa e and wa eforms at 2 se$tions of RC networ*. CIRC2IT DIAGRA":

,CC&10 ,Re&1*?, R$&5.9*?, R1&>(*?, R(&16*?, Ce&59L:, R&5.9*? (*&1) or )310456 C&1000p:, 8ot.: R<&036*? Result :Experiment No* : 7 Department Of Electronics and Communication Conduction Date: Page 13

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TESTING O 5ART!E8 AND CO!'ITTS OSCI!!ATORS Aim: Testing of ;artley and ColpittFs os$illators. Apparatus re$uired: -HT, Resistors, Capa$itors, /ndu$tors, DC power supply and CR#. T%eor&: ;artley and Colpitts os$illators are t)e tuned $ir$uit os$illators. 5artle& oscillator /f t)e os$illator $onsists of two indu$tors, and one $apa$itor in t)e feed+a$* networ* t)at is tan* $ir$uit t)en it is $alled ;artley os$illator. ;artley os$illator $onsists of a -HT C. amplifier wit) tan* $ir$uit (feed+a$* networ*). T)e resistan$es R1, R(, RC and R. +ias t)e -HT. T)e C. amplifier pro ides a p)ase s)ift of 1>0Q and tan* $ir$uit pro ides p)ase s)ift of anot)er 1>0Q, t)is satisfies t)e re0uired os$illating $ondition of total p)ase s)ift of 270o. :re0uen$y of os$illations in t)e output wa e is: fo&14R(M CLe0 S w)ere Le0&L1NL( Colpitts oscillator: /f t)e os$illator uses two $apa$itors and one indu$tor in t)e feed+a$* networ* t)en it is $alled a Colpitts os$illator. Colpitts os$illator $onsists of a -HT C. amplifier wit) tan* $ir$uit (feed+a$* networ*). T)e resistan$es R1, R(, RC and R. +ias t)e -HT. T)e C. amplifier pro ides a p)ase s)ift of 1>0Q and tan* $ir$uit pro ides p)ase s)ift of anot)er 1>0Q, t)is satisfies t)e re0uired os$illating $ondition of total p)ase s)ift of 270o. :re0uen$y of os$illations in t)e output wa e is: fo&14R(M LCe' S w)ere Ce0&C1C(4(C1NC() 'rocedure: 1. (. 2. 5. -efore wiring t)e $ir$uit, $)e$* all t)e $omponent using multimeter. 1a*e t)e $onne$tions as s)own in $ir$uit diagram. Design t)e tan* $ir$uit w)ere fo & 100 O;D. Set t)e alues of indu$tor and $apa$itor so as to get t)e re0uired fre0uen$y of os$illation. 6. Compare t)e alues of t)eoreti$al and pra$ti$al alues of fre0uen$y. 5artle& Oscillator: :re0uen$y of os$illation f&14(M A)ere, Le0&L1NL( :re0uen$y of os$illation re0uired: f&100 *;D Let L1&L(&0.1m; C& 0.1(9 n: (Sele$t standard alue of 0.1 n:)
LCe'

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Circuit Dia/ram

,CC&10 , Re&1*?, R$&5.9*?, R1&>(*?, , R(&16*?, Ce&59L:, L1&L(&0.1m;, C&0.1n: Colpitts Oscillator: :re0uen$y of os$illation f&14(M (Sele$t standard alue of ( m;)
LCe'

A)ere, Ce0&C1C(4(C1NC()

:re0uen$y of os$illation re0uired: f&100 *;D Let C1&C(&(.(n: L& (.2 m;

,CC&10 , Re&1*?, R$&5.9*?, R1&>(*?, R(&16*?, Ce&59L:, C1&C(&(.( n:, L&( m; Result : Department Of Electronics and Communication Page 1!

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Experiment No* :9

Conduction Date:

TESTING O TRANS OR"ER!ESS '2S5 '2!! 'O#ER A"'!I IER Aim: Testing of a $omplementary symmetry Class - power amplifier (Transformer less 8us) 8ull power amplifier. Apparatus re$uired: 8ower Transistors (SL100 and SO100), Resistors, load resistor,Capa$itors, fun$tion generator, DC power supply and CR#. T%eor&: Class - amplifier is one w)i$) gi es )alf (1>0Q) $y$le as output signal for one $omplete $y$le (270Q) of input signal. Complementary symmetry $lass - power amplifier needs two power transistors, among t)at one is npn and ot)er is pnp power transistor. T)e main ad antage of t)is amplifier is t)at t)e a+sen$e of t)e transformer w)i$) is more e'pensi e, +ul*y and )ea y. T)is type of transformer )as ma'imum effi$ien$y e0ual to 9>.6T. ! single input signal is applied to t)e +ase of +ot) transistors, t)e transistors, +eing opposite type, will $ondu$t on opposite )alf $y$les of t)e input. -ot) t)e transistors are +iased at $ut off regions of t)eir output $)ara$teristi$s, so t)at one of t)e transistors $ondu$ts during ea$) )alf $y$le. During a $omplete $y$le of t)e input a $omplete $y$le of output signal is Department Of Electronics and Communication Page 1"

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de eloped a$ross t)e load. #ne disad antage of t)e $ir$uit is t)e need for two separate oltage supplies. 'rocedure: 1. 1a*e t)e $onne$tions as s)own in t)e :ig. and ta*e proper $are w)ile gi ing +iasing oltage. (. !pply t)e input signal at a fre0uen$y of 1 *;D310 *;D. 2. !dPust t)e input oltage (pea*) e0ual to DC supply i.e. ,m&,CC. /f t)e output oltage is sine wa e t)en note t)e magnitude of output oltage, ot)erwise de$rease t)e input till t)e output remain sinusoidal and t)en note t)e magnitude of output oltage. 5. Cal$ulate 8ower input, output and effi$ien$y. Circuit Dia/ram:

K13SL100, K(3SO100, R1&R(&1*?, R2&100?, C1&C(&10:, RL&1(? Result :Experiment No* :: Conduction Date:

,ERI ICATION O T5E,ENIN;S AND "A<I"2" 'O#ER TRANS ER T5EORE" Aim: ,erifi$ation of T)e enin<s and 1a'imum 8ower Transfer t)eorem. Apparatus re$uired: Resistors, DC supply, ammeter and multimeter. T%eor&: T%e=inin;s T%eorem states t)at U!ny linear, +ilateral, two terminal networ* $an +e repla$ed +y a oltage sour$e in series wit) a resistan$e, w)ere alue of oltage sour$e is e0ual to open $ir$uited oltage +etween t)e load terminals and t)e resistan$e is e0ual to t)e resistan$e loo*ing from t)e open $ir$uited terminals repla$ing all t)e sour$e +y t)eir internal resistan$es if anyV. Let ,#C +e t)e open $ir$uited oltage a$ross t)e load resistan$e, RT; +e t)e T)e enin<s resistan$e of t)e $ir$uit. T)en, $urrent t)roug) t)e load resistan$e is gi en +y, /L&,#C4(RT;NRL) Department Of Electronics and Communication Page 1#

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"aximum 'o>er Trans)er T%eorem states t)at U/n any linear, +ilateral networ* t)e ma'imum power will +e transferred from t)e $ir$uit to t)e load if and only if load impedan$e is $omple' $onPugate of t)e internal impedan$eV #R :or DC $ir$uit it states t)at U./n any linear, +ilateral networ* t)e ma'imum power will +e transferred from t)e $ir$uit to t)e load if and only if load resistan$e is e0ual to t)e internal resistan$eV Let ,#C +e t)e open $ir$uited oltage a$ross t)e load resistan$e, R/ +e t)e internal resistan$e of t)e $ir$uit.T)en, ma'imum power will +e deli ered to t)e load resistan$e is gi en +y, 8ma'&,#C (45R/

'rocedure: T%e=inin;s T%eorem 1. 1a*e t)e $onne$tions as s)own in t)e :ig31 (. !dPust t)e DC supply oltage using multi3meter. 2. Cote t)e $urrent flowing t)roug) t)e load resistor. 5. Swit$) off t)e DC sour$eJ remo e t)e load resistor from t)e terminals (open $ir$uit). 6. Swit$) on DC sour$e and note ,#C a$ross t)e open $ir$uited terminals (:ig. (). 7. 1a*e $onne$tions as s)own in t)e :ig. 2 and find RT;. 9. 1a*e $onne$tions as s)own in t)e :ig. 5 to o+tain T)e enin<s e0ui alent $ir$uit and adPust ,#C and RT; as o+tained in steps 6 and 7. >. Cote t)e $urrent flowing t)roug) t)e load resistor. W. ,erify t)e $urrent o+tained in step 2 and >. "aximum 'o>er Trans)er T%eorem 1. 1a*e t)e $onne$tions as s)own in t)e :ig.1 (* !dPust t)e DC supply oltage using multimeter. 2. ,ary t)e load resistan$e from 100 o)m to 1*o)ms. 5. Cote t)e $urrent $orresponding to ea$) alue of load resistan$e. 6. Cal$ulate t)e power and erify t)e load resistan$e at w)i$) t)e power will +e ma'imum. T%e=enin;s t%eorem Circuit Dia/ram:

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Circuit to find Voc:

Circuit to find Rth:

"aximum 'o>er trans)er t%eorem Circuit Dia/ram:

To )ind ,oc:

'max3,oc2?1R! To find internal resistan$e Rin at w)i$) power transfer to t)e load RL is ma'imum: :ig to draw yet Department Of Electronics and Communication Page 1%

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A E C Lab Manual

To o(tain a plot o) po>er ,s R!:

Ta(ulation: SN R! in O%ms I! in mA '! in m#

Result :-

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Experiment No* :@

Conduction Date:

Series and 'arallel Resonant Circuits Aim: To o+tain t)e $)ara$teristi$s of series and parallel resonant $ir$uits. Apparatus re$uired: De$ade resistan$e +o', De$ade indu$tan$e +o', De$ade $apa$itan$e +o' and ammeter. T%eor&: Series Resonant Circuit: /n a series RLC $ir$uit t)ere +e$omes a fre0uen$y point were t)e indu$ti e rea$tan$e of t)e indu$tor +e$omes e0ual in alue to t)e $apa$iti e rea$tan$e of t)e $apa$itor. T)e point at w)i$) t)is o$$urs is $alled t)e Resonant re$uenc&, ( Xr ) and as we are analysing a series RLC $ir$uit t)is resonan$e fre0uen$y produ$es a Series Resonance $ir$uit. Series resonan$e $ir$uits are one of t)e most important $ir$uits used ele$troni$s. T)ey $an +e found in arious forms in mains !C filters, and also in radio and tele ision sets produ$ing a ery sele$ti e tuning $ir$uit for t)e re$ei ing t)e different $)annels. /n a series resonant $ir$uit, t)e resonant fre0uen$y, Xr point $an +e $al$ulated as follows fr&14(M
LC

Ae $an see t)en t)at at resonan$e, t)e two rea$tan$es $an$el ea$) ot)er out t)ere+y ma*ing a series LC $om+ination a$t as a s)ort $ir$uit wit) t)e only opposition to $urrent flow in a series resonan$e $ir$uit +eing t)e resistan$e, R. /n $omple' form, t)e resonant fre0uen$y is t)e fre0uen$y at w)i$) t)e total impedan$e of a series RLC $ir$uit is purely (real( as no imaginary impedan$es e'ist, t)ey are $an$elled out, so t)e total impedan$e of t)e series $ir$uit +e$omes Pust t)e alue of t)e resistan$e and: E & R. T)erefore, at resonan$e t)e impedan$e of t)e $ir$uit is at its minimum alue and e0ual to t)e resistan$e of t)e $ir$uit. Department Of Electronics and Communication Page 21

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A E C Lab Manual

T)e fre0uen$y response $ur e of a series resonan$e $ir$uit s)ows t)at t)e magnitude of t)e $urrent is a fun$tion of fre0uen$y and plotting t)is onto a grap) s)ows us t)at t)e response starts at near to Dero, rea$)es ma'imum alue at t)e resonan$e fre0uen$y w)en /1!Y & R and t)en drops again to nearly Dero as X +e$omes infinite. T)ese 32d- points gi e us a $urrent alue t)at is 90.9T of its ma'imum resonant alue as: 0.6( /( R ) & (0.909 ' /)( R. T)en t)e point $orresponding to t)e lower fre0uen$y at )alf t)e power is $alled t)e Zlower $ut3off fre0uen$yZ, la+elled XL wit) t)e point orresponding to t)e upper fre0uen$y at )alf power +eing $alled t)e Zupper $ut3off fre0uen$yZ, la+elled ;. T)e distan$e +etween t)ese two points, i.e. ( X; 3 XL ) is $alled t)e -and>idt%, (-A) and is t)e range of fre0uen$ies o er w)i$) at least )alf of t)e ma'imum power and $urrent is pro ided. 'arallel Resonant Circuit ! 8arallel $ir$uit $ontaining a resistan$e , R, an indu$tan$e , L and a $apa$itan$e . C will produ$e a parallel resonan$e (also Called anti3 resonan$e) $ir$uit w)en t)e resultant $urrent t)roug) t)e parallel $om+ination is in p)ase wit) supply oltage. at resonan$e t)ere will +e large $ir$ulating $urrent +etween t)e indu$tor and t)e $apa$itor due to t)e energy of t)e os$illations. ! parallel resonant $ir$uit stores t)e $ir$uit energy in t)e magneti$ field of t)e indu$tor and t)e ele$tri$ field of t)e $apa$itor. t)is energy is $onstantly +eing transferred +a$* and fort) +etween t)e indu$tor and t)e $apa$itor w)i$) results in Dero $urrent and energy +eing drawn from t)e supply . t)is is +e$ause t)e $orresponding instantaneous alues of /L and /C will always +e e0ual and opposite and t)erefore t)e $urrent drawn from t)e supply is t)e e$tor addition of t)ese two $urrents and t)e $urrent flowing in /R 8ro$edure: Series resonant Cir$uit: 1. -efore wiring t)e $ir$uit, $)e$* t)e $omponent using multi meter . (. 1a*e t)e $onne$tions as s)own in t)e $ir$uit diagram. 2. !pply oltage a$ross RLC series $ir$uit using fun$tion generator. 5. ,ary t)e fre0uen$y (or indu$tan$e or Capa$itan$e) in suita+le steps and note t)e total $urrent flow t)roug) t)e $ir$uit. Current rea$)es t)e ma'imum alue at series resonan$e. 6. 8lot t)e $ur e of $urrent against t)e fre0uen$y. 8arallel Resonant Cir$uit: 1. (. 2. 5. -efore wiring t)e $ir$uit, $)e$* t)e $omponent using multi meter . 1a*e t)e $onne$tions as s)own in t)e $ir$uit diagram. !pply oltage a$ross 8arallel resonant $ir$uit using fun$tion generator. ,ary t)e fre0uen$y (or indu$tan$e or Capa$itan$e) in suita+le steps and note t)e total $urrent flow t)roug) t)e $ir$uit. Current rea$)es t)e ma'imum alue at 8arallel resonan$e. 6. 8lot t)e $ur e of $urrent against t)e fre0uen$y. Department Of Electronics and Communication Page 22

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A E C Lab Manual

Cir$uit diagram for series resonant $ir$uit : ,arying :re0uen$y

,arying :re0uen$y

S.C

Capa$itan$e(@:)

Current (m!)

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S.C

:re0un$y(;D)

Current (m!)

,arying Capa$itan$e S.C /ndu$tan$e(m;) Current (m!)

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Circuit Dia/ram 'arallel resonant circuit

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,arying fre0uen$y

S.C

:re0un$y(;D)

Current (m!)

Result : -

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Experiment No* :A

Conduction Date:

DIODE C!I''ING CIRC2ITS Aim: To design and test diode $lipping $ir$uits for pea* $lipping and pea* dete$tion. Components re$uired: 38ower Supply 3Diodes /C5009or -[1(9 3Resistors 'rocedure: 1. 1a*e t)e Conne$tions as s)own in t)e $ir$uit diagram (. !pply sinusoidal input ,i of 1 O;D and of amplitude >, 838 to t)e $ir$uit. 2. #+ser e t)e output signal in t)e CR# and erify it wit) gi en wa eforms. 5. !pply ,i and ,o to t)e Y and [ $)annel of CR# and o+ser e t)e transfer $)ara$teristi$ wa eform and erify it. /) 'ositi=e Clippin/ Circuit: Circuit Dia/ram:

Trans)er C%aracteristics

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To )ind t%e =alue o) R: "i en: Rf &100\, Rr &100O\ Rf 3 Diode forward resistan$e Rr 3 Diode re erse resistan$e R& )f)r &2.17O \ C)oose R as 10 O\ Let t)e output oltage +e $lipped at N2, ,oma' &2, :rom t)e $ir$uit diagram, ,oma' & ,rN,ref A)ere ,r is t)e diode drop & 0.7, ,ref & ,oma' I,r & 2 3 0.9 ,re) 3 2*+ , //) Ne/ati=e Clippin/ Circuit: Circuit Dia/ram: #a=e orms

Transfer C)ara$teristi$s

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#et the output voltage be clippe! at $%& &omin ' $%& &omin ' $&r(&ref &ref ' &omin(&r ' $% ( ).* Vref = !"#V +++) Diode Serie$ C%i&&in' ( Po$iti)e Pe*+ C%i&&er: Circuit Di*'r*,: W*)efor,$

Transfer ,haracteristics

#et the output voltage be clippe! at -&. Circuit Dia/ram:

Vo,*- = Vref = !V

/,) Ne/ati=e 'ea4 Clipper: #a=e)orms Page 2%

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#et the output voltage be clippe! at $-& !V

Vo,in = Vref =

Transfer C)ara$teristi$s

,) Clippin/ at t>o independent le=els: Circuit Dia/ram: #a=e)orms

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Transfer ,haracteristics

Let ,oma' & 7, and ,omin & 2, ,r1 3 ,omax - ,r 3 9 B 0*: 3 7*+, ,r2 3 ,omin C ,r 3 + C 0*:3 +*:,

,oma' & ,r1 N ,r ,omin & ,r(3 ,r

&++) To C%i& * $ine .*)e /et.een 0!V *nd #V %e)e%: Circuit Di*'r*,: Ch*r*cteri$tic$ Tr*n$fer

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A E C Lab Manual

To ,lip a sine wave between (-& an! $%& level &o ' &1 ( &r &o ' &- $ &r &1 ' &o $ &r ' -$).* % ' &- . ).* &- ' $% ( ).* V1 = 1"2V V! = !"#V

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A E C Lab Manual

Experiment No* :A

Conduction Date:

Aim: Design and test positi e and negati e $lamping $ir$uit for a gi en referen$e oltage. Components re$uired: 3 8ower Supply 3 CR# 3 Signal "enerator 3 Diode -[ 1(9 3 Resistors 3 Capa$itor De$i'n: /f . Dio!e forwar! resistance ' 1))0 /r . Dio!e /everse resistance ' 11 0 / ' )f)r ' 1)20 /,33T #et T ' 1ms f41256) #et /, ' 1)T, /, ' 1)ms, , ' 178, / ' 1)20 /) 'ositi=e Clampin/ Circuits: Circuit Dia/ram:

Aa eforms

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//) Desi/n a Clampin/ Circuit to Clamp Ne/ati=e 'ea4 at C+,: Cir$uit Diagram

&o '&9 ( &ref,

% ' $).* ( &ref,

Vref = #"3

///) Ne/ati=e Clampin/ Circuit: Circuit Dia/ram:

/,) Desi/n a Clampin/ Circuit to clamp 'ositi=e 'ea4 at -+,:

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Circuit Dia/ram:

,o & ,] 3 ,ref ,ref & 3 ,o N ,] & N2N0.9

,re) 3 +*:

,) Desi/n a Clampin/ Circuit to Clamp Ne/ati=e 'ea4 at -+,: Circuit Dia/ram: #a=e)orm

,o & 3 (,] N ,ref)

,ref & 3,o 3& 3 0.9 I (3 2) ,re) 3C2*+,

,/) Desi/n a Clampin/ Circuit to clamp 'ositi=e 'ea4 at C+,: Circuit Dia/ram: #a=e)orms :

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,o & ,]N ,ref, ,ref & ,o 3 ,] & 2 3 0.9,

,re) 3 2*:,

Procedure: 1. /ig up the circuit. 2. Apply sinusoi!al input signal of :& ;$; from signal generator. 3. <bserve the output waveform in the ,/<. 4. =ote !own the rea!ings from the ,/< an! compare it with the e>pecte! values. Experiment No* :10 RECTI IER CIRC2ITS Aim: To design and test ;alf wa e, :ull wa e, -ridge Re$tifier $ir$uits wit) ^ wit)out $apa$itor filter and determine t)e Ripple fa$tor, Regulation ^ .ffi$ien$y. Components re$uired: 3 Resistors 3 Diodes 3 1(3031(, Transformer 3 Capa$itor Calculations: !ssume RL & 5.9O\, C & ((0L: I 4 5al) >a=e Recti)ier: 1. /ipple 8actor without 8ilter 4Theoretical) ' 1.-1 -. ;ercentage /egulation '4/f?/#)@1)) A " /f' Dio!e 8orwar! resistance. %. /ectifier Bfficiency C ' ).D)E?41( /f?/#) 'D).E4appro>) D. /ipple 8actor without filter F' 1?- 2 f/#, " f'G)56 II D ull #a=e Recti)ier 1. /ipple 8actor without 8ilter 4Theoretical) ' ).D: -. ;ercentage /egulation '4/f?/#)@1)) A " /f' Dio!e 8orwar! resistance. %. /ectifier Bfficiency C ' ).:1?41( /f?/#) ':14appro>) D. /ipple 8actor without filter F' 1?D 2 f/#, " f'G)56 IIII D -rid/e Recti)ier Department Of Electronics and Communication Page 3" Conduction Date:

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A E C Lab Manual

1. /ipple 8actor without 8ilter 4Theoretical) ' ).D: -. ;ercentage /egulation '4/f?/#)@1)) A " /f' Dio!e 8orwar! resistance. %. /ectifier Bfficiency C ' ).:1?41( /f?/#) ':14appro>) D. /ipple 8actor without filter F' 1?D 2 f/#, " f'G)56 'rocedure: 1. 1a*e t)e Conne$tions as s)own in t)e $ir$uit diagram (. !pply (20, !C supply from t)e power mains to t)e primary of t)e transformer 2. #+ser e t)e oltage a$ross se$ondary to get ,m , t)e pea* alue in CR# 5. =se rele ant formula to find ,d$ and ,rms of +ot) :ull wa e and ;alf wa e re$tifier ^ draw t)e wa eforms 6. :ind out t)e Ripple fa$tor, Regulation and .ffi$ien$y +y using t)e formula ID 5al) >a=e Recti)ier >it%out ilter: Circuit Dia/ram:

+nput &oltage ;eaH <utput &oltage &m'II. &D,' &m?J'II. &rms' &m?-'II. Department Of Electronics and Communication

<utput &oltage

Page 3#

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&ac ' I. /ipple 8actor F' &ac?&!cI.. Bfficiency C' &-!c?&-rms'I. A /egulation 'KL&!c4=#)$&!c48#)M? &!c48#)N @ 1)) 'I.

IID 5al) >a=e Recti)ier >it% ilter:

+nput voltage

5O/ output

<utput with filter

;eaH <utput &oltage &m'II. &!c' &m?L1(41?-f/#,)M 'II. &rms' &ac ' &r p$p?- 'I. /ipple 8actor F' &ac?&!cI.. /ectification Bfficiency C' &-!c?&-rms'I. Department Of Electronics and Communication Page 3$

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A /egulation 'KL&!c4=#)$&!c48#)M? &!c48#)N @1)) 'I.

IIID ull >a=e Recti)ier >it%out ilter: Circuit Dia/ram:

&D,' -&m?J'I. &rms' &m? ( 'I &ac' /ipple 8actor F' &ac?&!cI.. /ectification Bfficiency C' &-!c?&-rms'I. A /egulation 'KL&!c4=#)$&!c48#)M? &!c48#)N @1)) 'I. I,D ull >a=e Recti)ier >it% ilter: Circuit Dia/ram:

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,d$& ,m4R1N(145fRLC)S&_.. ,a$&,rp3p4( 2 &_ /ipple 8actor F' &ac?&!cI.. &rms' /ectification Bfficiency C' &-!c?&-rms'I. ,D -rid/e Recti)ier >it%out ilter: Circuit Dia/ram:

&D,' -&m?J'I. &rms' &m? ( 'I Department Of Electronics and Communication Page &

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&ac' /ipple 8actor F' &ac?&!cI.. /ectification Bfficiency C' &-!c?&-rms'I. A /egulation 'KL&!c4=#)$&!c48#)M? &!c48#)N @1)) 'I.

,ID -rid/e Recti)ier >it% ilter: Circuit Dia/ram:

,d$& ,m4R1N(145fRLC)S&_.. ,a$&,rp3p4( 2 &_ /ipple 8actor F' &ac?&!cI.. &rms' /ectification Bfficiency C' &-!c?&-rms'I. Result : 3

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