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Abstract: The design and field programmable gate array (FPGA)-based realisation of automatic censored cell
averaging (ACCA) constant false alarm rate (CFAR) detector based on ordered data variability (ODV) is
discussed here. The ACCA – ODV CFAR algorithm has been recently proposed in the literature for detecting
radar target in non-homogeneous background environments. The ACCA – ODV detector estimates the unknown
background level by dynamically selecting a suitable set of ranked cells and doing successive hypothesis tests.
The proposed detector does not require any prior information about the background environment. It uses the
variability index statistic as a shape parameter to accept or reject the ordered cells under investigation.
Recent advances in FPGA technology and availability of sophisticated design tools have made it possible to
realise the computation intensive ACCA –ODV detector in hardware, in a cost-effective way. The architecture is
modular and has been implemented and tested on an Altera Stratix II FPGA using Quartus II software. The
post place and route result show that the proposed design can operate at 100 MHz, the maximum clock
frequency of the prototyping board and for this frequency the total processing time required to perform a
single run is 0.21 ms. This amounts to a speedup for the FPGA-based hardware implementation by a factor of
110 as compared to software-based implementation, which takes 23 ms to perform the same operation.
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adaptive threshold based on a CFAR detector. This detector non-coherent integrator are fed sequentially into a shift
dynamically determines a detection threshold by estimating register. The adaptive threshold Z, which is proportional to
the local background noise/clutter power and multiplying this the estimate of the total noise power, is formed by
estimate by a scaling constant based on the desired Pfa . processing the contents of reference cells surrounding the
cell under test (CUT), whose content is Y. To maintain Pfa
Although software-based implementation is very flexible, the at the desired value, the adaptive threshold is multiplied by
whole CFAR processing may degrade the performance of the a scaling factor called the threshold multiplier T. The
processor. Hence, to accelerate the processing, it is proposed product TZ is the resulting adaptive threshold. The output
to realise the computationally intensive CFAR detector in Y from the CUT is then compared with the threshold in
field programmable gate array (FPGA) hardware. FPGAs order to make a decision. A target is declared to be present
are a form of programmable logic. They offer design if Y exceeds TZ.
flexibility like software, but with time performance closer to
application-specific integrated circuits. Recent advances in The processor configuration varies with different CFAR
FPGA technology have resulted in enormous possibilities for schemes. For example, cell averaging (CA) CFAR processor
the implementation of sophisticated algorithms of high sums the contents of surrounding cells to produce the
complexity, in a variety of important applications, by using statistic Z, that is
low cost, high performance and high speed reconfigurable
hardware. FPGAs have become one of the prevailing X
N
technologies for fast prototyping and implementation of Z¼ Xi (1)
complex digital systems [3]. In this paper, a novel FPGA- i¼1
based design and realisation of a complex automatic censored
cell averaging (ACCA) CFAR detector based on ordered For homogenous environments, the CA – CFAR processor is
data variability (ODV), proposed in [4], are presented. optimum. However, in the presence of interfering targets, the
assumption of homogenous environment is no longer valid.
The rest of this paper is organised as follows. Section 2 The performance of the CA– CFAR processor seriously
describes the background information on CFAR theory and degrades under such conditions. Various classes of CFAR
the related work done towards the hardware realisation of techniques have been proposed to enhance the robustness
different CFAR processors. Section 3 describes the against non-homogeneous environment for different
ACCA–ODV detection algorithm. The hardware applications [5]. In particular, ordered statistics (OS)-based
architecture of the proposed CFAR detector is discussed in CFAR detectors proved to provide good performance in
detail in Section 4. Section 5 provides the FPGA-based the presence of interference. The clutter power estimate
realisation and simulation results. FPGA prototyping results Z, in OS– CFAR detectors, is computed by sorting the
are discussed in Section 6. Finally, Section 7 presents observations in the reference window in ascending order and
concluding remarks and some directions for future research. setting
Z ¼ X(k) (2)
2 Background theory and
related work where X(k) is the kth ordered sample. The rank of the order
A typical CFAR processor as shown in Fig. 1 consists of a statistic to be used is determined in advance. It can be any
matched filter followed by an envelope detector and a value between 1 k N, and is typically chosen to
non-coherent integrator. The output samples of the maximise detection performance. The OS – CFAR detector
has a small additional detection loss over the CA –CFAR
detector in homogeneous backgrounds, but can resolve
closely spaced interferences. However, it requires a longer
processing time than the CA– CFAR detector.
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Techniques based on the automatic censoring of unwanted to represent the largest rank possible, since CFAR loss would
cells have been proposed in the literature [2]. The ACCA– increase with the decrease in the value of j. In particular, the
ODV CFAR detector selects dynamically, by doing numerical results obtained in [5] show that the appropriate
successive hypothesis tests, a suitable set of ranked reference value of j, when detection is performed in homogeneous
window cells to estimate the unknown background level and environments, is j ¼ N. However, in the presence of k
set the adaptive threshold accordingly. The advantage interfering targets in the reference window, the value of j is
associated with this detector is that it neither requires any best selected such that j ¼ N 2 k. Therefore the main
prior information about the clutter parameters nor does it objective of the ACCA– ODV censoring algorithms is to
require the number of interfering targets. The effectiveness of have the task of determining the best value of k. Once the
the ACCA–ODV algorithm has been extensively studied in number of interfering targets is determined automatically,
[4] by computing the probability of censoring and the the output of the test cell X0 is then compared with the
probability of detection in different background environments. adaptive threshold Tk according to
H1
3 ACCA–ODV detection algorithm .
X0 Tk (5)
The square law detected range samples, fXi: i ¼ 0,
,
1, . . . , Ng, are sent serially into a tapped delay line, as H0
shown in Fig. 2. X0 is the test cell. The remaining N cells
surrounding the test cell are the auxiliary cells that are used
to construct the CFAR procedure. These auxiliary cells are where the adaptive threshold Tk (or equivalently the
ranked in ascending order according to their magnitudes to parameter tk) is selected so that the design Pfa is achieved.
yield Hypothesis H1 denotes the presence of a target in the test
cell, whereas H0 is the null hypothesis (i.e. no target is
X (1) X (2) X (p) X (N ) (3) present).
The test cell X0 is to be compared with the threshold Tk , to To determine the number of interfering targets k, the ODV
decide whether a target is present or not. Selecting statistic V0 is first compared with the ODV threshold S0 ,
which is selected so that a low probability of false censoring
X
j Pfc is maintained. The statistic V0 is defined as follows
Tk ¼ tk X (i) (4)
i¼1
mp þ X (N )2
leads to a CFAR processor in Rayleigh clutter. The threshold V0 ¼ (6)
Tk is parameterised by the variable tk . The subscript j is taken (sp þ X (N ))2
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Table 1 ODV thresholds in a homogeneous background with exponential probability density function (pdf)
(N, p) Pfc Sk
S0 S1 S2 S3 S4 S5 S6 S7
22
(16, 12) 10 0.356 0.246 0.199 0.173 — — — —
5 1023 0.389 0.267 0.213 0.183 — — — —
23
10 0.456 0.320 0.246 0.206 — — — —
(24, 16) 1022 0.332 0.235 0.189 0.162 0.143 0.131 0.122 0.117
23
5 10 0.362 0.255 0.204 0.173 0.152 0.138 0.129 0.122
1023 0.422 0.305 0.240 0.200 0.174 0.155 0.142 0.133
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L ¼ N þ G þ 1 cells (14)
The two N/2 cell reference groups are merged into one N cell
output group and sent to the sorting circuit for arranging the
samples in ascending order (the highest values are on the
right side). The sorting circuit is the most sophisticated
part as far as the circuit size and processing time are
concerned in this design. This is because the sorting must
be done sequentially for the N cells. After sorting is done,
the subsequent operations are explained in detail in Fig. 5,
where a certain number of data cells at the array edges are
subjected to an automatic censoring mechanism from one
side (right side in our case). The censoring operation is
very beneficial in minimising the estimation error of the
background, and is performed according to the background
configuration. The basic idea of this circuit is to consider p
of the lowest cells ( p ¼ 12 in our case) to represent the
initial estimation of the background level and then use this
estimate to compute the number of interfering targets k.
Background noise is estimated by first computing the Figure 4 Flow chart of ACCA– ODV CFAR detector
values of sp and mp . Once computed, they can be used
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Tclk
Ttotal ¼ s (15)
Fmax
(5 þ N )
Ttotal ¼ s (16)
Fmax
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Binary decision Represented No. of censored cells Mask code Threshold factor
code
d3 d2 d1 d0 K2 K1 K0 k M3 M2 M1 M0 tk
0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 ¼ (341)10
0 1 0 0 1 1 1 1 1 0 0 1 1 0 1 1 0 1 1 1 ¼ (439)10
0 1 1 0 1 0 2 1 1 0 0 1 0 0 0 1 0 0 1 0 1 ¼ (549)10
0 1 1 1 0 1 1 3 1 0 0 0 1 0 1 0 1 0 1 1 0 0 ¼ (684)10
1 1 1 1 1 0 0 4 0 0 0 0 1 1 0 1 0 1 1 0 0 0 ¼ (856)10
, do not care
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Table 3 Mask lookup table comparator circuit, 2:1 MUX and output flip flops. The
main task is to compare the two input elements: if the first
No. of Masking code Accepted cells element is greater than the second, the two elements are
censored cell swapped, and no change is performed otherwise. This
k M3 M2 M1 M0 X13 X14 X15 X16 operation is repeated for each pair of adjacent elements till
the end of the entire data array. The process can be
0 1 1 1 1 X13 X14 X15 X16 performed simultaneously for every adjacent pairs, so as to
1 1 1 1 0 X13 X14 X15 0 speed up the processing time through what is called parallel
bubble sorting.
2 1 1 0 0 X13 X14 0 0
3 1 0 0 0 X13 0 0 0 The next step in this module is to repeat the operation
described above on the array results obtained from the
4 0 0 0 0 0 0 0 0 previous sorted data in a serial manner and in synchronised
clocked stages till the end. Note that if the number of
elements to be sorted is N, the number of the stages will be
N; hence, the total number of the compare– swap circuits
4.2 Architecture of sorting module will be given by
Sorting is the operation that puts elements of a list in a certain
order. This operation plays an important role since it
consumes long computation time and constitutes a bottleneck No: of units ¼ N (N 1)=2 (17)
in the field of real-time signal processing applications [9].
The sorting algorithm can work in ascending order (data
elements are sorted from the smallest to the largest) or in
descending order (data elements are sorted from the largest to
the smallest). Since the processing time is critical, the decision 5 FPGA realisation and simulation
of choosing the highest speed and most efficient method of
The ACCA– ODV CFAR detector has been designed,
data sorting is of great interest. In this work, the bubble
synthesised and simulated using Altera Quartus II software
sorting algorithm is adopted. It is one of the best sorting
[12] targeting Stratix II FPGA. It provides a complete
algorithms that combine high speed and simplicity for the
design environment for designing system-on-a-
applications that involve small number of elements [10, 11].
programmable-chip. It offers a very rich library of
parameterised modules that can be utilised to construct
The bubble sort algorithm compares every two elements, different processing units used in this design. The designed
and then decides which one is greater. As shown in Fig. 8, CFAR detector is modular, which enables the designer to
each compare– swap switch circuit is simply composed of a test the various modules individually.
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For illustration, a shift register consisting of 19 cells (each In the absence of other hardware implementations,
cell of 16 bit), 16 reference cells and 2 guard cells are information on the extent of speedup obtained by our
considered. Hence, the total number of the clock cycles hardware implementation has been gathered by implementing
Tclk required is 21, the number of stages for the sorting the ACCA–ODV algorithm in software. The full
circuit is 16 and total number of compare– swap switch implementation of the ACCA–ODV CFAR detector was
circuits is 120. carried out in C language targeted to general purpose PC
(3.4 GHz Pentium 4 processor with on-board RAM of 1 GB
For simulation, two memories and their associated read/ running Microsoft Windows XP Professional). For the same
write control signals and address generation unit are built (N, p) configuration, the processing time on this platform is
inside the FPGA device as shown in the simplified block 23 ms. The performance improvement of the proposed
diagram of Fig. 9. A 256 16 ROM is used, which ACCA–ODV CFAR hardware architecture is 110 times
receives the data serially, stores it and is then read by the than the software implementation of the same algorithm.
rest of the hardware. The resulting flags decided by the
thresholding modules are stored in 256 1 RAM.
Table 4 summarises the FPGA hardware resource
utilisation of different modules and the proposed CFAR 6 FPGA prototyping
detector. The proposed ACCA– ODV CFAR detector, including the
associated input data ROM and the output target
The FPGA implementation result shows that the detection RAM, have been implemented on Stratix II
processor can achieve a maximum operating frequency of FPGA chip. The EP2S60 digital signal processing
109.37 MHz, which is very close to the clock frequency of (DSP) development kit [13] built around Stratix II device
the prototyping board (100 MHz). This implies that the has been selected for prototyping the proposed CFAR
total processing time Ttotal (for N ¼ 16) to perform a single detector because of its low cost, configurability and the fact
run is 0.21 ms that the operating master clock is 100 MHz, which is very
close to the maximum frequency determined by the
Ttotal ¼ 21=100 ¼ 0:21 ms compiler (109.37 MHz). This kit is a development
platform for high performance DSP designs. It is normally
employed to design, verify and evaluate systems prior to
final stand-alone single chip implementation.
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Authorized licensed use limited to: St. Xavier's Catholic College of Engineering. Downloaded on March 12, 2009 at 00:26 from IEEE Xplore. Restrictions apply.