IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO.

8, AUGUST 2013 3723

A Hybrid Multilevel Inverter System Based
on Dodecagonal Space Vectors for
Medium Voltage IM Drives
Jaison Mathew, Member, IEEE, K. Mathew, Member, IEEE, Najath Abdul Azeez, P. P. Rajeevan,
and K. Gopakumar, Fellow, IEEE
AbstractDodecagonal (12-sided) space vector pulsewidth mod-
ulation (PWM) schemes are characterized by the complete absence
of (6n 1)th-order harmonics (for odd n) in the phase voltages,
within the linear modulation range and beyond, including over-
modulation. This paper presents a new topology suitable for the
realization of such multilevel inverter schemes for induction motor
(IM) drives, by cascading two-level inverters with ying-capacitor-
inverter fed oating H-bridge cells. Now, any standard IM may be
used to get the dodecagonal operation which hitherto was possi-
ble only with open-end winding IM. To minimize the current total
harmonic distortion (THD), a strategy for synchronous PWM is
also proposed. It is shown that the proposed method is capable of
obtaining better THDgures, compared to conventional dodecago-
nal schemes. The topology and the PWM strategy are validated
through analysis and subsequently veried experimentally.
Index TermsDodecagonal space vector, ying capacitor
(FC), induction motor drive, multilevel inverters, space vector
modulation, total harmonic distortion (THD).
I. INTRODUCTION
M
ULTILEVEL inverters are often considered for high-
power applications as the power stage may be realized
using devices rated at lower voltages. As the step waveform
produced by multilevel operation is closer to a sinusoid, the
harmonic distortion in the load current is quite low. For a given
current distortion, a higher number of voltage levels will permit
lower switching frequencies. The additional benets of multi-
level inverters are lower common-mode voltages and reduced
EMI. Grid-connected applications such as reactive power com-
pensation and photovoltaic interconnections also benet, as the
lter requirement is less stringent, due to the improved voltage
quality. With all the above advantages, multilevel inverters are
gaining popularity in diverse applications [1]. The most popular
multilevel inverter families are the diode-clamped (NPC), ying
capacitor (FC), and the cascaded H-bridge topologies [1][3]. In
addition to these basic topologies, many interesting congura-
tions have been reported in the literature over the years [4][8].
The space vector structures due to most of these multilevel
Manuscript received August 21, 2012; revised October 5, 2012; accepted
November 4, 2012. Date of current version January 18, 2013. Recommended
for publication by Associate Editor P. Barbosa.
The authors are with the Department of Electronic Systems Engineer-
ing, Indian Institute of Science, Bangalore 560012, India (e-mail: jaison@
ieee.org; prajeev@cedt.iisc.ernet.in; kmathewmace@gmail.com; najath@
gmail.com; kgopa@cedt.iisc.ernet.in).
Digital Object Identier 10.1109/TPEL.2012.2227978
inverter topologies are hexagonal in shape, and for multilevel
operation, it is subdivided into many triangular regions. Even
though the harmonic performance of these multilevel invert-
ers is better than its two-level counterpart, it is found that for
low-switching frequencies or during overmodulation, there are
substantial amounts of fth and seventh harmonic components
in the load current, resulting in losses associated with current
and torque ripples. Further, in these cases, the current-control
schemes become less accurate and additional control schemes
may be necessary to get satisfactory performance [9]. To take
care of this issue, a dodecagonal space vector structure was pro-
posed in [10], which eliminates all (6n 1)th-order harmonics
(for odd n) for the entire modulation range. Multilevel invert-
ers based on dodecagonal space vector diagram were presented
in [11] and [12] which relied upon open-end winding induction
motors as the load because the open-end winding schemes al-
lowed the required phase voltage levels to be generated quite
easily by feeding it from both ends of the windings. The topol-
ogy reported in [11] used the diode clamped multilevel inverter
and that in [12] used FC-based inverters for the generation of
dodecagonal space vectors. The proposed topology utilizes cas-
cade connection of FCs and oating H-bridge cells in combina-
tion with basic two-level inverters to generate the same phase
voltage levels as that in [11] and [12] for the generation of do-
decagonal space vectors, thus allowing any standard induction
motor as the load. The disadvantage of open-end winding in-
duction motor is that six wires are to be drawn from the inverter
terminals to the motor, which is not possible in certain applica-
tions; the voltage reections in the wires are excessive. Of the
methods used for the speed control of induction motors, namely
sine-triangle pulsewidth modulation (PWM) and space vector
PWM(SVPWM), the latter that provides extra modulation range
is naturally preferred. The idea of injecting a common-mode
voltage in the reference phase voltages to enhance the modula-
tion range was introduced in [13]. Van der Broeck et al. [14]
discuss the concept of space vector modulation based on space
vector theory in detail. A simple method for space vector mod-
ulation for two-level inverters based on sampled amplitudes of
the reference voltages was proposed in [15]. The SVPWM tech-
nique illustrated in [12] discussed how the technique may be
extended to dodecagonal space vectors. It is a well-understood
fact that the way in which the PWM switching sequences are
applied has a signicant inuence on the harmonic performance
of the drive. However, this topic was not discussed in [12]. In
this paper, this aspect is also taken into account and the notion
0885-8993/$31.00 2012 IEEE
3724 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013
Fig. 1. (a) Proposed topology for the generation of multilevel dodecagonal space vectors and (b) multilevel dodecagonal space vector diagram used.
of harmonic ux trajectories and stator ux ripple proposed
in [16] and [17], respectively, are used to analyze the harmonic
performance of the various PWM switching patterns. Although
the PWM method used in this study is similar to that in [12], the
modication in the switching sequence in the PWM algorithm
yields signicant improvements in harmonic performance. The
proposed topology and PWM scheme are extensively simulated
and experimentally veried.
II. PROPOSED INVERTER TOPOLOGY
A. Description of the Topology and Space Vector Diagram
The proposed topology for nine-level (asymmetric) pole volt-
age generation is shown in Fig. 1(a). Each leg of the inverter
system consists of a six-level inverter cascaded with a oat-
ing capacitor H-bridge cell to achieve a nine-level inverter. The
six-level inverter in turn consists of a three-level FC inverter
stacked between two two-level inverters. The nominal voltage
of the capacitors in the FCcells (C
1
, C
2
, and C
3
) is 0.5 V
DC
and
that of the capacitors in the H-bridge cells (C
4
, C
5
, and C
6
) is
0.183 V
DC
, where V
DC
is the dc-link voltage of the system. The
switches in the two-level inverters are to be rated to block re-
verse voltage of 0.366 V
DC
. The switches in the FC inverter are
to be rated for 0.5 V
DC
and that in the oating H-bridge cells are
to be rated for 0.183 V
DC
. The pole-voltage levels and the corre-
sponding switching combinations for a phase leg are given in Ta-
ble I. An attractive feature of this topology would be that faulty
H-bridge cells maybe effectively bypassed to give a six-level
inverter. i.e., with all the H-bridge cells bypassed, we can still
have the pole voltage levels 0, 0.366 V
DC
, 0.5 V
DC
, 0.866 V
DC
,
V
DC
, and 1.366 V
DC
(six levels). With these voltage levels, we
can generate three dodecagons instead of six dodecagons and
have dodecagonal space-vector-based multilevel operation. But
the PWM algorithm must be modied to take this eventuality.
Likewise, if there are faults elsewhere in the converter circuit,
the converter cannot generate dodecagonal space-vector-based
multilevel operation, but hexagonal-based multilevel operation
is possible with much reduced power outputs. Both capacitor
voltages in a leg are controlled by utilizing the switching state
redundancies in a PWM cycle, as explained later. Of the set of
all space vectors given by (1), those vectors whose tips lie on
the vertices of 12-sided polygons (dodecagons) are selected to
obtain the space vector diagram shown in Fig. 1(b)
V
R
= V
ao
+ V
bo
e
j120

+ V
co
e
j240

(1)
where V
ao
, V
bo
, and V
co
represent the pole voltages of the sys-
tem.
As mentioned earlier, the PWM based on dodecagonal space
vectors gives better harmonic performance when the switch-
ing frequency is low or the operation is in the overmodulation
region. Compared to [11] and [12], the outer regions in the
space vector diagram (corresponding to 35.750 Hz) in this
study is subdivided into different triangular regions such that
in a carrier period, vectors nearest to the reference vector are
applied at all times. The asymmetrical dc-link voltages required
for the topology can be easily obtained from the power supply
scheme shown in Fig. 2, where the particular type of transformer
winding connections will improve the source side power factor
also [11], [22]. But at low speeds of operation, the improvement
in power factor is not signicant.
B. Generation of Different Voltage Levels and the Algorithm
for Capacitor Voltage Balancing
As mentioned earlier, all the capacitor voltages in a phase
leg may be controlled using switching state redundancies. De-
pending on the direction of load current and the voltage in each
capacitor, the switches in a phase leg are operated to charge the
capacitors to proper voltages so that the required pole-voltage
levels are obtained [12], [20], [21]. Fig. 3 shows how a pole-
voltage of 0.683 V
DC
may be obtained using different switching
combinations. Table I gives the switching combinations required
to keep the capacitor voltage at the correct level for phase A
while providing the required pole voltages. The switching states
have been selected so as to give the lowest voltage stress across
the devices also. For example, for S
2
= 0, S
1
state can very
well be a dont care state. But when we look at the reverse
voltage for the device S
2
, we can see that the switch state S
1
=0
MATHEW et al.: HYBRID MULTILEVEL INVERTER SYSTEM BASED ON DODECAGONAL SPACE VECTORS 3725
TABLE I
AVAILABLE POLE VOLTAGES AND THE REQUIRED SWITCHING COMBINATION FOR PHASE A
Pole
voltage
Levels
Current
Directio
n
VC1 VC4 S1 S2 S3 S4 S5 S6
0.183V
DC
+ NA more 0 0 0 0 0 1
+ NA less 0 0 0 1 1 0
- NA more 0 0 0 1 1 0
- NA less 0 0 0 0 0 1
0.366V
DC
unaffected 0 0 0 1 0 0
0.5VDC
+ more NA 0 0 1 0 0 0
+ less NA 0 1 0 1 0 0
- more NA 0 1 0 1 0 0
- less NA 0 0 1 0 0 0
0.683V
DC
+ more more 0 0 1 0 0 1
+ more less 0 0 1 1 1 0
+ less more 0 1 0 1 0 1
+ less less 1 1 0 1 1 0
- more more 1 1 0 1 1 0
- more less 0 1 0 1 0 1
- less more 0 0 1 1 1 0
- less less 0 0 1 0 0 1
0.866V
DC
+ more NA 0 0 1 1 0 0
+ less NA 1 1 0 1 0 0
- more NA 1 1 0 1 0 0
- less NA 0 0 1 1 0 0
1VDC unaffected 0 1 1 1 0 0
1.183V
DC
+ NA more 0 1 1 1 0 1
+ NA less 1 1 1 1 1 0
- NA more 1 1 1 1 1 0
- NA less 0 1 1 1 0 1
1.366V
DC
unaffected 1 1 1 1 0 0
0
unaffected 0 0 0 0 0 0
Fig. 2. Scheme for the generation of the asymmetrical dc-link voltages.
(S

1
= 1) will yield lower reverse voltage across the switch S
2
.
As the capacitor voltage control occurs once in every sampling
period and the capacitor voltage is controlled using switching
state redundancies, stiff voltage control can be achieved in all
modulation ranges irrespective of the load power factor, pro-
Fig. 3. Four different ways of generating the pole voltage level 0.683 V
DC
(V
c1
= 0.5 V
DC
, V
c4
= 0.183 V
DC
).
vided the switching frequency is sufciently high for the chosen
capacitor values.
III. SVPWM FOR THE TOPOLOGY
A. PWM Timing Computation From the Sampled Amplitude of
the Reference Voltages
A method based on the sampled amplitudes of the reference
voltages is used in this paper to eliminate the complex ma-
trix manipulations and lookup table operations required in con-
ventional SVPWM methods [14]. Although fully carrier-based
3726 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013
Fig. 4. (a) Hexagonal sectors S
1
S
6
and the locus of the voltage reference
vector V
ref
. (b) Derivation of the hexagonal sector timings from the reference
voltage waveform.
implementations of space vector modulation are in use [15],
[18], these approaches do not allow choice of the switching
combination. The choice of switching sequence in a subcarrier
cycle has a major role in the total harmonic distortion (THD)
performance of the system [19]. The method used in this pa-
per offers the exibility of choosing the switching sequences as
desired, while also maintaining the simplicity of carrier-based
space vector methods. The analysis of the inuence of switch-
ing sequences on the harmonic performance of the system is
provided in the next section. It is clear that the locus of the ref-
erence voltage space vector V
ref
in the space vector diagram is
decided by the speed requirement of the motor [see Fig. 4(a)].
The three-phase reference voltages corresponding to this space
vector trajectory may be obtained using the transformation
_

_
V
a
V
b
V
c
_

_ =
_

_
2/3
1/3
1/3
0
1/

3
1/

3
_

_
_
V

_
(2)
where V

and V

are obtained by projection of the reference

space vector on to the - and -axes, respectively. Consider
the resulting three-phase waveform as shown in Fig. 4(b). The
hexagonal sector in which the reference vector is located may
be identied using the sampled amplitudes of the reference volt-
ages. For example, if V
a
> V
b
> V
c
, then the sector is identied
as sector-I (S
1
), if V
b
> V
c
> V
a
, then sector-II and so on. Fur-
ther, the timings of the active vectors T
1Hex
and T
2Hex
for a
hexagonal sector in conventional two-level space vector mod-
ulation may also be computed from the sampled amplitudes of
the reference voltages.
For odd numbered sectors [see Fig. 4(a)]
_
T
1Hex
T
2Hex
_
=
T
s
|V
1Hex
|
_
V
max
V
mid
V
mid
V
min
_
. (3)
For even numbered sectors
_
T
1Hex
T
2Hex
_
=
T
s
|V
1Hex
|
_
V
mid
V
min
V
max
V
mid
_
(4)
where T
s
denotes the sampling period, and V
max
, V
mid
, and
V
min
represent the maximum, mid, and minimum amplitudes
of the reference voltage, respectively. |V
1Hex
| is the radius of
the outermost hexagonal pattern of the space vector diagram
which is the same as the dc-link voltage (1.366 V
DC
). If the
reference vector is inside a particular hexagon sector, say the rst
Fig. 5. Hexagonal sector S
1
and its rst 30

region, shown as enclosed within

the vectors V
1Dod
and V
2Dod
.
sector S
1
, then it can be further inferred that for T
1Hex
> T
2Hex
,
the reference vector is inside the rst 30

region (dodecagonal
sector) of the hexagon sector. Else, it will be in the second
half of the hexagon sector. Fig. 5 shows the rst 30

region
of the hexagonal sector S
1
enclosed within the vectors V
1Dod
and V
2Dod
, which are ctitious vectors having the same vector
length as V
1Hex
. The respective timings T
1Dod
and T
2Dod
of the
vectors V
1Dod
and V
2Dod
can be obtained by equating the real
and imaginary parts of the following equation:
V
ref
T
s
= ( |V
1Hex
|0) T
1Hex
+ ( |V
2Hex
|60) T
2Hex
= (|V
1Dod
|0) T
1Dod
+ (|V
2Dod
|30) T
2Dod
(5)
Now, for multilevel operation, the space vector diagram is par-
titioned to many triangular regions as shown in Fig. 1(b). From
the above discussion, it may be noted that the computation of
the hexagonal sector timing from the sampled amplitudes of the
reference voltage is quite similar to that of carrier-based tech-
niques. But the PWM timing required for each triangle that falls
in a 15

region to realize the reference vector in an average sense

is computed based on vector approach. i.e., the magnitude and
angle of the vectors (which we already know from the vector
locations) making up a triangle is used to compute the required
vector switching timings. For example, if the reference vector
is inside a triangle (see Fig. 5), it is a straightforward task to get
the timings from the already computed vector timing using the
concept of voltsecond balance as used in (5) and as detailed
in [12]. After such mapping of the hexagonal vector timings
into the inner triangles, the triangle which gives positive values
for its vector timings can be identied as the only triangle, the
vectors of which can realize the reference vector in an average
manner. Since the algorithm requires only a few scaling opera-
tions, summations, and comparisons, the method is much faster
compared to conventional multilevel space vector modulation
algorithms. A more detailed description of the PWM method
may be found in [12].
B. Harmonic Analysis Using the Concept of Stator Flux Ripple
This section illustrates the analytical method used to compare
the PWM switching strategies used in connection with the pro-
posed topology. Based on this analysis, it is shown in the next
section that a variation in the switching sequence in a PWMcar-
rier period could yield improvements in the THDperformance in
certain frequency ranges. In fact, the PWM modulation scheme
along with the proposed switching strategy can be used in the
MATHEW et al.: HYBRID MULTILEVEL INVERTER SYSTEM BASED ON DODECAGONAL SPACE VECTORS 3727
Fig. 6. (a) Voltage vectors V
1
, V
2
, V
3
, the reference vector V
ref
, and the
corresponding error vectors. (b) Harmonic ux trajectories in a half-carrier
cycle for the position of the reference voltage V
ref
(dotted lines: when the
sequence 3123 is used, solid lines: when the sequence 1231 is used).
case of other multilevel inverters also to get better harmonic
performance.
As the reference voltage vector is realized using the available
voltage vectors only in an average sense, there exists an in-
stantaneous error between the reference and the applied voltage
vectors, which results in a ripple in addition to the fundamental
voltage. The load seen by harmonic voltages is largely the leak-
age inductance of the motor, as the slip tends to be much higher
at these frequencies. The line current ripple is, therefore, pro-
portional to the integral of the voltage ripple, which was termed
as stator ux ripple in [17]. Various synchronous PWM tech-
niques may be compared on basis of the stator ux ripple. The
analysis presented here also uses the denition of harmonic ux
trajectory (HFT) from [16], in which the harmonic ux (stator
ux ripple) in the Nth carrier cycle is dened as

=
(N+1)T
s
_
NT
s
(V
k
V
ref
) dt (6)
where T
s
denotes the switching interval, V
ref
the reference vec-
tor, and V
k
the space vector used.
While a per-carrier cycle analysis of the HFT provides in-
formation regarding the peak and local stresses on the power
devices, a per-fundamental cycle analysis of the same is re-
quired for the computation of current ripple, torque ripple, and
associated losses [16]. Consider the case when the reference
vector is located inside the triangular region formed by vectors
25, 13, and 26 in Fig. 1(b), as shown in Fig. 6(a).The voltage
errors are

V
1
= V
1
V
ref
(7)

V
2
= V
2
V
ref
(8)

V
3
= V
3
V
ref
. (9)
Fig. 6(b) shows the HFTs for two PWM sequences for a given
half-carrier cycle. Since the HFT for the second-half-carrier
cycle shall be symmetric to that for the rst half, it is sufcient
to analyze a single half-carrier cycle. The RMS value of the
stator ux ripple

(where

=

+j

) over a half-carrier
cycle may be easily computed by its resolution into alpha and
beta components, as shown in Figs. 6(b) and 7. The ux ripple
values for the conventional SVPWM sequence 3-1-2-3, where
1, 2, and 3 represent vectors V
1
, V
2
, and V
3
, respectively, when
Fig. 7. Decomposition of ux ripple in to their alpha and beta components
when the sequence 3123 is used.
different voltage vectors applied are

1
=

V
1
T
1
= |

V
1
| cos(

V
1
)T
1
(10)

2
=

V
2
T
2
= |

V
2
| cos(

V
2
)T
2
(11)

3
=

V
3
T
3
2
= |

V
3
| cos(

V
3
)
T
3
2
(12)

1
=

V
1
T
1
= |

V
1
| sin(

V
1
)T
1
(13)

2
=

V
2
T
2
= |

V
2
| sin(

V
2
)T
2
(14)

3
=

V
3
T
3
2
= |

V
3
| sin(

V
3
)
T
3
2
. (15)
The timings T
1
, T
2
, and T
3
, correspond to the vectors V
1
, V
2
,
and V
3
. It may be noted that the rst and last vectors are applied
for equal time duration in a half-carrier cycle. Fig. 7 illustrates
the development of and components of the stator ux ripple
for a half-carrier cycle, where the magnitudes Q
a
through Q
f
are representative values of the ripple ux for the switching
sequence and may be written as
Q
a
=

3
, Q
b
=

3
+

1
, Q
c
=

3
+

1
+

2
(16)
Q
d
=

3
, Q
e
=

3
+

1
, Q
f
=

3
+

1
+

2
. (17)
The -axis and -axis ux ripples that are piecewise linear
functions of time when squared become parabolic, and the area
under these parabolic sections is to be evaluated to get their
mean square values. Thus
(

)
2
=
1
3T
s
_

_
Q
2
a
T
3
2
+ (Q
2
a
+ Q
a
Q
b
+ Q
2
b
)T
1
+(Q
2
b
+ Q
b
Q
c
+ Q
2
c
)T
2
+ Q
2
c
T
3
2
_

_ (18)
(

)
2
=
1
3T
s
_

_
Q
2
d
T
3
2
+ (Q
2
d
+ Q
d
Q
e
+ Q
2
e
)T
1
+(Q
2
e
+ Q
e
Q
f
+ Q
2
f
)T
2
+ Q
2
f
T
3
2
_

_. (19)
3728 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013
Therefore
(

RMS
)
2
=
1
T
s
T
s
_
0
(

)
2
dt (20)
(

RMS
)
2
=
1
T
s
T
s
_
0
(

)
2
dt. (21)
The per-carrier cycle RMS value of the harmonic ux may be
then calculated as

RMS
=
_
(

RMS
)
2
+ (

RMS
)
2
. (22)
Due to the 12-fold symmetry, the per-fundamental cycle RMS
harmonic ux for the dodecagonal case may be calculated as

F,RMS
=

_
1

/
6
/6
_
0
(

RMS
)
2
d (23)
where d corresponds to the angular movement of the reference
vector in the space vector diagram. The per-fundamental cycle
RMS value of harmonic ux, usually represented in per unit, is
termed as the harmonic distortion factor (HDF):
HDF =

F,RMS

1
(24)
where

1
=
V
ref
2f
1
(25)
where f
1
is the fundamental frequency of operation. Also, as
the current ripple is proportional to the stator ux ripple, HDF
is an equivalent to the THD of the no-load current I
THD
(26),
and is hence a measure of the line current distortion [17]
I
THD
=
_

n=1
I
2
n
RMS
I
1RMS
=
_
I
2
RMS
I
2
1RMS
I
1RMS
(26)
where I
1RMS
is the rms value of the rst harmonic component
and I
nRMS
that of the nth harmonic.
C. Proposed Variation in the PWM Switching Strategy
In carrier-based PWM schemes, the freedom of choosing the
PWM switching combinations is limited. For example, in pure
carrier-based schemes, for every half-carrier cycle, the sequence
commences with a pivot vector followed by two active vectors
and a pivot vector. In order to improve the harmonic perfor-
mance, the vector nearest to the reference may be applied as
the rst and the last vector for the PWM sequence. A carrier-
based scheme [18] for a ve-level inverter incorporates this idea
by addition of suitable dc offsets to the modulating voltage.
However, the offset computation for different ranges of modu-
lation and the limitations in selecting the switching sequences
make the practical realization of this scheme difcult. This pa-
per presents a scheme where one has the opportunity to select
the switching sequence in such a way that the vector nearest to
the reference is applied as the rst and last switching vectors
Fig. 8. Four locations of the reference space vector in a triangular region.
TABLE II
PER-CARRIER CYCLE HARMONIC FLUX RIPPLE CORRESPONDING TO
DIFFERENT POSITIONS OF THE REFERENCE VOLTAGE
Location Vref
~
RMS

( volt-sec) p.u.
Proposed PWM
sequence
Conventional
SVPWM sequence
a 1.1<2 1.813710-5 2.230410-5
b 0.9202<2.5 8.5510-6 8.5510-6
c 1.03<12.5 1.295110-5 1.358910-5
d 1.0245<7.5 2.565810-5 2.929110-5
for each half-carrier cycle. The information regarding the near-
est vector is obtained easily, as the PWM timings are already
available from the sampled amplitudes of the reference voltage
and the vector having the largest PWM time value can be taken
as the nearest vector. The effectiveness of the PWM strategy is
illustrated by considering four different locations of the refer-
ence voltage in a triangular region in the space vector diagram,
as shown in Fig. 8. The per-carrier cycle harmonic RMS ux is
computed for: 1) proposed PWM sequence, in which the vector
nearest to the reference is used as the rst and last switching
vectors, with the vector-timing sequence T
3/2
-T
1
T
2
T
3/2
where T
3
represents the time corresponding to the nearest vec-
tor and T
1
and T
2
correspond to that of active vectors; and 2)
conventional SVPWM sequence, where the rst and last vec-
tors in the switching sequence need not be the nearest vector,
with the same timing sequence T
3/2
-T
1
T
2
T
3/2
where T
3
is that of a pivot vector. In both cases, the rst and last vec-
tors are switched for the same time duration in order to get the
best harmonic performance [18], [19]. From Table II, it is clear
that the proposed PWM sequence gives better harmonic perfor-
mance compared to conventional SVPWM sequence for all the
reference vector locations shown in Fig. 8.
Throughout the modulation ranges, synchronous PWM was
used for the analysis and experimentation. In the frequency
range 4048.85 Hz, the number of samples per cycle is taken
as 24. In the frequency range 2540 Hz, it is taken as 36, and
in the frequency range 1525 Hz, the number of samples is 48.
Below 15 Hz, the number of samples per cycle is chosen as 72.
The per-fundamental cycle RMS stator ux ripple is analyti-
cally computed for different frequencies from 25 Hz until the
end of linear modulation (48.85 Hz) [12] and a graph showing
HDF against frequency is plotted, as shown in Fig. 9. Curve
1 represents the PWM scheme used for the dodecagonal space
vector diagramin [11] and [12] where the vector-sequence 3-1-2
(T
3
T
1
T
2
) was used. Curve 2 represents the conventional
MATHEW et al.: HYBRID MULTILEVEL INVERTER SYSTEM BASED ON DODECAGONAL SPACE VECTORS 3729
Fig. 9. Comparison of different PWM strategies for dodecagonal PWM
operation.
Fig. 10. Functional block diagram of the control scheme.
SVPWM sequence 3-1-2-3 (T
3
/2-T
1
T
2
T
3
/2). Curve 3 is
the proposed PWM scheme where the vector nearest to the ref-
erence vector, calculated in every carrier cycle, is applied as the
rst and the last vector. At all frequencies, the harmonic distor-
tion of curve 1 is higher than those of curves 2 and 3. Its perfor-
mance is considerably poor in the high modulation range. Curve
3 indicates better harmonic performance compared to curves and
2. The analysis in this section indicates that signicant improve-
ment in THD may be achieved with the proposed PWM scheme
for dodecagonal space-vector-based inverter drives.
IV. IMPLEMENTATION ASPECTS AND EXPERIMENTAL
VERIFICATION
A. Implementation Aspects
The control scheme was implemented using the TMS
320F2812 processor running at a clock frequency 150 MHz
as the main controller. Since the code was written using C pro-
gramming, it took 10 s for the PWMtiming computation alone.
The capacitor charge control algorithm, ADC, and other over-
heads took another 10 s. Fig. 10 shows the functional diagram
of the implementation scheme. The reference speed is sensed,
rate limited, and fed to the v/f block inside the DSP to compute
the modulation depth required as per the reference speed. The
sector identication and the PWM timing computation are then
done as explained in Section III-A. Finally, the PWM timings
are output by the PWM modules in the DSP. The information
regarding the vector nearest to the reference vector is also output
by the DSP. The DSP is also used to detect the direction of the
motor currents that are sensed by hall sensors. Depending on
Fig. 11. Voltage and current waveforms of A phase at 20-Hz operation us-
ing the proposed PWM scheme: x-axis: 10 ms/div, y-axis: 1) phase voltage,
100 V/div; 2) phase current, 2 A/div; 3) ripple voltage of capacitor C
1
, 5 V/div;
4) ripple voltage of capacitor C
4
, 2 V/div.
Fig. 12. Voltage and current waveforms of A phase at 20-Hz operation using
the PWM switching scheme (3-1-2) in [11] and [12]: x-axis: 10 ms/div, y-axis:
1) phase voltage, 100 V/div; 2) pole voltage V
AO
, 100 V/div; 3) phase current,
2 A/div.
the current direction and the capacitor voltages, the DSP outputs
the information on whether a capacitor is to be charged or dis-
charged. A Spartan-3 XC3S200 eld-programmable gate array
(FPGA) uses the PWMsignals to decode the timing information
required for the PWMsequencing. Using the information on the
triangle number, the nearest vector, and the charging status of
the capacitors, the FPGA outputs the gating pulses to gener-
ate the proper vectors while keeping the capacitors charged in
the correct direction. Dead time control for the switches is also
realized using the FPGA.
B. Experimental Verication
A four-pole, 3.7-kW, 50-Hz, 415-V three-phase induction
motor with the following parameters was used for the ex-
periment: stator resistance R
s
: 2.08 , rotor resistance R
r
:
4.19 , stator self-inductance L
s
: 0.28 H, rotor self-inductance
L
r
: 0.28 H, magnetizing inductance M: 0.272 H, moment of in-
ertia J: 0.1 kgm
2
. The insulated-gate bipolar transistor devices
of 75 A, 1200 V (Semikron make, SKM75GB12T4) and a dead
time of 1.25 s was provided to avoid shoot through problems.
Fig. 11 shows pole voltage, phase voltage, and phase current
waveforms at 20 Hz when using the proposed PWM scheme.
Fig. 12 shows the situation when the PWM sequence in [11]
and [12] (3-1-2) is used. Fig. 13 shows the results at 38 Hz
when the proposed scheme is used, while Fig. 14 shows the re-
sult when the conventional SVPWM sequence 3-1-2-3 is used.
Figs. 15 and 16 show the results for 48.85-Hz operation. It can
be seen that the proposed PWM scheme results in lower current
3730 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013
Fig. 13. Voltage and current waveforms of phase A at 38-Hz operation us-
ing the proposed PWM scheme: x-axis: 5 ms/div, y-axis: 1) phase voltage,
100 V/div; 2) pole voltage V
AO
, 100 V/div; 3) phase current, 2 A/div.
Fig. 14. Voltage and current waveforms of phase A at 38-Hz operation using
conventional SVPWM switching sequence (3-1-2-3): x-axis: 5 ms/div, y-axis:
1) phase voltage, 100 V/div; 2) pole voltage V
AO
, 100 V/div; 3) phase current,
2 A/div.
Fig. 15. Voltage and current waveforms of A phase at 48.85-Hz operation
using the proposed PWM scheme: x-axis: 5 ms/div, y-axis: 1) phase voltage,
100 V/div; 2) phase current, 2 A/div; 3) ripple voltage of capacitor C
1
, 5 V/div;
4) ripple voltage of capacitor C
4
, 2 V/div.
ripple. Fig. 17 shows the 24-step operation in the overmodula-
tion region. Fig. 18 shows the input phase voltage, input mains
current, motor phase voltage, and current when the motor op-
erates at 50 Hz. It can be noted that because of the transformer
connection scheme, the mains current drawn has a sinusoidal
nature. Fig. 19 shows the disabling and re-enabling of charge
control at times A and B, respectively. It may be noted that
the reasonably fast charge control action permits the capacitors
to regain the lost charge within a small period of time. Fig. 20
shows the acceleration prole of the motor as it is accelerated
from 10 to 50 Hz. It may be further noted that the capacitor
voltages remain well balanced even during the acceleration.
Fig. 16. Voltage and current waveforms of A phase at 48.85-Hz operation
using the PWM switching scheme (3-1-2) in [11] and [12]: x-axis: 5 ms/div,
y-axis: 1) phase voltage, 100 V/div; 2) pole voltage V
AO
, 100 V/div; 3) phase
current, 2 A/div.
Fig. 17. Voltage and current waveforms of A phase at 49.5-Hz operation:
x-axis: 5 ms/div, y-axis: 1) phase voltage, 200 V/div; 2) phase current, 2 A/div;
3) ripple voltage of capacitor C
1
, 5 V/div; 4) ripple voltage of capacitor C
4
,
2 V/div.
Fig. 18. Voltage and current waveforms of phase Aat 50-Hz operation: x-axis:
10 ms/div, y-axis: 1) phase voltage of the source, 100 V/div; 2) source current,
2 A/div; 3) motor phase voltage, 100 V/div; 4) motor phase current, 2 A/div.
Fig. 19. Disabling the charge control scheme of capacitors of A phase at
time A and reestablishing the charge control at B, 30-Hz operation. x-
axis: 0.5 s/div, y-axis: 1) phase voltage, 100 V/div; 2) capacitor voltage V
c1
,
100 V/div; 3) capacitor voltage V
c4
, 20 V/div; 4) phase current, 2 A/div.
MATHEW et al.: HYBRID MULTILEVEL INVERTER SYSTEM BASED ON DODECAGONAL SPACE VECTORS 3731
Fig. 20. Acceleration Prole of the motor when the motor is accelerated from
10 to 50 Hz. x-axis: 1 s/div, y-axis: 1) phase voltage, 100 V/div; 2) phase
current, 2 A/div; 3) voltage across the capacitor C
1
, 5 V/div; 4) voltage across
the capacitor C
4
, 2 V/div.
V. CONCLUSION
A novel hybrid multilevel inverter topology is proposed for
the generation of dodecagonal space vectors for a standard in-
duction motor, eliminating the need for an open-end winding
motor used in previously reported dodecagonal space-vector-
based drives. The FC voltages in the inverter are tightly con-
trolled using the switching state redundancies in a PWM cycle.
The conventional dodecagonal space vector diagramis modied
such that in a carrier cycle, only the vectors nearest to the refer-
ence are used. This results in improved current THD, especially
for higher modulation indices. Further improvement in THD
is obtained by adopting a special PWM switching sequence in
which the nearest out of the three switching vectors is used as
both the rst and last switching vectors in a carrier half-cycle.
The improvement in harmonic performance is discussed and
presented in comparison with previously reported schemes. The
proposed topology and the PWM scheme are experimentally
veried on a 5-hp induction motor drive.
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Jaison Mathew (S96M02) received the B.Tech.
degree in electrical engineering from the Rajiv
Gandhi Institute of Technology Kottayam, Kottayam,
India, in 1998, and the M.Tech. degree in power sys-
tems from the College of Engineering Trivandrum,
Trivandrum, India, in 2001. He is currently work-
ing toward the Ph.D. degree in the Department of
Electronic Systems Engineering, Indian institute of
Science, Bangalore, India.
He is a Faculty Member with the Department
of Electrical Engineering, Rajiv Gandhi Institute of
Technology. He was the secretary of IEEE IA/IE/PEL Joint Chapter of Kerala
section during 20092011. His research interests include power converters, mo-
tor drives, and power quality.
3732 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013
K. Mathew (S11M12) received the B.E. degree
in electronics and communication engineering from
K.V.G Engineering College, Mangalore, India, in
1994, and the M.Tech. degree in electronic design
from the Centre for Electronics Design and Technol-
ogy, Indian Institute of Science, Bangalore, India, in
2006, where he is currently working toward the Ph.D.
degree.
He is a Faculty Member with the Department of
Electronics Engineering, M.A College of Engineer-
ing, Kothamangalam, India. His research interests in-
clude embedded systems, power electronics, and electromechanical systems.
Najath Abdul Azeez received the B.Tech. degree
from the National Institute of Technology, Calicut,
India, in 2003, and the M.Tech. degree from the In-
dian Institute of Science, Bangalore, India, in 2008,
where he is currently working toward the Doctoral
degree in the Department of Electronic Systems En-
gineering (formerly Centre for Electronics Design
and Technology).
His research interests are in the areas of power
converters and drives.
P. P. Rajeevan received the B.Tech. degree in elec-
trical engineering from the University of Calicut,
Thenhipalam, India, and the M.E. degree in power
electronics from Bangalore University, Bangalore,
India. He is currently working toward the Ph.D. de-
gree at the Centre for Electronics Design and Tech-
nology, Indian Institute of Science, Bangalore.
His research interests include multilevel power
converters, drives, pulsewidth modulation tech-
niques, and power quality.
K. Gopakumar (M94SM96F11) received the
B.E., M.Sc. (Engg.), and Ph.D. degrees from the In-
dian Institute of Science, Bangalore, India, in 1980,
1984, and 1994, respectively.
He was with the Indian Space Research Organiza-
tion, Bangalore, from 1984 to 1987. He is currently
the Chairman and Professor in the Department of
Electronics System Engineering (formerly Center for
Electronics Design and Technology), Indian Institute
of Science. His research interests include pulsewidth
modulation converters and high power drives.
Dr. Gopakumar is a Fellow of the Institution of Electrical and Telecom-
munication Engineers India and Indian National Academy of Engineers. He
is currently an Associate Editor of the IEEE TRANSACTIONS ON INDUSTRIAL
ELECTRONICS.