ARM

Architecture, Programming and Development Tools

Lesson 1

ARM CPUs

"Microcontrollers....", Raj Kamal, from Pearson Education, 2005

Outline
ARM Processors Features of a RISC architecture ARM Family and ARM many variant architectures

"Microcontrollers....", Raj Kamal, from Pearson Education, 2005

Examples of Systems needing highperformance precise- computing

Image processing, Video games, Robotics and Adaptive control Mobile Devices
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ARM Applications in Mobile Systems

PDA

Multimedia Phone

Network Walkman

Pocket PC

Robot With Distributed Sensors

Vending Machine with Wireless Support

Pocket PC with VOIP

"Microcontrollers....", Raj Kamal, from Pearson Education, 2005

Mobile Device CPUs/MCUs CPUs ARM-7 and ARM-9 (More than 50% devices) CPUs PowerPC 750,ColdFire, TigerSHARC MCUs ST72x, LPC21xx,
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Embedded RISC Core ARM7TDMI (http://www.arm.com/news/5135.html)

ARM family of general-purpose 32-bit microprocessors offers high performance and very low MIPS/watt power consumption 32-bit RISC architecture

Design centers around and concentrate on simple instructions Smaller and simpler processor circuit, Simpler decoding subunit. Lower power more space for other performing units
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Outline..
ARM Processors Features of a RISC architecture ARM Family and ARM many variant architectures

"Microcontrollers....", Raj Kamal, from Pearson Education, 2005

RISC Features
Same Length instructions Single Cycle Execution Hardwired implementation of Instructions Large Register Set(s) Load and Store Architecture"Microcontrollers....", Raj Kamal, from Pearson Education, 2005 10

Internal bus

Fetch Decode
Execution

IR ID
Hardwired Circuits

Hardwired Implementation
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Outline
ARM Processors Features of a RISC architecture ARM family and ARM many variant architectures

"Microcontrollers....", Raj Kamal, from Pearson Education, 2005

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ARM CPUs optionsExtensive range of CPUs with third-party adaptation and application development tools

"Microcontrollers....", Raj Kamal, from Pearson Education, 2005

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ARM Many Variant Architectures

ARM Thumb (T) variants

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v1 ARM 1

v3 full 32bit addressing v2 ARM 2, v2as for both data and code -ARM 3, ARM250 ARM 6, ARM 7, v3 ARM 8 and
ARM variants

Amulet 1 v3M - ARM 6, ARM 7 and ARM 8 v4 StrongARM,

v4

ARM 9, VFP1- ARM10 for high floating-point performance

v5 - ARM10

Some variants Single-precision and double-precision floating point arithmetic) on typical graphics and DSP algorithms "Microcontrollers....", Raj Kamal,
from Pearson Education, 2005

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ARM Special Features

Speed-critical control signals pipelining processing more than one instruction at the fetching, decoding and executing stages.

"Microcontrollers....", Raj Kamal, from Pearson Education, 2005

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A three stage pipeline STAGE 1

Instruction A Execute Instruction B Instruction C Execute Execute

STAGE 2 STAGE 3

Instruction B Decode

Instruction C Decode

Instruction D Decode Instruction E Fetch clock cycle n+2

Instruction C Fetch clock cycle n

Instruction D Fetch clock cycle n+1 Time

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Contd

Three stage Pipelining in superscalar processor facilitating each instruction fetch is in single cycle, decoding in single cycle and execute in the single cycle: Three times execution speed boost up

"Microcontrollers....", Raj Kamal, from Pearson Education, 2005

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Cond

ARM 7 common internal bus for the address and data of 32-bit in32-bit Princeton architecture bus and bus interface for 32-bit data and instructions. ARM9 - Harvard Architecture.
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Memory Architecture
ARM 7 ARM 9 Program, constants and stored tables Memory

Address

Data and Program, constants, stored tables Common Memory

Address

Address

Data Memory

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Performance
ARM 7 and ARM 9 support 300 MIPS (Million Instructions per Second) when die size is 0.13 m.

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ARM 7 architecture
Uses 0.25m and less die size HCMOS technology, very small die size facilitating low voltage operations and low power consumption, (very small power consumption means very low MIPS/Watt)
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Cond

Processor operation on the words as per initialization. A word alignment can then be in big endian [least significant byte stored as higher bits (address 3) of a word] or little endian [least significant byte stored as lower bits (address 0) of a word].
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A 32bit word
Address Little Endian Byte0 (LSB) byte1 byte2 Byte3 (MSB) Big Endian Byte3 (MSB) byte2 byte1 Byte0 (LSB) Address0 Address1 Address2 Address3

Two Initialization options

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Cond

Fully static operation- MCU clock can be reduced to 0 and since fully MOSFETs based

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Cond

Optimized for fast interrupts and DSP algorithms There are two types of requests for interrupts- Fast interrupt request (FIQ) and interrupt request (IRQ). Fast means high priority. 4 gigabytes of linear address space
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Cond

32-bit large set of 16 generalpurpose registers with program counter as one of the register (r15) plus CPSR and SPSR -are two other registers.

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ARM Family Programming Model 16 general-purpose registers with program counter as one of the register (R15).

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- Registers
R0 R1 R2 R3 R4 R5 R6 R7 Lo registers

R8 R9 R10 R11 R12 Hi registers SP (R13) Stack Pointer LR (R14) Link Register PC (Rr15) Program Counter CPSR SPSR

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CPSR and SPSR

CPSR (Conditions and Processor Status Register) SPSR ( Saved Program Status Register) Saves Program Status Register from CPSR on branch and link (routine call) and SPSR can be stacked for each processor mode
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Cond

32-bit RALU and highperformance multiplier Instructions have 8-, 16-, and 32bit data types

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RALU Temp 1
R0R15
+, - , x Rotate

Temp 2

ALU
Multi-bit shifter MAC

CPSR SPSR

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Cond

Coprocessor interface to connect coprocessors, like DSP processors and Java Accelerators

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Cond

System control functions implemented in standard lowpower logic Cost-effective, compact chip

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ARM 7 T Variants

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ARM TDMI instruction set options1. High-performance 32-bit instruction set2. High-code-density Thumb16-bit instruction set than 32-bit instruction architecture
"Microcontrollers....", Raj Kamal, from Pearson Education, 2005 36

Summary

ARM family general-purpose 32-bit superscalar processors Three stage Pipeline High performance and very low MIPS/watt power consumption 32-bit RISC architecture

32 bit Sixteen Registers plus CPSR and SPSR ARM 9 and ARM7 Harvard and Princeton architectures Initialized options: little or big endian modes 32/16/8 bit data types
Two interrupts - Fast interrupt request (FIQ) and interrupt request (IRQ)

- ARM has Many Variants - T variants give alternate option of high code density with 16-bit instructions ARM 7 and ARM 9 popularly used

ARM applications Mobile Devices, PocketPC, PDA, Control Systems, DSP based applications Speech and Image processing Robotics

End of Lesson 1 on ARM CPUs

THANK YOU

"Microcontrollers....", Raj Kamal, from Pearson Education, 2005

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