Escolar Documentos
Profissional Documentos
Cultura Documentos
DIgSILENT GmbH Heinrich-Hertz-Strasse 9 D-72810 Gomaringen Tel.: +49 7072 9168 - 0 Fax: +49 7072 9168- 88 http://www.digsilent.de e-mail: mail@digsilent.de
Sel Directional block Published by DIgSILENT GmbH, Germany Copyright 2003. All rights reserved. Unauthorised copying or publishing of this or any part of this document is prohibited. doc.TechRef, Build 233 27 Mrz 2007
Table of Contents
Table of Contents
1 GENERAL DESCRIPTION ....................................................................................................................................... 4 2 USING THE BLOCK ................................................................................................................................................ 5 3 AVAILABLE SEL DIRECTIONAL TYPES .................................................................................................................. 6 3.1 SEL321.......................................................................................................................................................................... 7 3.2 SEL 351 ........................................................................................................................................................................ 7 3.3 SEL351R ....................................................................................................................................................................... 7 4 INPUT PARAMETERS DEFINITION........................................................................................................................ 8 4.1 DIRECTIONAL TYPE (TYPSELDIR)................................................................................................................................... 8 4.2 SEL DIRECTIONAL ELEMENT (RELSELDIR) ...................................................................................................................... 8 5 INPUT/OUTPUT SIGNALS DEFINITION ................................................................................................................ 9
1 General description
1 General description
The SEL directional block is a full implementation of the new directional logic used by the Schweitzer devices. Such logic is using the negative and the zero sequence impedances to detect the direction of both the phase and the ground fault current. At the moment the block is completely supporting the directional detection features of the SEL 321, SEL 351 and SEL351R. It means that the SEL 321logic is using only a Negative sequence current negative voltage polarized directional logic. The SEL351 and SEL351R logic is more complicate and consists of a combination of three directional elements: Zero-sequence current-polarized (321). Negative-sequence voltage-polarized (32Q). Zero-sequence voltage-polarized (32V).
The logic selects the optimal directional element for each system condition. The Zero-sequence current-polarized equation is:
Z2 =
where:
Re V2 (1 L 2 * I 2 ) I2
2
V2 = Negative-sequence voltage = (VA+ a2VB+ aVc)/3 I2 = Negative-sequence current (IA + a2IB + alc)/3 L2 Line negative-sequence impedance angle
Z0 =
Re 3V0 (1 L 0 * I 0 ) 3I 0
2
where: V0 = Zero-sequence voltage = (VA+ VB+ Vc)/3 I0 = Zero-sequence current (IA + IB + lc)/3 L0 Line zero-sequence impedance angle
For more details regarding such detection method please refer to: http://www.selinc.com/techpprs/6026.pdf http://www.selinc.com/techpprs/6072.pdf http://www.selinc.com/techpprs/6036.pdf http://www.selinc.com/techpprs/6009.pdf http://www.selinc.com/techpprs/6012.pdf http://www.selinc.com/appguide/9902.pdf (SEL351R sensitive directional element)
Please note that such directional block interface is including the directional settings which are usually part of the single distance tripping zone of the impedance devices. In other words its inside this block that the directional setting of each trip element must be set using the Level 1 direction, Level 2 direction etc combo boxes. 16 separated enabling outputs are available.4 for each of the main families of protective elements: the positive sequence elements family, the negative sequence elements family, the neutral current elements family and the residual current elements family. The block is also providing the outputs to control the phase, ground and negative sequence overcurrent element (51P,51N,51Q). The directional type is set using the Relay model parameter in the SelDir type dialog (TypSeldir) main page.
Figure 2: The TypSelDir dialog main page with the Relay Model combobox open
3.1 SEL321
It fully supports the Schweitzer SEL 321 directional element: with reference the 321-3_im_20010417.pdf ( http://www.selinc.com/instruction_manual/321-3/321-3_IM_20030404.pdf )manual the logic implements Figure 2.22 scheme (pag#2-63) . The loss of potential and the open pole logic are implemented using simplified schemes (the reference schemes are figure 2.37 and 2.39 (pag#2-73-75))
3.3 SEL351R
It fully supports the Schweitzer SEL 351 directional element: with reference the 351R_IM_20021119.pdf (http://www.selinc.com/instruction_manual/351r/351R_IM_20021119.pdf) manual the logic implements Figure 4.5 (pag#4-11) Figure 4.6 scheme (pag#4-12), Figure 4.7 scheme (pag#4-12), Figure 4.8 scheme (pag#4-13), Figure 4.9 scheme (pag#4-14), Figure 4.10 scheme (pag#4-15), Figure 4.11 scheme (pag#4-16), Figure 4.12 scheme (pag#4-17), Figure 4.13 scheme (pag#4-17), Figure 4.14 scheme (pag#4-18), Figure 4.15 scheme (pag#4-19), Figure 4.17 scheme (pag#4-23), Figure 4.18 scheme (pag#4-24), Figure 4.19 scheme (pag#4-25), Figure 4.20 scheme (pag#4-25), Figure 4.21 scheme (pag#4-26) . The loss of potential is implemented using the Figure 4.1 scheme (pag#4-1), the open pole logic is implemented using the Figure 5.3 scheme (pag#5-6).
s51PTC s51NTC s51QTC ELOP s3PVOLT E32IV s50P32P s50GFP s50GRP Z0F Z0R Z0 phi0 s50LP a0 s50QF s50QR Z2F Z2R Zm Phi a2 k2
Phase(51P) Torque Control Residual(51N) Torque Control Negative sequence(51Q) Torque Control: Loss Of Potential enable setting True 3-phase voltage connected 3PVOLT flag Ground directional element enabling flag Phase directional element 3-phase pickup threshold Forward directional residual ground pickup threshold Reverse directional residual ground pickup theshold Forward directional Z0 threshold Reverse directional Z0 threshold Zero sequence line impedance magnitude threshold Zero sequence line impedance angle threshold Load detection phase pickup threshold Zero sequence current restraint factor a0 = I0/I1 Forward directional current threshold Reverse directional current threshold Forward directional Z2 threshold Reverse directional Z2 threshold Positive sequence line impedance magnitude threshold Positive sequence line impedance angle threshold Positive sequence current restraint factor a2 = I2/I1 Zero sequence current restraint factor k2 = I2/I0
Amps Amps Amps Ohm Ohm Ohm Ohm Amps Amps Amps Amps Ohm Ohm Ohm
Zero sequence voltage imaginary part Positive sequence voltage real part Positive sequence voltage imaginary part Starting signal coming from the phase (Mho) zone #2 Starting signal coming from the ground zone #2 Breaker status signal (1 = closed,0 = open). At the moment not used
Output Signal Fwd_I1 Fwd_I2 Fwd_I0 Fwd_IN rev_I1 rev_I2 rev_I0 rev_IN I0Level1 I0Level2 I0Level3 I0Level4 INLevel1 INLevel2 INLevel3 INLevel4 I1Level1 I1Level2 I1Level3 I1Level4 I2Level1 I2Level2 I2Level3 I2Level4 _51PTC _51NTC _51QTC
Description Signal on when the positive sequence element detects a forward fault Signal on when the negative sequence element detects a forward fault Signal on when the zero sequence element detects a forward fault Signal on when the neutral current element detects a forward fault Signal on when the positive sequence element detects a reverse fault Signal on when the negative sequence element detects a reverse fault Signal on when the zero sequence element detects a reverse fault Signal on when the neutral current element detects a reverse fault I0 level 1 enabling signal I0 level 2 enabling signal I0 level 3 enabling signal I0 level 4 enabling signal IN level 1 enabling signal IN level 2 enabling signal IN level 3 enabling signal IN level 4 enabling signal I1 level 1 enabling signal I1 level 2 enabling signal I1 level 3 enabling signal I1 level 4 enabling signal I2 level 1 enabling signal I2 level 2 enabling signal I2 level 3 enabling signal I2 level 4 enabling signal Signal enabling the phase overcurrent element (51P) Signal enabling the neutral overcurrent element (51N) Signal enabling the negative sequence overcurrent element (51Q)
Unit
10