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WFX 2nd Semester SY 2010 - 2011 Due: 5pm Wednesday, March 16, 2011 (Rm 201) 1. A dierential amplier is placed in a feedback loop as shown below.
Ro ve + _ vo + ve _ vo Ri + _ a0v e C
RF RS vi _ + vo
Figure 1 Find an expression for the following quantities and and plot their magnitude and phase as a function of frequency: The small signal model of the whole feedback amplier can be drawn as:
RF
RS vi _ ve + Ri + _
Ro vo a0v e C
Figure 2 Assuming the feedback is unilateral, and converting the input to a current source,
i fb RF vo RF RF
ii
ie _ RS ve + Ri + _
Ro vo a0v e C
Figure 3 The eective forward gain with loading, Ae (s), the input impedance Zei and output impedance, Zeo are then
R
Ae (s)
= = =
(1)
F
(2) (3)
where p =
1 C (Ro ||RF ) .
(4)
(5)
F =
1 RF
(6)
(a) The loop gain, T (s). What is T0 ? T (s) = Ae (s) F = a0 (RS ||Ri ||RF ) 1 s Ro + RF 1+ p (7)
T0 =
(8)
vo vi .
What is Av0 ?
ACL (s)
= =
s 1+ vo 1 T (s) 1 p = = T0 ii F 1 + T (s) F 1 + 1+ s
(9) (10)
1 T0 T0 1 1 = RF s s F 1 + T0 1 + p (1+ 1 + T 1 + 0 T0 ) p (1+T0 )
(c) The closed loop input impedance, Zi (s). What is Zi0 ? The input impedance calculation is a little more involved. Notice that the impedance Zi = Zei = RS ||Zix 1 + T (s) (12)
where Zix is the impedance seen if RS is not present. The actual input impedance seen by the input voltage source is RS + Zix . Thus, 1 1 1 1 + T (s) = + = Zi RS Zix Zei Solving for Zix : (13)
1 Zix
1+ 1 RS
T0 s 1+ p
1 RS
(14)
(15)
s p
RS (1 + T0 ) 1 + =
s p (1+T0 )
(16)
(17)
(18)
Zi
= =
(19) (20)
(d) The closed loop output impedance, Zo (s). What is Zo0 ? (Ro ||RF ) 1+1 s Zoe (Ro ||RF ) 1 p = Zo = = s T 0 1 + T (s) 1 + T0 1 + p (1+ 1 + 1+ s T0 )
p
(21)
2. Repeat problem (1) if the dierential amplier is placed in the following feedback loops:
vi
+ _ R1
vo
vi R2
+ _
vo
(a)
(b)
Figure 4 (a) For the amplier in gure (a): The small signal model can be drawn as:
Ro vi + ve _ vo Ri + _ a0v e C
v fb R2 R1
Ro vi + ve _ vo Ri + _ a0v e C
v fb R1 R2 + _ R2 R1+R2
Figure 6 The amplier forward gain, feedback factor, input impedance and output impedance are then:
(R1 +R2 )
vo
R1+R2
Ae (s)
= a0 = a0
where p =
F =
R2 R1 + R2
Zei = Ri + R1 ||R2 Zeo (s) = Ro || (R1 + R2 ) || The loop gain is then: T (s) = Ae (s) F = a0 T0 = a0 The closed-loop gain is then: vo 1 T (s) = vi F 1 + T (s)
s 1+ 1 1 T0 1 p = s T0 F 1 + 1+ F 1 + T 1 + 0 s p (1+T0 ) p
1 1 = Ro || (R1 + R2 ) s sC 1+ p
Ri R1 + R2 R2 1 s Ri + R1 ||R2 Ro + R1 + R2 R1 + R2 1 + p
(28) (29)
Ri R1 + R2 R2 Ri + R1 ||R2 Ro + R1 + R2 R1 + R2
Av (s)
(30)
T0
(31)
R1 + R2 R2
T0 1 s 1 + T0 1 + p (1+ T0 )
(32)
1+
R1 R2
T0 1 s 1 + T0 1 + p (1+ T0 )
(33)
Zi (s)
T0 s 1+ p
(34) (35)
Zo (s)
= =
1 s 1+ p
(36)
Ro || (R1 + R2 ) 1 s 1 + T0 1 + p (1+ T0 )
(37)
(b) For the amplier in gure (b): The small signal model can be drawn as:
Ro vi + ve _ vo Ri + _ a0v e C
Ro vi + ve _ + _ vo Ri + _ a0v e C
vo
Figure 8 The amplier forward gain, feedback factor, input impedance and output impedance are then:
Ae (s) where p =
1 CRo .
= a0
1 1 = a0 s 1 + sCRo 1+ p
(38)
F =1 Zei = Ri Zeo (s) = Ro || The loop gain is then: T (s) = Ae (s) F = a0 T0 = a0 The closed-loop gain is then: vo 1 T (s) = vi F 1 + T (s)
s 1+ 1 1 a0 1 p = a0 s F 1 + 1+ F 1 + a0 1 + p (1+ s a0 ) p
(39) (40)
1 1 = Ro s sC 1+ p
(41)
1 s 1+ p
(42) (43)
Av (s)
= = =
a0
a0 1 s 1 + a0 1 + p (1+ a0 )
Zi (s)
= Zei [1 + T (s)] = Ri = Ri (1 + a0 ) 1+
1+
a0 s 1+ p
(47) (48)
s p (1+a0 ) s 1+ p
Zo (s)
= =
(49) (50)
Ro 1 s 1 + a0 1 + p (1+ a0 )
V DD vi
+ _
M1 vo I bias
Figure 9 Note that the amplier is the same as that used in problem (1), the transistor M1 has nite output resistance, and the current source is ideal. The small signal model can be drawn as:
Ro vi + ve _ Ri + _ C
vx ro
a0v e
g m v gs
vo
Figure 10 Notice that vgs = vx vo . (a) What feedback topology is used? Since the quantity sampled at the output is a voltage, and the quantities compared at the input is also a voltage, this is a shunt-shunt feedback amplier. (b) What is the DC open loop forward gain? The forward gain is just the gain from ve to vo without the feedback connection, thus: vx = a0 Writing the KCL equation at the output node: gm vgs = Thus, vo gm ro = vx 1 + gm ro (53) vo = gm (vx vo ) = gm vx gm vo ro (52) 1 ve 1 + sCRo (51)
T (s)
= Ae F = a0 = T0 1 s 1+ p
gm ro 1 1 + gm ro 1 + sCRo
(56) (57)
Where T0 = a0
gm ro 1+gm ro
and p =
1 CRo .
(e) Plot the magnitude and phase response of the loop gain, T (s).
|T| T0
Figure 11
(f) Plot the magnitude and phase response of the closed loop gain, Av (s) =
vo vi .
Av (s)
vo 1 T (s) = vi F 1 + T (s)
s 1+ 1 T0 1 p = s T0 F 1 + 1+ 1 + T 1 + 0 s p (1+T0 ) p
(58)
T0
(59)
Av 0 45 90
Figure 12
(g) In what type of applications would this circuit be used? This circuit uses a common-source amplier as a buer. Thus, in situations where a large amount of current is required at the output, this large current is provided by the MOSFET. The amplier can be relatively low power and only provides a boost to the open loop gain, thus making the closed loop amplier gain very close to 1. 4. The dierential amplier in problem (1) is relatively ideal. In a real amplier, due to parasitic capacitances of the transistors inside the amplier, the gain is also a function of frequency. Assume that the gain of the dierential amplier varies with frequency as a ( ) = a0 1 + j p2 (60)
vi
+ _
vo
Figure 13
= a0
(61)
Ae (s)
a (s)
1 1 1 s = a0 s s 1+ 1 + 1 + p2 p p F =1
(62)
(63)
10
T (s) = Ae (s) F = a0
1 1 s 1 + s 1 + p p2
(64)
T0 = a0
(65)
(a) What should be the value of p2 such that the phase margin is 45 ? From our class notes, k = tan (P M ) where p2 = k T0 p Thus for a P M = 45 , (67) (66)
p2
= =
(68) (69)
(b) What should be the value of p2 such that the phase margin is 60 ?
p2
= =
(70) (71)
(c) What should be the value of p2 such that the phase margin is 0 ?
p2
= =
p tan (0 ) T0 0
(72) (73)
This should be expected since the arctangent function only asymptotically approaches 180 . thus, for a nite p , the second pole must be at p2 = 0.
11