Code No: RR410408 Set No.

1
IV B.Tech I Semester Supplementary Examinations, February 2007
ADVANCED COMPUTER ARCHITECTURE
( Common to Electronics & Communication Engineering and Electronics &
Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) Distinguish between

i. data processing
ii. information processing
iii. Knowledge processing
iv. intelligence processing.
(b) What do you understand by balancing of system bandwidth? Why is it nec-
essary? Illustrate with suitable examples. [8+8]

2. (a) What are precedence graph and reservation tables. What is their role in pipline
systems?
(b) Describe three different classes of data dependent hazards and illustrate the
hazard conditions. [8+8]

3. (a) Explain the various configurations of an SIMD array Processors.

(b) List down the similarities and differences between them. [10+6]

4. (a) Describe Batcher’s Odd Even merge of two sorted sequences on a linear array
of P E ′s using an example.
(b) Give the schematic logic design of a typical memory cell in an associative
memory. [8+8]

5. (a) Explain briefly the communication between processors in a Multiprocessor

environment.
(b) With suitable diagram, explain loosely coupled and tightly coupled Multi-
processors. [6+10]

6. (a) Describe multicache problems? Describe methods to solve these problems.

(b) Describe a methodology to evaluate different multiprocessor memory configu-
rations. [8+8]

7. (a) Compare Control flow computers against Data flow computers.

(b) Explain with an example, how an instruction is executed in a data flow com-
puter. [8+8]

8. (a) What are the fundamental classes of performance measures? Explain in detail

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Code No: RR410408 Set No. 1
(b) Discuss in detail the performance of M/M/1 queuing structure. [8+8]

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Code No: RR410408 Set No. 2
IV B.Tech I Semester Supplementary Examinations, February 2007
ADVANCED COMPUTER ARCHITECTURE
( Common to Electronics & Communication Engineering and Electronics &
Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Explain different parallel processing mechanisms that are possible in uniprocessor

computers. [16]

2. (a) Describe the basic concepts of pipelined computers and overlapped instruction
execution with the help of space-time diagrams.
(b) Give the functional structure of a pipelined modern computer with scalar and
vector capabilities and explain. [8+8]

3. (a) Explain the connectivity of a barrel shifter for N = 8.

(b) List down the routing function for a plus-minus-2i Network and compare with
Illiac Network. [10+6]

4. (a) Describe O (n log2 n) algorithm used for matrix multiplication.

(b) Describe the connection issues of PEs for efficient SIMD processing. [8+8]

5. (a) Briefly describe the following terms associated with a multiprocessor system.
i. Multiple computer systems.
ii. Multiprocessor systems.
iii. Loosely coupled multiprocessors.
iv. Tightly coupled multiprocessors.
(b) Explain briefly the steps involved in an intracluster memory access. [8+8]

6. (a) When processes are said to be concurrent? Explain briefly Conway’s fork-join
concept.
(b) Explain briefly reusable, consumable and virtual resources. [10+6]

7. (a) Explain any two VLSI arithmetic modules for matrix computation.
(b) Explain the VLSI computing module for the inversion of a triangular matrix.
[8+8]

8. (a) Give the features of Hydra operating system.

(b) Demonstrate the effect of memory contention on the performance of C.mmp.
[8+8]

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Code No: RR410408 Set No. 3
IV B.Tech I Semester Supplementary Examinations, February 2007
ADVANCED COMPUTER ARCHITECTURE
( Common to Electronics & Communication Engineering and Electronics &
Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Explain different Memory Management Policies.

(b) What are Array computers processors ? Describe a array processor environ-
ment. [8+8]

2. Describe how Branch target buffering, and Register tagging improves the perfor-
mance of pipelines. [16]

3. Bring out the differences, merits and demerits of Rearrangeable, Non Blocking,
and Blocking and Networks. Give an example commercial network for each one of
them. [16]

4. (a) Describe Merge - Sorting in M(4,4) sorting algorithm using an example.

(b) Explain the advantages of using shuffle interconnection for the implementation
of the polynomial evaluation algorithm, as compared with the use of the Illiac
mesh network for the same purpose. [8+8]

5. Explain about Tightly coupled multiprocessor with and without private cache mem-
ory. [16]

6. (a) Write an asynchronous parallel algorithm for finding the zeros of a function
f(x) using Newton’s iteration method.
(b) Explain briefly the methodology for evaluating the performance of a parallel
algorithm. [8+8]

7. (a) Explain the functional structure of the processing element(PE) in Arvind’s

data Flow machine.
(b) Describe switches, arbiters and distributers used in Data flow network con-
struction. [8+8]

8. (a) What are the fundamental classes of performance measures? Explain in detail
(b) Discuss in detail the performance of M/M/1 queuing structure. [8+8]

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Code No: RR410408 Set No. 4
IV B.Tech I Semester Supplementary Examinations, February 2007
ADVANCED COMPUTER ARCHITECTURE
( Common to Electronics & Communication Engineering and Electronics &
Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Describe the various parallel computer structures in common use and differ-
entiate among them.
(b) Distinguish between
i. temporal parallelism
ii. Spatial parallelism
iii. asynchronous parallelism. Illustrate each of these with examples. [8+8]
2. (a) How the vector length effects the processing efficiency ? Explain different
enhancement techniques.
(b) Describe memory interleaving mechanisms. [8+8]
3. (a) Explain the connectivity of Illiac Network with N = 16.
(b) Draw a neat 16*16 baseline network and Explain its connectivity between its
nodes. [8+8]
4. (a) Describe M(j,k) sorting algorithm.
(b) Describe a Bit serial Associative memory organization with suitable diagram.
[8+8]
5. (a) Explain the operation of a multiprocessor system with multiport memory.
(b) The multistage networks are modular and easy to control. Justify this. [10+6]
6. (a) What is PDN ? Why it is required ? Explain the various fields of PDN.
(b) Define the following terms with respect to multiprocessor scheduling Flow
time,Mean flow time,Idle time and Throughput. [8+8]
7. (a) Differentiate between dependence driven and multi level event driven approach
of designing data flow systems.
(b) Explain the functional design of a processor element in the EDDY system.
[8+8]
8. (a) Give the characteristics of the Cray-1 computer system.
(b) Explain with neat diagrams the 4 types of vector instruction in Cray and give
example. [8+8]

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