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A 8-GHz SiGe HBT VCO Design on a Low Resistive Silicon Substrate Using GSML
Jongsoo Lee, Young-Gi Kim, Member, IEEE, Eun-Jin Lee, Chang-Woo Kim, Member, IEEE, and Patrick Roblin, Member, IEEE

AbstractA practical layout method called ground shield microstrip lines (GSML) is investigated for the reliable design of high frequency interconnection lines on a low resistive silicon substrate. GSML facilitates the prediction of parasitic networks at the expense of introducing negligible loss. The microwave performance of a GSML line structure is compared to that of a conventional metal line on the same standard silicon substrate (20 cm). Then, the GSML structure is applied to an 8-GHz SiGe heterojunction bipolar transistor (HBT) voltage-controlled oscillator (VCO) circuit. The GSML method replaces the post layout simulation and reduces iteration time, increasing design efciency. A fully integrated differential tuning SiGe HBT 8-GHz VCO is designed and tested. The measured phase noise for the VCO is dBc/Hz at 1-MHz offset with an output power of dBm.

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Index TermsGround shield microstrip line (GSML), heterojunction bipolar transistor (HBT), microstrip line, radio frequency integrated circuit (RFIC), voltage-controlled oscillator (VCO).

I. INTRODUCTION HE RF and analog integrated circuit market for wireless broadband applications has been rapidly expanding during the last few years. To be successful in the wireless market, chip solutions need to be small, low cost and feature low power consumption. Well developed, low-cost, reliable and time proven silicon processes have become attractive and can now effectively compete with other expensive processes such as GaAs processes. With the advances in state-of-the-art silicon processes, silicon-based circuits have now reached applications in which IIIV devices had previously prevailed. Silicon-based circuits have now become a strong candidate that can meet the requirements for successful chip set solutions for new developing high-frequency broadband applications. Recently new emerging wireless broadband applications such as ultra-wide-band (UWB) [1] and WiMAX [2] have been introduced. These new developing wireless broadband applications operate at very high frequencies. As operating frequencies
Manuscript received November 13, 2006; revised February 15, 2007. This work was supported in part by the Basic Research Program of the Korea Science & Engineering Foundation under Grant R01-2003-000-10455-0 and in part by a Texas Instruments Fellowship. This paper was recommended by Associate Editor A. Apsel. J. Lee and P. Roblin are with the Electrical and Computer Engineering, The Ohio State University, Columbus, OH 43210 USA (e-mail: leej1@ece.osu.edu). Y,-G, Kim is with the Department of Data Communications, Anyang University, Anyang-Si 430-714, Korea (e-mail: kimyg@aycc.anyang.ac.kr). E.-Jin Lee was with the Department of Data Communications, Anyang University, Anyang-Si 430-714, Korea. He is now with the College of Electrical Engineering and Computer Science, Kook Min University, Seoul 136-702, Korea. C.-W. Kim is with the College of Electric and Information Engineering, Kyung Hee University, Yongin-Si 449-701, Korea (e-mail: cwkim@khu.ac.kr). Digital Object Identier 10.1109/TCSI.2007.904595

are pushed up, the low resistivity silicon substrate becomes a major obstacle for silicon-based radio frequency integrated circuits (RFICs). The low-resistivity of silicon substrate leads to large signal losses in the substrate and cross talk through the substrate. Obviously, high resistive substrates are preferable for high frequency applications. However due to its complicated fabrication processes, high-resistive silicon wafers are quite expensive for standard commercial chip applications, and are not attractive as a chip solution material. Typical transmission-line loss on standard Si substrate (i.e., 15 to 20 cm) is much higher than that on GaAs substrate, which is a huge obstacle for many microwave applications. Due to the complicated parasitic networks caused by low resistivity of silicon substrate, precise prediction of the high frequency transmission characteristics for conventional interconnection lines based on standard silicon substrate is hardly possible in the design of RFIC at high frequencies [3]. To overcome the drawback of the low resistive silicon substrate and take advantage of cheap silicon wafer prices and welldeveloped silicon process technology, much research has been carried out and new novel methodologies have been suggested. These novel methodologies are based on two basic principles. One approach is to imitate a high resistivity substrate, and the other is to provide an ideal ground plane [4]. This work proposes a practical layout method called ground shield microstrip lines (GSML) which allow for the precise prediction of parasitic networks of high frequency interconnection lines on the low resistive silicon substrate at the expense of introducing trivial loss. GSML can be directly used in the design procedure of RFICs in standard CMOS or bipolar processes. We will rst investigate the microwave performance of a GSML line structure and compare it to a conventional metal line counterpart on the same standard silicon substrate (20 cm). Then, the use of the GSML technique will be demonstrated in the design of an 8-GHz SiGe heterojunction bipolar transistor (HBT) voltage-controlled oscillator (VCO) circuit. The outline of this paper is as follows. In Section II, previous works are reviewed. Section III is dedicated to the GSML structure. The design of an 8-GHz SiGe HBT VCO is presented in Section IV. Measurement results of the 8-GHz SiGe HBT VCO are reported in Section V. Finally, a summary of achievement is given in Section VI. II. SPECIAL RF TECHNOLOGY REVIEW There are several different mechanisms which cause energy losses at high operating frequencies. One is related to the metal loss, i.e., metal series resistance, and the others are associated

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with the substrate loss via capacitive coupling and magnetic coupling to the substrate [5]. Metal loss comes from the skin effect and other magnetic effects at high frequencies, which leads to nonuniform current distribution in the metal lines and an increase in the effective resistance. Capacitances between metal lines and substrate provide paths where signals in metal lines pass through the substrate, causing signal losses and cross talks between nearby building blocks. In the case of heavily doped substrate, the magnetic eld induced by the current owing in the metal lines results in eddy currents in the substrate, and image currents in the substrate which ow in opposite direction to the original currents, leading to energy loss. To overcome the drawback of the low resistive silicon substrate, a number of special RF technologies have been suggested. Yue described in his paper [4] a pattern ground shield in which the resistivity of the silicon substrate goes to either zero or innity. This observation will provide an important clue to resolution of the above issues. Etching of the silicon substrate [6] or high resistivity substrate [7] have been used such that the resistivity of the substrate approaches innity. The substrate crosstalk suppression capability of silicon-on-insulator substrate with buried thick undoped tungsten silicide ground planes has been reported [8]. Those methods have however the drawback that they are not compatible with standard CMOS processes. Since the introduction of a patterned ground shield (PGS) [4] by Yue, this method has been used extensively in RF circuit designs. Patterned ground shield is made of plates that must be broken regularly in the direction perpendicular to the current direction in metal lines so as to prevent an image current from occurring on the ground shield, reducing energy losses in metal lines and, in addition, reducing coupling noise from substrate to metal lines. Its advantage is that it can be implemented in standard silicon process. This method was successfully applied to on-chip interconnection lines to reduce the loss up to 7 GHz [9]. The disadvantage of PGS method is that the number of plates which are used for a patterned ground shield is very large. Accordingly, the extraction of the parasitics associated with this layout process is greatly complicated by the large number of plates used. The complexity of integrated circuits for high frequency broadband applications is increasing rapidly. The number of interconnections between building blocks is increasing and the level of interaction is becoming much more complicated. To be successful in RFIC design, it is very important to take all of parasitic effects into account to verify whether designed circuits work appropriately. The parasitic effects become much more critical and serious as operating frequencies are pushed up. RFIC designers normally rely on the post layout simulation to check if parasitic networks have an impact on the performance of designed circuits and verify if the designed circuits meet all requirements described in the application specications. In general, the design time spent on extraction of layout and post layout simulation depends on the number of circuit blocks and associated wiring, and the fact that parasitic networks dramatically increase with the number of building block considered. Highly complex layout structures such as patterned ground shields under on-chip inductors and interconnection lines, and guard rings

Fig. 1. Actual signal line structures. (a) Proposed GSML. (b) Bare line.

around on-chip inductors lead to an unacceptable number of parasitic networks, causing a huge waste of time and resources. In spite of their advantages, these RF special techniques make it very difcult or sometimes impossible to do reliable post layout simulation in such complicated circuits. In this paper, we propose a very practical methodology to remove the issue of post layout simulation in circuits with complicated layout structures. III. GSML METHOD We propose the use of GSML based on the thin lm microstrip (TFMS) lines [10] for high precise and reliable prediction of parasitic effects of interconnection lines at high frequencies on low resistive silicon wafers. GSML can be used for the design and fabrication of RFICs in standard CMOS or bipolar processes. The main advantage of GSML is that the parasitic effects coming from interconnection lines can be considered in the stage of schematic simulation. This method can replace the post layout simulation process to some degree, reducing circuit design time and increasing efciency in RF circuit designs by reducing iterations between schematic and layout simulations. Fig. 1 shows the proposed GSML transmission line structure. The GSML line structure consists of signal transmission lines and a ground shield metal plane. A top thick metal layer is used for the signal transmission lines and metal 1 layer is used for the shield metal plane. To provide a ground plane and separate the top metal line from the lossy silicon substrate, metal 1 layer is grounded. In addition, separation between signal line and lossy substrate mitigates the effect of the low resistive silicon substrate.

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Fig. 2. Equivalent circuit for a lossy transmission line.

Fig. 3. Two examples of a microstrip over a lossy silicon substrate.

Microstrip loss and prediction of the loss in general are topics of continued interest [11]. The advantage of GSML is that the entire chip area except the active devices and pads provides a ground plane to the signal line. The ground shield plain blocks the signal path through the low resistive substrate and simplies the modeling of the parasitic networks relative to the ground by providing a solid ground plane. By using a GSML structure, prediction of high frequency parasitic loss and cross talk problems in low resistive silicon substrate can be improved. The high predictability of parasitic loss in the GSML structure arises from the more accurate micro-strip line methods which can be directly applied to the RFIC design. If these effects are well predicted, the circuit design and layout can be optimized to minimize parasitic loss. Microstrip line modeling allows us to more precisely predict the performance of high frequency RF building blocks. To route interconnects in the design, a few additional metal layers other than the top metal layer were used. However, the number of these additional layers was kept to a minimum and their length was kept very short, such that their associated parasitic effects are insignicant. A. Lossy Transmission Lines In physical transmission lines, the propagation of the voltage and current waves is attenuated. The attenuation constant is a joint function of the microstrip geometry, the electrical properties of the dielectric substrate and the conductors, and of frequency. The losses can be expressed as loss per unit length along the microstrip line using an attenuation factor. There are two types of losses in a microstrip line: the dielectric loss and the ohmic skin loss in the conductors [12]. Fig. 2 shows a basic equivalent circuit for a lossy transmission line. R and G represent a series resistance and shunt conductance of transmission line per unit length. The conductor loss is represented by the series resistance R, while the dielectric loss is represented by the shunt conductance G. The propagation constant and characteristic impedance of a lossy transmission line is given as (1) (2) which are complex, indicating power loss during propagation and a phase shift between voltage and current waves. For large loss in the dielectric, the propagation of modes such as the slow-wave mode or skin-effect mode can take place. Consider two examples in Fig. 3. Depending on the conductivity of

Fig. 4. Comparison of the propagation constant  versus frequency for a TEM model neglecting the dielectric loss and a Momentum simulation and the Tuncer model.

the silicon layer and the wave frequency, the silicon layer can behave like a shunt resistance, a capacitance or a ground plane. When the loss in the dielectric region is important, an exact solution must be obtained for the propagation constant and attenuation factor . Starting from (1) and using the following denitions: (3) (4) (5) (6) (7) One can verify that is given by (8) A plot of versus frequency is given by Fig. 4. (A Momentum simulation The dispersion obtained for and the Tuncer model [13]) clearly departs from the conventional linear loss-less TEM case. Assuming a TEM mode, the phase and group velocity are obtained from the propagation . constant and (9)

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Fig. 5. Various modes of propagation for a 20-m line on a lossy substrate.

Fig. 7. Skin depth versus frequency in an aluminium metal line.

Fig. 6. Skin effect of transmission line.

The larger slope observed at low frequency in Fig. 4 is indeed associated with low phase and group velocities. This originates from the penetration of the magnetic eld in the lossy silicon layer whereas an electric eld remains mostly conned in the SiO layer. As a result, both C and L are large, and the phase velocity becomes very large. For high enough frequencies, a propagation mode switches to either a dielectric quasi-TEM mode at high silicon resistivity or a skin effect mode at low silicon resistivity when the skin depth becomes comparable or smaller than the silicon layer thickness. The different modes are indicated in Fig. 5 for a 20- m width line. Clearly, accurately modeling lines in lossy substrate is difcult. B. Loss in Transmission Line 1) Conductor Loss: Conductor loss at high frequencies increases with the square root of the frequency and is dominated by skin effect as illustrated in Fig. 6. Due to the skin effect, RF currents are forced to ow near the surface of the conductor. The skin depth of a conductor is dened as the distance in the conductor for which the current density drops by 37% of its value at the surface [14] and is given by (10)

where is the skin depth (m), the conductor magnetic perme: free space), the bulk conducability ( tivity (S/m), and the frequency (Hz). As frequency increases, the skin depth becomes thinner and thinner, and the effective resistance of the metal line increases. Fig. 7 shows the variation of the skin depth versus frequency. It is evident that a 2.5- m thick metal layer is efcient up to 5 GHz, which is the normal thickness for top metal layers in recent processes. Above 5 GHz, the skin effect in a 2.5- m metal layer becomes serious. To accurately model interconnection losses between devices as well as I/O pads, skin effect has to be taken into account in the design stage, especially, at frequencies above 5 GHz. The GSML method provides a good methodology for making it possible by utilizing the microstrip models used in MMIC design. 2) Dielectric Loss: Another source of loss in transmission line is dielectric loss. In this work, a ground plane is placed between thick metal signal lines and a lossy silicon substrate. Due to the thin dielectric layer placed between the metal layer and the ground shield, transmission lines show relatively high insertion losses. Fortunately, compared to conductor losses, dielectric losses are relatively small, and not a major source of loss. To verify the performance of the GSML, several 10- m width signal lines are designed and fabricated as shown in Fig. 8. Signal lines with and without a ground shield are implemented. In the test structure, open and short patterns are also included to assist with the de-embedding process. The loss characteristics of the signal lines are predicted using the ADS Momentum simulator and compared with measured values. The results given in Fig. 9 show that the GSML improves the return loss characteristics. This comes from the fact that the inserted ground shield plane provides a sound ground point. Insertion losses in Fig. 10 show that the insertion loss of the GSML is larger than that of a conventional line up to 4.5 GHz, while the insertion loss of a GSML is smaller than that of a conventional line above 4.5 GHz. In practice the return loss has an impact on the insertion loss of signal lines. This fact makes insertion loss comparisons relevant only to 50- source and loads.

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Fig. 11. Gmax characteristics of 10 m width signal lines in Fig. 8. Fig. 8. Photo of GSML test structure.

Fig. 9. Return loss characteristics of 10 m width signal lines in Fig. 8.

The result is shown in Fig. 11. It shows that the signal loss with GSML increases slightly faster than in the unshielded line. This increase is due to the thinner dielectric. However, the signal loss remains quite small for the ideal matching condition reand is an acceptable tradeoff. quired by Patterned ground shields are preferred over solid ground shield under the inductor because they suppress the eddy or image current induced by magnetic coupling. In the case of a microstrip line the image current is welcomed as it provides a well dened return path for the current. At the same time the inductive series impedance added by the microstrip is kept small due to the strong capacitive coupling induced by the very thin dielectric. The loss associated with the eddy current effect along the microstrip is then the skin effect loss in the ground plane which for the GSML considered is kept quite small as in Fig. 11. indicated by Indeed the GSML structure provides advantages such as lower R , suppression of cross talk, reliable prediction of all parasitics at the expense of trivial potential losses coming from the thinner dielectric. Further the optimization of the line width can be done at the circuit level using microstrip design method. IV. CIRCUIT DESIGN The SiGe HBTs used in the design feature a typical cutoff frequency of 45 GHz and a typical maximum oscillation frequency of of 60 GHz. The designed circuit is fabricated using a 0.35- m SiGe process. The VCO core is made up of a cross-coupled differential pair with a parallel resonator connected between the collector nodes. In most of the frequency tuning circuits in the differential VCOs reported by other research groups, the oscillation frequency decreases as the tuning voltage goes up, or negative tuning voltages are used [15][17]. Similarly, the differential VCO presented in this paper has the frequency tuning circuit such that the oscillation frequency decreases as the tuning voltage goes up. The P-ports of the varactor diodes are biased by the tuning voltage via choke resistors. Inductors have a low dc voltage drop, reduce noise and improve linearity. However, they occupy a large chip area. Therefore, resistors are used for the choke to reduce the chip area due to the comparatively large size of the spiral inductor in the MMIC chip. However, the choke resistors contribute to increase phase noise and decrease the tuning range

Fig. 10. Insertion loss characteristics of 10 m width signal lines in Fig. 8.

The ultimate gure-of-merit for comparing GSML to a conventional line under optimal matching condition is provided by given in the maximum available gain,

with (11)

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Fig. 14. Schematic of differential VCO with buffer amplier circuit with transmission lines. Fig. 12. Simplied schematic of differential VCO with buffer amplier circuit.

Fig. 13. Layout of differential VCO with buffer amplier circuit. The built-in inductors used in the VCO circuit have a patterned ground shield.

of the oscillation frequency. The coupled differential oscillator circuit is connected to a buffer amplier circuit which adapts an emitter follower buffer circuit topology as shown in Fig. 12. Traditionally, error-free layouts pass through post layout simulation process to verify whether the performances of the design fulll its requirements. If the requirements are not satised, optimization of the circuit is required. This process is repeated over and over until all requirements are satised. In the post layout process, the extraction of parasitic components is a timeconsuming process. This problem is aggravated when using advanced state-of-art layout techniques which require more complicated layouts. In the new proposed method, the optimization process is possible at the schematic design stage because compared to devices and passive components, the interconnection lines are large enough not to be affected by the change of parameters of devices and passive components. The increase of the number of components introduced by the GSML structure is trivial compared to the number of parasitic components introduced by the extraction process. Therefore, simulation at the schematic stage greatly benets from the GSML methodology. The layout of the differential VCO is shown in Fig. 13. As mentioned in Section III, the GSML method is applied to the layout. To be successful in the design of RFIC circuits, parasitic effects coming from interconnection lines have to be taken into account. In this work, the microstrip line method is applied using the GSML methodology. Fig. 14 shows the schematic of the differential VCO and buffer amplier using microstrip

Fig. 15. Simulation result of a differential VCO with a buffer amplier circuit with transmission lines.

lines. All interconnection lines shown in Fig. 13 have been converted to microstrip lines in Fig. 14. Using this reliable information on interconnection lines, the VCO circuit is optimized at the schematic design level, removing the need for multiple post layout simulation iterations. To investigate the effect of GSML in the VCO performances, two VCOs were simulated; one with GSML, and the other without GSML. Fig. 15 shows the simulation results of the GSML VCO. The simulated output power of the VCO and the second harmonic suppression are dBm at 7.9 GHz and dBc, respectively. Fig. 16 and 17 show simulated characteristics of VCOs with and without GSML structure. The operating frequency of the GSML based VCO varied from 7.32 to 8.18 GHz with a tuning voltage varying from 0 to 2.8 V. This shows a negative frequency tuning of 860 MHz. The phase noise of the VCO was dBc/Hz at 1-MHz offset. Table I summarizes the performances of VCOs with and without GSML, and Table II provides a measurement summary of an 8-GHz VCO. The frequency tuning range is one of the most important requirements in VCO design. The start and stop frequencies of the 2 VCOs deviate by 1.02 and 1.14,

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TABLE I SIMULATION RESULTS SUMMARY OF VCOS

TABLE II MEASUREMENT SUMMARY OF 8-GHZ VCO

Fig. 16. Simulated output power, oscillation frequency, and second harmonic suppression characteristics of VCO versus Frequency tuning voltage. (a) VCO with GSML. (b) VCO with elimination of GSML.

Fig. 18. Photograph of microbuffered VCO chip.

practice perturbed by the interconnect parasitic components. The accurate quantication of the parasitics in the GSML VCO will allow to achieve closer agreement between simulation and measurement results. Note also that the output power and phase noise exhibit improved performance when using GSML. V. MEASUREMENT RESULTS The VCO chip occupies an area of 0.57 mm by 0.89 mm including all wire bonding pads as shown in Fig. 18. The practical chip occupation will be reduced to 0.40 mm by 0.62 mm if it is integrated as a component in a monolithic RF transceiver circuit. After grinding to 235- m thickness, the processed chips were wire-bonded to the circuit board and tested with a HP8563 E spectrum analyzer. dBm output power at 8.35 GHz The oscillator shows as shown in Fig. 19. The second harmonic suppression is dBc as shown in Fig. 20. The even order harmonics

Fig. 17. Simulated phase noise versus frequency tuning voltage.

respectively. These deviations measure how the oscillation frequency of the VCO ideally set by the LC resonator is in

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Fig. 21. VCO phase noise at 1-MHz offset from 8.347-GHz carrier.

Fig. 19. VCO output spectrum.

Fig. 22. Output power, oscillation frequency, and 2 harmonic suppression characteristics of VCO in terms of frequency tuning voltage.

Fig. 20. VCO harmonic spectrum performance.

will be even more reduced when the VCO is connected as a differential LO supply circuit to the balanced mixer, due to the even harmonic cancellation in the differential VCO circuit dBc/Hz topology. The VCO achieves a phase noise of at 1-MHz offset as shown in Fig. 21. A 3-V battery was used as dc bias source for phase noise measurements to reduce the DC-FM noise contribution normally produced by standard power supply [18]. The VCO operating frequency was varied from 7.35 to 8.55 GHz with a tuning voltage variation from 0 V to 2.8 V as shown in Fig. 22. This is a negative frequency tuning of 800 MHz. The dc current consumption is 12 mA at 3-V voltage supply. VI. CONCLUSION The accurate and reliable GSML layout methodology was used in the design of a VCO. The ground shield layer is conformed to the circuit such that the interconnection lines are

shielded from the low resistive silicon substrate. This layout methodology has the advantage of greatly simplifying the estimation of the parasitic networks for the interconnection lines at the expense of introducing trivial amount of loss. This structure also reduces cross-talk and noise from the low resistive silicon substrate. In this work, the GSML method replaced the post layout simulation and reduced iteration times, increasing efciency in the design and optimization of the circuit. A fully integrated differential tuning SiGe HBT 8-GHz VCO was designed and tested. It has negative tuning frequency range of more than 10% with a positive tuning voltage change of 2.8 V. dBc/Hz at The measured phase noise for the VCO was dBm. The measured 1-MHz offset with an output power of oscillation frequency and output power were close to those predicted by the simulation using GSML. The VCO chip size, dc power consumption, output power, and the phase noise are comparable to other monolithic oscillators and are believed to deliver optimal results for monolithic oscillators intended for 8-GHz RF transceivers. This work demonstrated that GSML is an effective and useful layout method which leads to reliable design even for sensitive autonomous circuits such as oscillators. GSML provides an alternative RFIC layout methodology which simplies design procedures by eliminating the post layout simulation procedure which is believed not to be reliable at high radio-frequencies.

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ACKNOWLEDGMENT The authors would like to thank to IC Design Education Center for providing computer-aided design tools. The rst author would like to thank Mr. Wetterskog of Texas Instruments for organizing the TI graduate student fellowship. REFERENCES
[1] R. Harjani, J. Harvey, and R. Sainati, Analog/RF physical layer issues for UWB systems, in Proc. 17th Int. Conf. VLSI Design, Mumbai, India, Jan. 2004, pp. 941948. [2] B. Bisla, R. Eline, and L. M. Franca-Neto, RF system and circuit challenges for WiMAX, Intel Techolog. J., vol. 8, pp. 189200, Aug. 2004. [3] J. D. Cressler, SiGe HBT technology: A new contender for si-based RF and microwave circuit applications, IEEE Trans. Microw. Theory Tech., vol. 46, no. 5, pp. 572589, May 1998. [4] C. Yue and S. Wong, On-chip spiral inductors with patterned ground shields for si-based RF ICs, IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 743752, May 1998. [5] B. Razavi, RF Microelectronics. Englewood Cliffs, NJ: PrenticeHall, 1998. [6] A. J. Chang and M. Gaitan, Large suspended inductors on silicon and their use in a 2-m CMOS RF amplier, IEEE Electron Device Lett., vol. 14, pp. 246248, May 1993. [7] W. J. K. Ashby, I. Koullias, and S. Monian, High-Q inductors for wireless applications in a complementary silicon bipolar process, IEEE J. Solid-State Circuits, vol. 31, no. 1, pp. 49, Jan. 1996. [8] J. S. Hamel, S. Stefanou, M. Bain, B. M. Armstrong, and H. S. Gamble, Substrate crosstalk suppression capability of silicon-on-insulator substrates with buried ground planes(GPSOI), IEEE Microw. Guide Wave Lett., vol. 10, pp. 134135, Apr. 2000. [9] R. Lowther and S. G. Lee, On-chip interconnection lines with patterned ground shields, IEEE Microw. Guide Wave Lett., vol. 10, pp. 4951, Feb. 2000. [10] T. Hiraoka, T. Tokumitsu, and M. Akaike, Very small wideband MMIC magic-ts using microstrip lines on a thin dielectric lm, IEEE Trans. Microw. Theory Tech., vol. MTT-37, no. 10, pp. 15691575, Oct. 1989. [11] D. G. Swanson, Jr. and W. J. R. Hoefer, Microwave Circuit Modeling Using Electromagnetic Field Simulation. Norwood, MA: Artech House, Inc., 2003. [12] G. Gonzales, Microwave Transistor Ampliers: Analysis and Design, 2nd ed. Upper Saddle River, NJ: Prentice-Hall, 1997. [13] E. Tuncer and D. P. Neikirk, Highly accurate quasi-static modeling of microstrip lines over lossy substrates, IEEE Microw. Guide Wave Lett., vol. 2, pp. 409411, 1992. [14] R. Mongia, I. Bahl, and P. Bhartia, RF and Microwave Coupled-Line Circuits. Norwood, MA: Artech House Inc., 1999. [15] M. A. Copeland, S. P. Voinigescu, D. Marchesan, P. Popescu, and M. C. Maliepaard, 5-GHz SiGe HBT monolithic radio transceiver with tunable ltering, IEEE Trans. Microw. Theory Tech., vol. 48, no. 2, pp. 170181, Feb. 2000. [16] H. Jacobsson, B. Hansson, H. Berg, and S. Gevorgian, Very low phasenoise fully-integrated coupled VCOs, in Proc. 2002 IEEE Radio Frequency Integr. Symp., 2002, pp. 467470. [17] J.-M. Mourant, J. Imbornone, and T. Tewksbury, A low phase noise monolithic VCO in SiGe BiCOMS, in Proc. 2000 IEEE Radio Frequency Integr. Symp., 2000, pp. 6568. [18] K. W. Kobayashi, L. T. Tran, A. K. Oki, T. Blok, and D. C. Streit, A coplanar waveguide InAlAs/InGaAs HBT monolithic ku-band VCO, IEEE Microw. Guide Wave Lett., vol. 5, no. 9, pp. 311312, Sep. 1995.

and development of linearization scheme for a WCDMA transmitter. He is also involved with 900-MHz RFID transceiver development and ubiquitous 8-GHz wireless transceiver development. His research interest is RF and analog integrated circuit design.

Young-Gi Kim (M06) was born in Seoul, Korea. He received the B.S. and M.S. degrees in electronics engineering from Hanyang University, Seoul, Korea, in 1983 and 1984, respectively, and the Ph.D. degree from the University of Texas at Arlington in 1993. From 1986 to 1997, he was with Korea Telecom Research Laboratory, where he was engaged with long-distance optical ber communication and developed Monolithic Microwave Integrated Circuits for wireless application. In 1996, he moved to Anyang University, Anyang, Korea, where he is currently a Professor in the Department of Data Communication Engineering. His research interests are included radio frequency integrated circuits and devices.

Eun-Jin Lee was born in Jin-Hea, Korea, in 1980. He received the B.S. and M.S degrees in information comunication and engineering from the Anyang University, Anyang, Korea, in 2005 and 2007, respectively. He is working toward the Ph.D. degree in the College of Electrical Engineering and Computer Science, Kook Min University, Seoul, Korea. His research interests include CMOS RF circuits for wireless communication system and RFID.

Chang-Woo Kim (M93) was born in Seoul, Korea, in March, 1961. He received the B.S. and M.S. degrees in electronic engineering from the Hanyang University, Seoul, in 1984 and 1986, respectively, and the Ph.D. degree in elecronic engineering from the Shizuoka University, Hamamatsu, Japan, in 1992. From 1992 to 1996, he was with the Microelectronics Laboratories, NEC Corporation, Tsukuba, Japan, where he worked on the high-frequency and high-power heterojunction devices and ICs used for mobile and satellite communication applications. Since 1996, he has been with the Department of Radio Communication Egineering, Kyung Hee University, Gyeonggi-do, Korea, where he is a professor. From 2004 to 2005, he was a visiting professor of the Radio Communication Laboratory, University of Cincinnati, OH, USA. His research interests include microwave/mm-wave soild-state device modeling, MCIC and MMIC design, and RF characterization. Dr. Kim is a member of IEEK, KIEE, KEES, and IEICE.

Jongsoo Lee was born in Dangjin, Korea, in 1974. He received the B.S degree in physics from Chung-Ang University, Seoul, Korea, in 1999, and the M.S degree in electrical engineering from The Ohio State University, Columbus, in 2003, where he is currently working toward the Ph.D. degree From 2000 to 2006, he received Texas Instruments fellowship. As part of the requirement of his M.S. thesis, he developed inductor structures for a high-Q factor and designed a CMOS mixer. His recent work is focused on the design of a WCDMA transmitter

Patrick Roblin (M85) was born in Paris, France, in September 1958. He received the maitrise de physics degree from the Louis Pasteur University, Strasbourg, France, in 1980, and the M.S. and D.Sc. degrees in electrical engineering from Washington University, St. Louis, MO, in 1982 and 1984, respectively. In 1984, he joined the Department of Electrical Engineering, at The Ohio State University (OSU), Columbus, OH, as an Assistant Professor and is currently a Professor. His present research interests include the measurement, modeling, design and linearization of nonlinear RF devices, circuits and systems such as oscillators, mixers, and power-ampliers. He is the author of textbook on High-Speed Heterostructure Devices published by Cambridge University Press. He has developed at OSU two educational RF/microwave laboratories and associated curriculum for training both undergraduate and graduate students. He is the founder of the nonlinear RF research lab.