Microelectrnica das Telecomunicaes

Mestrado em Engenharia Electrnica

Design of a Receiver Front-End October 2013

Prof. Joo Vaz

Instituto Superior Tcnico 2013/2014

Objectives The objective of this evaluation project is to design a simple integrated radio frequency receiver front-end at schematic and layout levels. The receiver is composed by a low-noise amplifier (LNA), a voltage-controlled oscillator (VCO), and a mixer (MIX). A RF input signal will be down converted to an intermediate frequency (IF) output signal. The technology to be used is the C35B4C3 CMOS from Austria Micro Systems manufacturer. All the electrical accesses between the receiver integrated circuit and the exterior must be made using the technology available pads and respective bond wires accordingly to the following instructions. Receiver specifications Technology: CMOS 0.35um C35B4C3 from Austria Micro Systems. Input frequency (fRF): see table. Input RF source impedance: 50!. Input matching: |"IN|<-15dB. Single-ended input port. Input RF channels bandwidth: 5MHz. Input RF channels spacing: 7MHz. Intermediate frequency (IF): 100MHz. Output IF differential load impedance: 500!//4pF. Pad capacitance to ground (RF pads only): 284fF. Bond-wire inductance (RF pads only): 0.4nH. Supply voltage: 3.3V. LNA specifications Two-stage topology. Input transistor size (W1): see table. Second stage transistor size: 10um. Single-ended output port. DC decoupled output port. Output load impedance: 5k! // 74fF.

Mixer and VCO specifications Mixer topology: Gilbert cell. VCO topology: Cross-coupled differential pair and LC resonator. Mixer and VCO transistors size (W2): see table. Technology available components NMOS transistors in library PRIMLIBRF. Spiral inductors in library SPIRALS_4M. Cpoly capacitors in library PRIMLIBRF. Rpoly2 and RpolyH resistors in library PRIMLIBRF. PAD with g_padonly layout instance in library IOLIB_ANA_4M.

Work plan The work can be divided into four parts. 1) LNA design The LNA will have two stages: both stages will have a common source topology, with eventual inductive source degeneration in the first one. 1.1) Schematic level main steps Design the output stage in order to obtain an input tuned impedance with maximum value. The power gain should be maximized. Obtain the input stage transistor dimension and bias point in order to match the LNA input and minimize the noise figure as much as possible. Avoid high power bias consumption. Maximize the LNA power, available and transducer gains. The LNA should be center frequency and wideband stable. The LNA input access will have one pad and one bondwire that should be considered in the design. 1.2) Layout level Minimize the interconnections parasitic effects. All the electrical connections between the LNA and the outside world must be made using the pads frame. 1.3) Simulation results a) Input and output matching, noise figure, transducer and available gains. b) 1-dB compression point and third order intermodulation distortion. c) Repeat (a) with corners and Monte-Carlo simulations. d) Repeat (a) with post-layout simulations.

2) VCO design 2.1) Schematic level main steps Choose the local oscillator frequency with a lower value than the RF frequency. Include buffer stages at both outputs and DC decoupling capacitors. Assume the mixer LO input port differential impedance is 10k! // 135fF. Use the technology varactors to give the oscillator a tuning capability of at least 50MHz.

2.2) Layout level Minimize the interconnections parasitic effects. All the electrical connections between the LNA and the outside world must be made using the pads frame. 2.3) Simulation results a) VCO onset and steady-state output voltage in the time domain. b) VCO steady-state output voltage, power and phase-noise. c) VCO output frequency and power inside the tuning range. d) Repeat (a) and (b) with post-layout simulations. 3) Mixer design 3.1) Schematic level main steps Assure that all transistors bias points are in the saturation region. Maximize the conversion gain for the available LO power. Each mixer output port will have one pad and one bondwire that should be considered in the design. 3.2) Simulation results a) Simulate the power, available and transducer conversion gains, LO and RF ports input impedances. b) Simulate the LO-RF and LO-IF isolations. c) Repeat (a) with post-layout simulations.

4) Complete receiver design Use the previous designed blocks as they are. If necessary perform only a fine-tuning. The complete receiver layout must be placed inside a rectangular frame of pads. Pads centers should be 120um apart from each other. 4.1) Simulation results a) Simulate the overall power, available, transducer and voltage conversion gains. b) Input impedance and matching. c) Simulate the adjacent channel and image frequency rejection. d) Simulate complete noise figure. e) Simulate overall and individual blocks power consumption.

Report The final report must contain all the calculations, options and trade-offs made during the design and the respective justifications. Simulation results from the design steps and final ones should be included. All the final schematics and layouts for each block and for the final receiver must be presented. The report must include comparative simulation results for schematics and pos-layout (only when requested) in the same chart. When necessary, for an easier reading and interpretation, graphical curves should be presented in narrowband (around a center frequency) and for wideband (100MHz-6GHz).

Table The LNA specifications must be chosen in accordance with the following table. Group Name 65465 Pedro Marques 1 71069 Fbio Barroso 70583 Rben Afonso 66004 Bruno Guilherme 2 66020 Mariana Daniel 77855 Federica Pelli 3 4 5 6 68274 Tiago Padua 68448 Bruno Costa 63526 Harshit Dhirajlal 68268 Renato Encarnao 68247 Diogo Guerra 77856 Filippo Rovigatti 72506 Carlos Azevedo 2.4 2.4 1.8 1.8 10 5 10 5 5 10 5 10 3.5 5 10 3.5 10 5 fRF [GHz] W1 [m] W2 [m]