2202 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 46, NO.

6, NOVEMBER/DECEMBER 2010
A Novel High-Power-Factor Single-Switch
Electronic Ballast
John C. W. Lam, Member, IEEE, and Praveen K. Jain, Fellow, IEEE
AbstractA novel single-stage single-switch electronic ballast
topology with a unity power factor is presented in this paper. The
proposed circuit consists of an integrated buckboost stage that
operates in the discontinuous conduction mode to provide a high
power factor and a single-switch current-fed resonant inverter to
stabilize the lamp current. The proposed topology presents a low
cost and compact electronic ballast design method. The detailed
descriptions of the circuits operating principles are provided
in this paper. The design equations and mathematical analysis
regarding the proposed circuit are discussed in this paper. The
proposed ballast has been tested with an 18-W compact uores-
cent lamp, and the experimental results conrmed that a very
high power factor of 0.995 and an efciency of 83.4% have been
achieved.
Index TermsCompact uorescent lamp (CFL), electronic
ballast, power factor correction (PFC).
I. INTRODUCTION
C
OMPACT uorescent lamps (CFLs) are now becoming
more popular than the conventional incandescent light
bulbs in numerous lighting applications due to their high ef-
cacy and lumen performance. A CFL requires only one-third
of the power consumed by an incandescent lamp to provide the
same amount of light output [1]. The operating principles of a
CFL are similar to the operating principles of T5, T8, or T12
uorescent lamps. Magnetic ballasts were conventionally used
in uorescent lighting because they are simple and inexpensive.
However, the fact that they operate at line frequency implies
that the device itself is heavy and large. Due to the size of
a CFL, the bulky nature of the magnetic ballast also makes
it impossible for use in CFL applications. Furthermore, when
the uorescent lamp is operating at line frequency, a ickering
noise is observed, and the light efcacy is very low. By using
advanced electronics circuits, the ballast can operate at higher
operating frequencies (> 20 kHz), and as a result, the size of
the ballast can be signicantly smaller than that of a magnetic
ballast while also achieving a higher light efcacy. Therefore,
Manuscript received December 15, 2007; accepted February 8, 2010.
Date of publication August 30, 2010; date of current version November 19,
2010. Paper MSDAD-ILDC-0803, presented at the 2007 Industry Applications
Society Annual Meeting, New Orleans, LA, September 2327, and approved
for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS
by the Industrial Lighting and Displays Committee of the IEEE Industry
Applications Society.
The authors are with the Queens Centre for Energy and Power Electron-
ics Research, Queens University, Kingston, ON K7L 3N6, Canada (e-mail:
john.lam@ece.queensu.ca; praveen.jain@.queensu.ca).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TIA.2010.2071131
Fig. 1. Conventional two-stage high-power-factor electronic ballast with
boost PFC.
Fig. 2. Single-stage electronic ballast with boost PFC [3].
high-frequency electronic ballasts are promising solutions for
compact uorescent lighting applications.
A conventional high-power-factor electronic ballast circuit
is shown in Fig. 1; it consists of a boost front-end converter
to perform the power factor correction (PFC) and a half-
bridge voltage-fed resonant inverter to control the lamp current.
Although this approach can achieve a high power factor at
the input and ensure a low lamp crest factor (CF) at the
output, it requires three MOSFETs in the power circuit and two
controllers in the overall system. The resulting circuit is costly
and too large to be practical in CFL applications. In addition,
the two-stage approach lowers the power conversion efciency.
To reduce the size and cost of the ballast power circuit, var-
ious single-stage resonant inverters have been introduced by
combining the active PFC stage and the resonant inverter stage
to create a more efcient ballast circuit [2][9]. Most of the
PFC stages associated with the aforementioned ballasts operate
in a discontinuous conduction mode (DCM) because feedback
loops are not required for the power factor control. In [2]
[6], the authors designed several single-stage high-power-factor
electronic ballasts by integrating different active PFC circuits
with a voltage-fed half-bridge parallel resonant inverter [10].
Figs. 2 and 3 show two examples of single-stage electronic
ballast topologies that use the voltage-fed half-bridge inverter.
Fig. 2 shows a single-stage inverter with a boost PFC [2], [3],
and Fig. 3 shows a single-stage inverter with a yback PFC [4].
0093-9994/$26.00 2010 IEEE
LAM AND JAIN: A NOVEL HIGH-POWER-FACTOR SINGLE-SWITCH ELECTRONIC BALLAST 2203
Fig. 3. Single-stage electronic ballast with yback PFC [4].
The features and performance of these two circuits have been
discussed and compared in [7]. Both topologies are capable of
achieving a high power factor at the input. However, the shared
switch in the single-stage inverter with a boost PFC suffers
from a higher voltage stress than the circuit in [4]. Hence, the
DCM boost PFC limits its application to countries that have a
high line voltage range (e.g., 220 V). A current-fed pushpull
resonant inverter variation of the single-stage electronic ballast
was proposed in [8]. The advantage of this circuit is that it
does not require any isolation device in the MOSFET driver
circuit since the source of the two MOSFETs is referenced to
the ground. However, the magnetic complexity is quite high
at the inverter stage with this topology. Another single-stage
electronic ballast variation based on a single input inductor
current-fed resonant inverter was later proposed in [9]. The
circuit in [9] does not require a transformer at the inverter stage,
and at the same time, it also offers the same advantages as the
circuit in [8]. However, the inverter stage of the circuit in [9]
must operate belowresonance in order to minimize the recovery
loss in the diodes and the switching losses in the MOSFET [11].
In addition, the voltage stress across the MOSFET is higher
than the voltage stresses observed in the voltage-fed half-bridge
inverter topologies.
To further reduce the cost and size of the ballast power cir-
cuit, some single-switch electronic ballasts have been proposed
and discussed in the literature [12][14]. The existing single-
switch topologies all suffer from high voltage stress and/or high
current stress across the switch. This paper proposes a new
single-stage single-switch electronic ballast that can achieve
a unity power factor for CFL applications. Compared to the
circuit presented in [9], the proposed circuit saves one MOS-
FET and a diode at the inverter stage. It also has lower voltage
and current stresses across the MOSFET than all the other
referenced topologies. Since only one MOSFET is required in
the proposed circuit, the conduction loss of the overall circuit
is lower than that in [9]. A high power factor is achieved in the
proposed circuit by using a buckboost circuit that operates in
the DCM. The detailed explanations of the circuits operating
principles will be discussed in this paper.
This paper is organized as follows. Section II presents the
derivation of the proposed single-switch electronic ballast. The
detailed explanations of the circuit characteristics will also be
given in this section. Section III illustrates the design process
of the circuit through a design example for an 18-W CFL. This
section provides all the simulation and experimental waveforms
to conrm the validity of the theoretical analysis and design
procedure. Section IV gives a conclusion to summarize the
merits of this paper.
II. DESCRIPTIONS OF PROPOSED CIRCUIT
The proposed single-stage ballast circuit is derived by com-
bining a buckboost converter with a single-switch current-
fed resonant inverter. Fig. 4(a) shows the initial circuit design
where the buckboost converter is connected to the input of
the single-switch current-fed resonant inverter. The lamp at the
output of the inverter stage is modeled as a power-dependent
resistor (R
lamp
), where r
l
represents the laments of the lamp.
Fig. 4(b) shows the intermediate step of the proposed circuit
derivation. Since the source terminals of the two switches (M
pfc
and M
s1
) share the same node, the two switches can be replaced
by a single switch to obtain the nal circuit. Fig. 4(c) shows the
nal design of the proposed single-stage single-switch circuit
where the dotted line highlights the integrated buckboost PFC
stage. Figs. 5 and 6 illustrate the operating principles of the
circuit and the key waveforms, respectively. The operating
stages of the proposed electronic ballast, as shown in Fig. 5,
are discussed in the following list.
[Stage 1:] During this stage, M
s1
is on, diode D
in
conducts,
and inductor L
b
begins to charge. Current i
Lb
rises linearly.
When M
s1
is on, diode D
1
is forced to turn on at the same
time. As a result, i
sn
begins to increase due to the presence
of L
in
. To minimize the switching turn-off loss, the size of
inductor L
in
should be small enough so that i
sn
will return
to zero before the MOSFET turns off. At this stage, the
total current owing through M
s1
is i
s1
, which is equal to
the sum of i
Din
and i
sn
.
[Stage 2:] The gate signal to the MOSFET V
G
goes to zero,
and M
s1
turns off, which forces diode D
in
to turn off. As
a result, D
b
begins to conduct, and i
Lb
decreases linearly
through the loop D
b
, C
b
, and L
b
. Due to the presence of
the parallel capacitance (C
oss
) of the MOSFET, v
ds
rises
slowly, which helps to reduce the turn-off switching losses
of the MOSFET.
[Stage 3:] At this stage, i
in
decreases to zero, which indicates
the start of the discontinuous period of the inductor cur-
rent. Meanwhile, D
1
is still off, and the resonant circuit
continues to deliver the required energy to the lamp.
When the buckboost converter operates in the DCM, the
peak of the inductor L
b
current will follow the rectied sinu-
soidal voltage from the line. The average input line current can
then be analyzed as follows: Let v
s
(t) = V
p
sin(
L
t) be the line
voltage, where V
p
and
L
represent the amplitude of the line
voltage and angular line frequency, respectively. According to
Fig. 4(a), the average current after the rectier is equal to the
average current across the switch. The average line current is
then obtained to be (1), where i
Lb,pk
is determined to be (2)
according to Fig. 6
i
s,avg
(t) =
i
Lb,pk
t
ON
2T
s
=
V
p
D
2
T
s
2L
b
sin(
L
t) (1)
i
Lb,pk
(t) =
V
p
sin(
L
t)DT
s
L
b
. (2)
Since it can be observed from (1) that the line current is in
phase with the line voltage, the DCM buckboost converter
2204 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 46, NO. 6, NOVEMBER/DECEMBER 2010
Fig. 4. Derivation of proposed single-switch high-power-factor electronic ballast. (a) Initial design. (b) Circuit derivation. (c) Final design of proposed
circuit.
can therefore achieve a very high power factor. Unlike the
DCM boost PFC circuit, the MOSFET does not suffer from
high voltage stress in order to achieve PFC [15]. The average
power of the buckboost PFC stage is obtained by averaging the
instantaneous power given by the line voltage and the average
input current. The average power equation is shown in (3).
The dc-bus voltage (v
dc
), across the capacitor C
b
, is given by
(4), where R
inv
represents the mean input resistance of the
inverter stage and D is the steady-state duty ratio. To ensure
that the lamp CF is maintained to be below the maximum value
according to the standard set by the American National Stan-
dards Institute (ANSI) [16], C
b
should be designed according
to the maximum allowable dc ripple voltage (|v
rip
|) across C
b
.
The voltage ripple across C
b
for a buckboost PFC circuit is
given in (5). From (5), C
b
can then be expressed as a function
of |v
rip
| as shown in (6), where V
dc
is the average dc-bus
voltage, P
avg
is the average input power, and f
L
is the line
frequency
P
avg
=
1

_
0
V
p
sin(
L
t)
V
p
D
2
T
s
2L
b
sin(
L
t)d(
L
t) =
V
2
p
D
2
T
s
4L
b
(3)
v
dc
=D
_
R
inv
T
s
2L
b
(4)
v
rip
=
1
C
b
_
i
Cb
dt =
P
avg
4f
L
C
b
V
dc
sin(4f
L
t) (5)
C
b
=
P
avg
2f
L
|v
rip
|V
dc
. (6)
LAM AND JAIN: A NOVEL HIGH-POWER-FACTOR SINGLE-SWITCH ELECTRONIC BALLAST 2205
Fig. 5. Operating stages of proposed electronic ballast.
A. Resonant Circuit Analysis
The proposed single-switch inverter uses an input choke
inductor (L
in
) to create the current-fed resonant inverter. The
resonant circuit consists of three components: the resonant
inductor (L
r
), the resonant capacitor (C
r
), and the starting in-
ductor (L
p
). During the lamp preheat stage, the lamp resistance
is innite, and the resonant circuit becomes a parallel LC
network. The preheat frequency during the lamp-ignition phase
is given by (7), where i
pre
is the preheat current. The preheat
voltage is given by (8). The lamp-ignition frequency (f
ign
) is
derived using (8), and the nal expression is given by (9), where
V
ign
is the amplitude of the lamp-ignition voltage and I
sn
is the
average current of i
sn
f
pre
=
v
pre
2(L
r
+L
p
)i
pre
(7)
v
pre
=
_
2f
pre
L
p
1 (2f
pre
)
2
(L
r
+L
p
)C
r
_
i
sn
(8)
f
ign
=
_
_
L
p
I
sn
V
ign
_
2
4(L
r
+L
p
)C
r

L
p
I
sn
V
ign
4(L
r
+L
p
)C
r
. (9)
After the lamp ignition, the lamp resistance becomes a nite
value. The corner frequency and quality factor of the resonant
circuit are dened by (10) and (11), respectively, shown at
the bottom of the next page. By selecting a high enough Q
in the resonant circuit, the resonant circuit lters out most of
the harmonics generated by the input current (i
sn
), and a high-
quality sinusoidal waveform can be obtained at the output.
By applying fundamental approximation to the resonant circuit
and assuming that the losses in the passive circuit components
are negligible, the output-to-input current-gain equation can be
obtained as given in (12), shown at the bottom of the next
page. In (12),
r
=
s
/
o
represents the relative operating
angular frequency, where
s
represents the angular switching
frequency, and k = L
p
/L
r
. The voltage-gain equation is then
obtained by assuming the resonant circuit to be a lossless circuit
network. Hence, i
sn
v
in
i
out
v
out
, and the voltage-gain equa-
tion is the inverse of (12). The voltage-gain plot is displayed
in Fig. 7 for illustration purposes. Fig. 7 illustrates that, when
Q is low (i.e., the lamp resistance is innite), a high output
voltage can be provided to the lamp during the lamp-ignition
process. It also shows that, when Q is high (i.e., the lamp
resistance drops after startup), the output voltage decreases
2206 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 46, NO. 6, NOVEMBER/DECEMBER 2010
Fig. 6. Key waveforms of proposed electronic ballast.
to its rated value during steady-state operation. To gain more
insight regarding the resonant characteristic of the proposed
inverter, the input impedance expression has been examined
and is expressed by (13), shown at the bottom of the page. The
magnitude of the input impedance |Z
in
(
r
)| is given by (14),
shown at the bottom of the page, and the phase angle of the
input impedance
Zin
(
r
) is given by (15), shown at the bottom
of the page. Fig. 8 shows the plot of (15), and it is used to
study the resonance point of the proposed circuit. The resonant
frequency f
res
is obtained by noting that f
res
is the frequency at
which
Zin
(
r
) becomes zero. It denes the boundary between
the capacitive and inductive regions of the resonant circuit. The
Fig. 7. Voltage-gain plot of resonant circuit.
resonant frequency can be expressed as a function of the corner
frequency Q and k; the resultant expression is given by (16),
shown at the bottom of the page. Through (16), it is observed
that the resonant frequency shifts as Q changes. In the actual
design, the resonant frequency should be chosen according to
the Q value at the full lamp power condition.
B. Current and Voltage Stress Analysis
The main disadvantage of a single-switch inverter topology
is the possible high current and voltage stresses imposed on
the power MOSFET. This means that a large heat sink or
careful circuit layout design is required in the power circuit.
High current stress also leads to high conduction loss in the
switch and can lower the power efciency of the circuit. Hence,
it is worthwhile to perform the stress analysis on the power
f
o
=
1
2

L
r
C
r
(10)
Q =
2f
o
L
r
R
lamp
(11)

i
out
i
sn,1

=
1
_
(1
2
r
)
2
+
_

r
Q
_
1 +
1
k
_

1
Qk
r
_
2
(12)
Z
in
(j) =
1
jC
r
_
_
_
_
_
_
jL
r
+
jL
p
R
lamp
R
lamp
+jL
p
_
=
R
lamp
_

2
r
Q
2
k +j
r
(1 +k)Q
_
(1
2
r
(1 +k)) +j(
r
Qk) (1
2
r
k)
= |Z
in
()| e
j()
(13)

Z
in
()
R
lamp

2
r
Q
2
k +j
r
(1 +k)Q
_
(1
2
r
(1 +k)) +j(
r
Qk)(1
2
r
k)

(
2
r
Q
2
k)
2
+ (
r
(1 +k)Q)
2
(1
2
r
(1 +k))
2
+ (
r
Qk)
2
(1
2
r
k)
2
(14)

Zin
(
r
) = tan
1
_
Q(1 +k)
r

2
r
Q
2
k
_
tan
1
_
Qk
r
(1
2
r
)
1 (1 +k)
2
r
_
(15)
f
res
(Q, k) =f
o

(1 +k)
2
+ (Qk)
2
+
_
((1 +k)
2
(Qk)
2
)
2
+ 4(Qk)
2
(1 +k)
2(Qk)
2
(16)
LAM AND JAIN: A NOVEL HIGH-POWER-FACTOR SINGLE-SWITCH ELECTRONIC BALLAST 2207
Fig. 8. Phase plot of resonant circuit.
switch in the proposed circuit. The main difference between the
proposed topology and the well-known class-E inverter [14] is
that the resonant current, which is usually high in magnitude,
does not ow through the switch when the switch is on due
to the presence of diode D
1
. As mentioned earlier, the total
current owing through the switch M
s1
is the sum of i
sn
and
i
Din
. The conduction loss of the switch is given by (17), shown
at the bottom of the page, where r
ds
is the ON-resistance for
the MOSFET, i
sn,rms
is the rms value of i
sn
, and i
Din,rms
is the rms value of i
Din
. i
Din,rms
is determined by rst taking
the average of the square of i
Din
over the switching period and
then averaging it over the ac line period [17], as shown in (18),
shown at the bottom of the page. i
sn,rms
can be determined by
assuming that the harmonics in the resonant circuit are negli-
gible so that the voltage across capacitor C
r
is approximately
given by v
cr
V
op
sin(
s
t +
Vcr
), where V
op
is the amplitude
of the output voltage and
Vcr
is the phase difference between
Fig. 9. Equivalent circuit at the input side.
the output voltage and the voltage of capacitor C
r
. i
sn,rms
is
then given in (19), shown at the bottom of the page.
Since i
sn
decreases to zero before the end of the conduction
time of the MOSFET, the MOSFET peak current is simply
determined by i
Lb,pk
, as shown in (20), shown at the bottom
of the page. The voltage across the MOSFET within one
switching cycle simply equals to the difference between the dc-
bus voltage (v
dc
) and v
cr
as shown in (21), shown at the bottom
of the page, where
Vcr
is given by (22), shown at the bottom
of the page.
C. Input Filter Design
The input lter at the rectier stage is designed according to
the analysis given in [18] and [19]. Fig. 9 shows the simplied
circuit at the input side with the LC input lter. The purpose
of this lter is to obtain the average current of the DCM current
that appears across L
b
so that a clean sinusoidal line current
with a low ripple can be achieved. From Fig. 9, the cutoff
frequency (f
c
) of the input lter, which is dened in (23),
should be around 1/10 of the switching frequency in order to
lter out the high-frequency components in i
pfc
. Although C
i
helps to perform the ltering function, it can introduce a phase
shift between v
s
and i
s
that affects the input power factor if its
value is not chosen properly. Since the detailed analysis of the
design for C
i
has been discussed in [19], only the nal design
equation will be given in this paper as shown in (24), where
p
cond_loss
=r
ds
i
2
ds,rms
= r
ds
(
_
i
sn,rms
+i
Din,rms
)
2
(17)
i
Din,rms
=

_
1

_
0
_
_
1
T
s
T
s
_
0
i
2
Din
d(t)
_
_
d(
L
t) =

_
1

_
0
_
I
2
pk
D
3
_
d(
L
t) =
D
3/2
T
s
V
p

6L
b
(18)
i
sn,rms
=

_
1
T
s
T
s
_
0
i
2
sn
d(t) =

_
1
T
s
t
ON
_
0
_
v
dc
v
cr
(t)
L
un
_
2
d(t)
=

1
L
in
_
v
2
dc
D +v
dc
V
op
cos(2D +
Vcr
)

V
op
2
cos(
Vcr
) +V
2
op
_
D
2

1
4
[sin(4D + 2
Vcr
) sin(2
Vcr
)]
__
(19)
i
ds,pk
=i
Lb,pk
= i
sn,pk
+i
Din,pk
=
DT
s
V
p
L
b
(20)
v
ds
=v
dc
v
cr
= v
dc
V
op
sin(
s
t +
Vcr
) for t
ON
t T
s
(21)

Vcr
= tan
1
_
1 +k

r
kQ
_
90
0
(22)
2208 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 46, NO. 6, NOVEMBER/DECEMBER 2010
TABLE I
CIRCUIT PARAMETERS
DPF represents the displacement power factor and I
p
is the
amplitude of the input current
f
c
=
1
2

L
i
C
i
(23)
C
i,max
=
I
p
2f
L
V
p
tan
_
cos
1
(DPF)
_
. (24)
III. DESIGN EXAMPLE AND EXPERIMENTAL RESULTS
A design example is given in this section to validate the
theoretical analysis discussed in the previous section. An 18-W
CFL is chosen as the test load, and its lamp resistance is
calculated in (25). The tested line voltage range is 85120 V
rms
in 60 Hz. The resonant circuit components are designed for the
chosen Q value so that the proper lamp-ignition voltage will be
provided for the lamp startup process. From the inspection of
Fig. 7, it can be seen that the switching frequency should be
chosen to be below the corner frequency to ensure that a high
voltage gain is guaranteed when Qis low. At the same time, the
switching frequency should be above the resonant frequency
to minimize the voltage and current stresses of the switch.
The corner frequency is chosen to be 85 kHz to minimize the
resonant inductor size. With Q chosen to be one and k 3,
f
res
is calculated to be 52 kHz from (16). Given the corner and
resonant frequencies, the switching frequency is subsequently
chosen to be 70 kHz for this design. The nal values of L
r
and
C
r
are then calculated as shown in (26) and (27), respectively.
With k 3 chosen for the design, the starting inductor for the
lamp ignition L
p
is selected to be 3.9 mH. From these circuit
parameters, the lamp-ignition frequency is then determined to
be 42 kHz according to (9).
R
lamp
is rst calculated as shown in (25) using the lamp rated
current I
out
and rated power P
out
R
lamp
=
P
out
I
2
out
=
18 W
(0.16 A)
2
= 700 . (25)
The values of L
r
and C
r
are then obtained as follows:
L
r
=
QR
lamp
2f
o
=
(1)(700 )
2(85 kHz)
1.3 mH (26)
C
r
=
1
(2f
o
)
2
L
r
=
1
(285 kHz)
2
(1.3 mH)
2.7 nF. (27)
In the buckboost PFC circuit, the inductor L
b
can be deter-
mined according to the average power equation in (3). In this
Fig. 10. Simulated waveforms: line and lamp currents.
Fig. 11. Simulated waveforms: v
ds
, i
Lb
, and i
sn
.
Fig. 12. Simulated dc-bus voltage.
design example, the maximum D is selected to be 0.36 with
V
p
= 155 V and f
s
= 70 kHz; L
b
is then calculated to be
0.65 mH from (28). Since the buckboost circuit is operating
in the DCM, the minimum v
dcmin
should follow (29), which is
determined to be 88 V in this case. The capacitor C
b
is designed
according to the ripple voltage specied in v
dc
. A ripple voltage
which is 20% of v
dc
is chosen in this design. The minimum C
b
is then calculated according to (30). In the prototype, 33 F
is used
L
b,max
=
V
2
p
d
2
T
s
4P
avg
=
(155 V)
2
0.36
2
(1/70 kHz)
4(18 W)
= 0.65 mH (28)
LAM AND JAIN: A NOVEL HIGH-POWER-FACTOR SINGLE-SWITCH ELECTRONIC BALLAST 2209
Fig. 13. Measured lamp voltage and current during lamp startup (v
out
: 200 V/div; i
out
: 0.2 A/div; time: 500 ms/div).
Fig. 14. (a) Measured lamp voltage and current waveforms within low-frequency cycle (v
out
: 200 V/div; i
out
: 0.2 A/div; time: 5 ms/div). (b) Measured lamp
voltage and current waveforms (v
out
: 200 V/div; i
out
: 0.2 A/div; time: 20 s/div).
v
dc

DV
p
1 D
= 88 V (29)
C
b,min
=
18 W
2(60 Hz)(18 V)(88 V)
= 25 F. (30)
The peak current owing through the MOSFET can be deter-
mined from (20) as shown in (31), with L
b
obtained earlier
in (28). The rms current of i
ds
is determined to be 0.6 A
according to (17); hence, the MOSFET model STP4NK60Z
from STMicroelectronics is used in the prototype
i
ds,pk
=
DT
s
V
p
L
b
=
0.36(1/70 kHz)155 V
0.65 mH
= 1.22 A. (31)
For the input lter design, C
imax
is rst determined to be 0.1 F
according to (24), with V
p
= 155 and I
p
= 0.23 since the
average input should be 18 W. Then, L
i
is determined to be
4.7 mH from (23). In the experimental prototype, L
i
is 2.7 mH,
and C
i
is 47 nF.
A. Simulation Results
To verify the functionality of the proposed design, the circuit
was rst simulated in PSIM 7.0. Table I summarizes the circuit
parameters and the component part numbers that have been
used in both the simulation and the experimental prototype.
The lamp model used in the simulation is a power-dependent
model that has been presented in [20]. For the 18-W CFL, the
lamp-ignition voltage was determined to be 290 V
rms
. Fig. 10
shows the line current and the lamp current of the proposed
circuit. The power factor is 0.996. Fig. 11 shows the simulated
steady-state MOSFET voltage and currents i
sn
and i
Lb
. The
waveforms are very similar to the waveforms obtained in the
theoretical section. Fig. 12 shows the dc-bus voltage.
2210 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 46, NO. 6, NOVEMBER/DECEMBER 2010
Fig. 15. Line current and line voltage (v
s
: 100 V/div; i
s
: 0.2 A; i
out
: 0.2 A; time: 10 ms/div).
Fig. 16. MOSFET voltage (v
ds
), inductor L
b
current (i
Lb
), and inverter input current (i
sn
) (v
ds
: 100 V/div; i
Lb
: 0.5 A/div; i
sn
: 0.3 A/div; time: 5 s/div).
Fig. 17. DC-bus voltage (v
dc
: 50 V/div; time: 5 ms/div).
B. Experimental Results
An experimental prototype with a diameter of 55 mm was
built to verify the simulation results. Fig. 13 shows the lamp
current and voltage waveforms at startup. It shows that a suc-
cessful lamp ignition is achieved, and it therefore supports the
theoretical calculations discussed in Section II. Fig. 14 shows
the lamp current and voltage waveforms after startup and the
circuit steady-state operating waveforms. The lamp current CF
was measured to be 1.56 from Fig. 14(a). Fig. 15 shows the
line voltage and the line current; it can be observed that a
power factor of 0.995 is obtained. The total-harmonic-distortion
level measured from the line current is less than 6.5%. Fig. 16
shows the steady-state switch voltage v
ds
, the DCM inductor
L
b
current, and the input current to the resonant circuit (i
sn
).
Fig. 17 shows the measured dc-bus voltage, and its average
value is measured to be 94 V. All the measured waveforms
have been observed to be consistent with the simulation results.
The overall efciency is measured to be 83.4% at the nominal
line voltage. The efciency numbers have been obtained by
multiplying the lamp current and lamp voltage waveforms,
averaging them over a few line cycles, and nally dividing
the power by the average input power. Much of the power
loss is due to the power dissipation from the power switch
and the inductor (L
in
) core losses. Table II shows the power
factor measurement obtained from different line voltages. It is
observed that the power factor changes slightly when the line
voltage changes, but a value of at least 0.98 was achieved for
the specied range of line voltages.
IV. CONCLUSION
A novel single-switch single-stage electronic ballast with a
unity power factor has been presented in this paper for CFL
applications. The proposed circuit has a low cost and compact
ballast design. The presented approach uses a buckboost PFC
that eliminates the need for a high-voltage large-size dc-bus
capacitor in the DCM boost PFC case. In order to minimize
LAM AND JAIN: A NOVEL HIGH-POWER-FACTOR SINGLE-SWITCH ELECTRONIC BALLAST 2211
TABLE II
POWER FACTOR PERFORMANCE
the switching losses, zero-current switching is guaranteed at the
turn-on of the MOSFET in the proposed circuit. Stress analysis
has been preformed, and all the circuit characteristics have been
analyzed in this paper. A design example for an 18-W CFL has
been provided to highlight and verify the performance of the
proposed circuit. The results have shown that both the voltage
and current stresses of the MOSFET have been signicantly
improved compared to that of the referenced topologies. Both
the simulation and experimental results have shown that a very
high power factor and a good efciency can be obtained by
using the proposed circuit.
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John C. W. Lam (S04M06) received the B.Sc.
(with rst class honors), M.Sc.E. and Ph.D. degrees
in electrical engineering from Queens University,
Kingston, ON, Canada, in 2003, 2006, and 2010,
respectively.
As a MITACS Industrial Fellow, he is currently
working with industrial partner Cistel Technologies
at the Queens Centre for Energy and Power Elec-
tronics Research (ePOWER). His research interests
include high power factor electronic ballasts for uo-
rescent lamps and digital control techniques in high-
frequency resonant inverters. He has published over 15 technical (journal and
conference) papers and has two patents pending.
Dr. Lam was the recipient of the Ontario Graduate Scholarship in 20032004
and 20082009. He is a member of the IEEE Power Electronics and IEEE
Industry Applications Societies.
Praveen K. Jain (S86M88SM91F02) re-
ceived the B.E. (with honors) degree from the Uni-
versity of Allahabad, Allahabad, India, in 1980, and
the M.A.Sc. and Ph.D. degrees from the University
of Toronto, Toronto, ON, Canada, in 1984 and 1987,
respectively, all in electrical engineering.
From 1980 to 1981, he was a Design Engineer
and Production Engineer with Brown Boveri Com-
pany and Crompton Greaves Ltd., Mumbai, India,
respectively. He also has considerable consulting
experience within industry. From 1987 to 1989, he
was with Canadian Astronautics, Ltd., Ottawa, ON, Canada, where he played a
key role in the design and development of high-frequency power-conversion
equipment for the Space Station Freedom. From 1989 to 1994, he was a
Technical Advisor with the Power Group, Nortel Networks, Ottawa, where
he provided guidance for the research and development of advanced power
technologies for telecommunications. From 1994 to 2000, he was a Professor
at Concordia University, Montreal, QC, Canada, where he was engaged in
teaching and research in the eld of power electronics. In addition, he has
consulted with Astec, Ballard Power, Freescale, General Electric, Intel and
Nortel. He is also a Founder of CHiL Semiconductor, Tewksbury, MA, and
SPARQ System, Kingston, ON, Canada. He is currently a Professor
and the Canada Research Chair of the Department of Electrical and Com-
puter Engineering at Queens University, Kingston. He is also currently the
Director of the Queens Centre for Energy and Power Electronics Research,
Queens University. He has secured over $20 million cash and $20 million in
kind in external research funding to conduct research in the eld of power
electronics. He has supervised more than 75 graduate students, Postdoctoral
Fellows, and research engineers. He has published over 350 technical papers
(including more than 90 IEEE TRANSACTIONS papers) and is the holder of over
50 patents (granted and pending).
Dr. Jain is an Associate Editor of the IEEE TRANSACTIONS ON POWER
ELECTRONICS and an Editor of the International Journal of Power Electronics.
He is an Associate Editor for the KIPE Journal of Power Electronics. He
is recognized as a Distinguished Lecturer of the IEEE Industry Applications
Society. He is a Fellow of the Engineering Institute of Canada and the Canadian
Academy of Engineering. He was also a recipient of the 2004 Engineering
Medal (R&D) from the Professional Engineers of Ontario.