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Transactions Briefs__________________________________________________________________
Improved Switched Tuning of Differential CMOS VCOs
Henrik Sjland or leaves it floating, whereas the other plate is connected to the resonance tank of the oscillator. The switched capacitors can be arranged in a binary weighted array, so the tuning can be performed by a digital control word, see Fig. 1. The frequency synthesizer must be able to adjust the binary control word in addition to the continuous control voltage. It is shown in [4] how this can be done. An analysis of the switched frequency tuning circuit is presented in Section II. Based on this analysis, a new improved switched frequency tuning for differential CMOS circuits is introduced in Section III. Transistor layout aspects are discussed in Section IV. II. PERFORMANCE LIMITATIONS The most important performance measures are the quality factor of the tuning circuit at the frequency of operation, and the ratio of the maximum to minimum capacitance. The quality factor is important because the total quality factor of the resonance tank limits the phase noise performance of an oscillator, whereas the capacitance ratio is important as it limits the achievable tuning range. The performance of varactors for continuous frequency tuning has been investigated, in, e.g., [5], but little work is done on switched tuning. The circuit has two states, ON and OFF, and we first analyze the circuit when the transistor is switched ON. Since no dc current is flowing through the capacitor and thereby the transistor, its drain-source dc voltage equals zero. The transistor, therefore, operates in the triode region, and can be replaced by a resistor equal to rds0 . The quality factor of the resulting series RC-link is, thus, equal to

AbstractVaractors for continuous frequency tuning are typically used in LC-oscillators. However, they have some drawbacks for large tuningranges, such as high tuning sensitivity causing high sensitivity to noise and disturbances on the control voltage. Furthermore, large metaloxidesemiconductor (MOS) varactors have high conversion of harmless amplitude noise into harmful phase noise. To reduce these problems a small varactor can be used in combination with MOS-transistors that switch fixed capacitors in and out of the oscillator. The limitations due to the imperfect complementary metaloxidesemiconductor (CMOS) switches are investigated, and an improved structure for use with the popular differential CMOS LC-oscillator is presented. Index TermsComplementary metaloxidesemiconductor (CMOS), differential, frequency tuning, oscillator, RF CMOS, switched tuning, varactor, voltage-controlled oscillator (VCO).

I. INTRODUCTION Oscillators with low-phase noise and power consumption are needed in modern wireless communication systems. For cost and miniaturization reasons the oscillators should be fully integrated, preferably on the same chip as the rest of the transceiver circuitry. To achieve the lowest cost and the possibility to integrate the analog circuitry together with the digital, a standard complementary metaloxidesemiconductor (CMOS) process should be used. Fully integrated CMOS oscillators outperforming discrete modules in terms of phase noise and power consumption have recently been reported [1]. When manufacturing oscillators in a standard CMOS process, the oscillation frequencies will have a large spread due to process variations. Capacitances will typically have a variation of tens of percents. To ensure coverage of the desired frequencies, a large tuning range is needed. Furthermore, if the tuning-range is large enough, a single oscillator can be used to cover more than one frequency band. To achieve a large tuning range is, however, often difficult. The fixed capacitance from transistor and metal routing parasitics is often considerable. This leaves little room for an additional variable capacitance (varactor) with a limited ratio between the highest and the lowest capacitance. If we, despite this, manage to design an oscillator with a wide tuning range, we will have problems with phase noise. Noise and disturbances on the control voltage will be translated into phase noise and sidebands. With continuous frequency tuning, a large tuning range corresponds to a high tuning sensitivity, which increases the problem. Furthermore, the nonlinearities of the varactor convert harmless amplitude noise into phase noise [2], and the larger the varactor the larger the conversion. To reduce these problems a small varactor can be used in combination with MOS-transistors that switch fixed capacitors in and out of the oscillator [1], [3]. A negative-channel metaloxidesemiconductor (NMOS) transistor switches one plate of the fixed capacitor to ground

Q=

2fCrds0

(1)

This expression is valid only if the transistor operates in triode, so we must now check when this is the case. The signal voltage from the resonance tank entering the tuning circuit is divided between the capacitor and the resistor (transistor). It can be shown that the voltage across the resistor, VR , is less than the input voltage divided by Q. The transistor leaves the triode region when its drain-source voltage (Vds ) exceeds its gate-source voltage (Vgs ) minus the threshold voltage (Vt ). In this case, Vgs equals the supply voltage Vdd , and the oscillation amplitude, A0 , of an oscillator is typically less than Vdd

VR  A0 = Vdd Q Q VR < Vgs 0 Vt = Vdd 0 Vt

1 1

dd ) VQ

< Vdd 0 Vt
(2)

Vdd ) Q > Vdd 0 Vt :

If for instance the threshold voltage is equal to half the supply voltage, (2) tells us that (1) is valid if the quality factor is higher than two. As we will soon see, the quality factor will in most cases be much higher than that, and (1) will be valid in most practical cases. It will, therefore, be assumed to be valid for the rest of the paper. Using a simple transistor model, the ON resistance of the transistor can be calculated as
1 W rds0 = ; gds0 = Cox (Vgs 0 Vt ) (3) gds0 L where ; Cox ; W , and L are the mobility, gate oxide capacitance per

Manuscript received September 10, 2001; revised May 23, 2002. This paper was recommended by Associate Editor G. Cauwenberghs. The author is with the Department of Electroscience, Lund University, SE-221 00 Lund, Sweden (e-mail: henrik.sjoland@es.lth.se). Publisher Item Identifier 10.1109/TCSII.2002.801415.

area, width, and length of the transistor. Only the transistor dimensions (width and length) can be changed by the circuit designer, and

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Fig. 1.

Binary weighted array of switched capacitors.

to achieve a high quality factor the transistor should be as wide and as short as possible. The minimum length should be used for best performance, whereas a compromise between tuning range and quality factor will determine the width. When the transistor is turned OFF, the conductance gds0 will be negligibly small. The transistor impedance is instead dominated by the capacitance from drain to bulk and gate (which was neglected in the ON state). The drainbulk capacitance Cdb is due to the reverse biased pn-junction formed by the p-doped substrate and the n-doped drain, whereas the gatedrain capacitance Cgd is due to the overlap between gate and drain. In modern CMOS processes, the sum of these capacitances often approximately equals the gatesource capacitance Cgs . The capacitance of the tuning circuit seen by the oscillator when the transistor is OFF, COFF , is the series connection of the capacitor being switched and the drain capacitance Cd of the transistor (Cd Cdb Cgd ). The drain capacitance is proportional to the width of the transistor. A wide transistor thus increases the quality factor but reduces the tuning range, leading to a compromise. Since (1) contains the frequency in the denominator it will be increasingly difficult to obtain a good compromise at higher frequencies. The achievable performance can be related to the ratio of the transistor transition frequency ft to the operating frequency

Fig. 2.

Simulated g

and g

versus V

for a 100/0.25-m MOS transistor.

CC 1C = CON 0 COFF = C 0 C +C CC COFF COFF C +C = C (C + Cd) 0 C 1 Cd = C

1 1

g ft = m 2C

(4)

Q1

1C COFF

= 2fr1 = gm 1 1 1 Cg ds0 Cd 2fCg gm rds0 Cd

t 1 gds0 1 Cg =f f gm Cd
(6)

C 1 Cd

Cd

(5)

1C is the difference in capacitance between the ON and OFF state.

where gm is the transconductance of the transistor in saturation and

The left-hand expression of (6) is used as a performance measure. The capacitance ratio Cg =Cd is approximately equal to unity in modern CMOS processes, but gds0 =gm which is equal to unity in the long channel low electric field situation, can be substantially larger for shortchannel devices with high gate voltages. In such a situation, disregarding this term in (6) would lead to an underestimation of the achievable performance. There are different mechanisms causing the gds0 =gm term to be larger than unity in a short-channel device. The speed of electrons in silicon saturate at sufficiently high electric fields, instead of growing linearly with the field strength. This causes a degradation of gm , but not gds0 , which is defined for zero Vds , and thereby electric field strength. Another effect is that of vertical electric fields at high gate voltages. At high gate voltages the electrons tend to move close to the interface between gate oxide and silicon, decreasing the charge mobility. This

degrades both gds0 and gm , but gm is degraded more as it is defined as the derivative of current with respect to gate voltage instead of drain voltage. A third effect that actually tends to decrease the ratio is built in series resistances in the devices. All these effects are included in the transistor model BSIM3v3 [6]. Fig. 2 shows the gm and gds0 of a 0.25-m CMOS transistor simulated with BSIM3v3. As can be seen the gm actually decreases above a certain voltage, whereas gds0 increases over the whole voltage range. Thus, the higher the supply voltage, the higher the performance. At very low Vgs ; gm is actually larger than gds0 . This is caused by a lower threshold voltage at higher drain voltages. Another important property of varactors is how much nonlinearity causing AM to FM conversion they have. Fig. 3 shows the nonlinearity of an MOS varactor in strong inversion and a switched-tuning circuit. Both varactors use a 300-m/0.25-m transistor. The switched circuit is designed to provide a slightly larger tuning range and uses a capacitor of 0.5 pF. The test was performed by doing simulations with 1.9and 2.1-V sinusoidal 1-GHz input signals in the SpectreRF simulator. The fundamental (1 GHz) current magnitudes were observed, and the effective capacitances was calculated. The y axis shows the relative capacitance change divided by the relative amplitude change. If the capacitance changes 1% for an amplitude change of 10%, the reading on the y axis will be 1%/10% 0.1. As can be seen in the figure, the MOS varactor exhibits a much larger AM to FM conversion than the switched one. The amount changes rapidly over the tuning interval and even the sign is reversed. This behavior is caused by the rapid transition from low to high capacitance in the MOS device as the gate to source voltage exceeds the threshold. A reverse biased diode varactor should give a better performance in this respect compared to the MOS varactor, but this is not further discussed as this work is limited to MOS varactors. The small amount of AM to FM conversion of the switched-tuning circuit is in the OFF state due to the nonlinear capacitance of the reverse biased diode between drain and substrate, and in the ON state due to the nonlinear ON resistance of the transistor.

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Fig. 3. AM to FM conversion for MOS varactor (solid line) and switched (2 stars).

Fig. 4.

Improved differential switched-tuning circuit.

purpose would be to fix the drain bias voltage to vdd in the OFF state, and thereby reduce and get a better control of the capacitance due to the reverse biased drainbulk junction. The same effect is achieved by the inverter arrangement in this circuit. The circuit has been tested using SpectreRF simulations and behaves as expected, see Fig. 5. In all graphs the same transistor size (100 m/0.25 m) and capacitor sizes were used in the differential and single ended circuits, resulting in the same simulated CON =COFF ratio. As can be seen in the figure, the quality factor of the differential tuning circuit was at all times twice that of the single ended one. The capacitances were 300 fF in (a) and (b), the supply voltage was 2.5 V in (a) and (c), and the frequency was 2 GHz in (b) and (c).

III. IMPROVED SWITCHED TUNING FOR DIFFERENTIAL CIRCUITS The use of two identical tuning circuits such as the one in Fig. 1, enables switched tuning of a differential oscillator [1]. The performance can be calculated by the equations in Section II. When a branch is turned ON it will contain two rds0 in series going from one side of the differential circuit (via ground) to the other. This limits the achievable quality factor. The idea here is to use just one switch transistor instead of two, see Fig. 4. If the transistor is kept the same size as in the previous circuit, the OFF capacitance is the same, since the transistor, which is assumed to be symmetric, has equal source and drain capacitances. The quality factor on the other hand is doubled, since just one device ON resistance is connected in series with the capacitors. The improvement can be used either as a doubled quality factor, C=COFF or frequency of operation capability. The inverter does not consume any static power, and a negligible amount of silicon area. Together with the resistors it makes sure that the transistor is OFF at all times in the OFF state and gets the maximum gate to source (and drain) voltage in the ON state. A large resistor can be included also in the single-ended circuit of Fig. 1 from drain to vdd. The IV. LAYOUT ASPECTS The layout of the switching devices will influence the achievable performance. The most efficient layout is the one that minimizes the drain junction area for a given device width [7]. In the differential switched tuning both the drain and source area must be minimized. The layout has less influence than one would first guess, however, since the drain (and source) capacitance in the OFF state is due to not just the junction area, but also the junction perimeter and the gate overlap capacitance, and the junction perimeter and overlap capacitance width can never be made less than the device width. For the single-ended switched tuning the best layout style is the doughnut. It has the smallest drain area, but this is achieved at the cost of a large source area, making it unsuitable for the differential scheme. The symmetrical counterpart of the doughnut is the waffle-iron layout. Whether it can be used with maximum benefit depends on the physical design rules for metal spacing. In Table I the different layout styles are compared for a typical 0.35-m CMOS process. The figure of merit (FoM) for comparing the different layout styles is 1/Cd; OFF , which is divided by two if differential use is

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V. CONCLUSION The performance limitations of switched capacitive tuning are investigated. A technology dependent limit exists in terms of simultaneously achievable tuning range and quality factor. An improved structure for differential circuits is presented. It doubles the quality factor or frequency of operation capability without degrading the performance in any other respect. Switched tuning is attractive in achieving higher tuning ranges than otherwise would be possible with continuous tuning, or would be possible but associated with problems concerning phase noise and disturbances. The switched tuning circuits presented have an AM to FM conversion that is negligible compared to that of an MOS varactor.
(a)

REFERENCES
[1] E. Hegazi, H. Sjland, and A. Abidi, A filtering technique to lower oscillator phase noise, in Dig. Tech. Papers ISSCC 2001, San Francisco, CA, 2001, pp. 364365. [2] C. Samori, A. L. Lacaita, A. Zanchi, S. Levantino, and F. Torrisi, Impact of indirect stability on phase noise performance of fully-integrated LC tuned VCOs, in Proc. ESSCIRC , Sept. 1999, pp. 202205. [3] A. Kral, F. Behbahani, and A. Abidi, RF-CMOS oscillators with switched tuning, in Proc. Custom IC Conf., Santa Clara, CA, 1998, pp. 555558. [4] F. Behbahani, W. Tan, A. Karimi-Sanjaani, A. Roithmeier, and A. Abidi, A broad-band tunable CMOS channel-select filter for a low-IF wireless receiver, IEEE J. Solid-State Circuits, vol. 35, pp. 476489, Apr. 2000. [5] P. Andreani and S. Mattisson, On the use of MOS varactors in RF VCOs, IEEE J. Solid-State Circuits, vol. 35, pp. 905910, June 2000. [6] [Online]. Available: http://www-device.eecs.berkeley.edu/bsim3/. [7] H. Sjland, Highly Linear Wideband AmplifiersDesign and Analysis of Frequencies From Audio to RF. Norwell, MA: Kluwer, 1999.

(b)

(c) Fig. 5. Quality factor versus (a) frequency, (b) supply voltage, and (c) switched capacitance.

TABLE I LAYOUT STYLE COMPARISON

not possible. The FoM is highest for the waffle-iron layout, but it also has the fewest number of metal to silicon contacts, resulting in more series resistance than the finger layout. At high supply voltages, when the ON resistance is low, the finger layout may, therefore, give a performance comparable to or even higher than the waffle iron.