AN3095 Application Note

November 2012 Doc ID 16555 Rev 3 1/55
AN3095
Application note
STEVAL-ISV002V1, STEVAL-ISV002V2 3 kW
grid-connected PV system, based on the STM32F103xx
Introduction
The STEVAL-ISV002V2 demonstration board is the same as the STEVAL-ISV002V1, but
assembled in a metal suitcase. In recent years, the interest in photovoltaic (PV) applications
has grown exponentially. As PV systems need an electronic interface to be connected to the
grid or standalone loads, the PV market has started appealing to many power electronics
manufacturers. Improvements in design, technology and manufacturing of PV inverters, as
well as cost reduction and high efficiency, are always the main objectives, [see References
1, 2].
This application note describes the development and evaluation of a conversion system for
PV applications with the target of achieving a significant reduction in production costs and
high efficiency. It consists of a high frequency isolated input power section performing DC-
DC conversion and an inverter section capable of delivering sinusoidal current of 50 Hz to
the grid. The system operates with input voltages in the range of 200 V to 400 V and is tied
to the grid at 230 Vrms, 50 Hz, through an LCL filter. Other peculiar characteristics of the
proposed converter are the integration level, decoupled active and reactive power control
and flexibility towards the source. A prototype has been realized and a fully digital control
algorithm, including power management for grid-connected operation and an MPPT
(maximum power point tracking) algorithm, has been implemented on a dedicated control
board, equipped with a latest generation 32-bit (STM32F103xx) microprocessor.
Figure 1. 3 kW PV system image
www.st.com
Contents AN3095
2/55 Doc ID 16555 Rev 3
Contents
1 System description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 DC-DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 DC-DC converter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 DC-AC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Schematic description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6 STM32F103xx-based current control strategy for inverter grid
connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
AN3095 List of tables
Doc ID 16555 Rev 3 3/55
List of tables
Table 1. System specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. MOSFET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. Diode rectifier electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. HF transformer specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. STGW35HF60WD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Operating modes of grid-connected voltage source inverter . . . . . . . . . . . . . . . . . . . . . . . 38
Table 7. Execution time of the main control functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
List of figures AN3095
4/55 Doc ID 16555 Rev 3
List of figures
Figure 1. 3 kW PV system image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Block scheme of hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. DC-DC and DC-AC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. DC-DC converter control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. DC-DC converter equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Current flow in mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Current flow in mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Current path in mode 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. DC-DC converter operating waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. Modulation and transformer current in DCM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Power transfer function for different input voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Variation of parameter d with input voltage for n=1.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13. Conversion systems with modified DC-AC inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Schematic of the power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Output sensing and relay board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Schematic of the AC voltage measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. Line current conditioning circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18. ADC interrupt service routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19. STM32F103xx microcontroller schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 20. DC-DC converter driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 21. DC-AC converter driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 22. 5 V,1 A flyback converter with VIPER17HN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 23. Multi-output flyback converter with VIPER27HN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 24. Block diagram of the implemented control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 25. Stationary reference frame and rotating reference frame. . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 26. Implemented PLL structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 27. DQ components of the current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 28. Block diagram of the implemented MPPT algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 29. Grid angle and Vd component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 30. Grid angle and grid voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 31. Grid angle (yellow), grid voltage (red), 90 phase-shifted voltage (blue) . . . . . . . . . . . . . . 46
Figure 32. DC-DC phase-shift modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 33. Phase-shifted signals, transformer current in CCM, power MOSFET M1 drain current . . . 47
Figure 34. Power MOSFET M1- Ch1 gate signal; Ch2 drain-source voltage and drain current Ch4. . 47
Figure 35. Phase-shifted gate signals (Ch1, Ch2), primary and secondary transformer voltage
(Ch3, Ch4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 36. DC-AC voltage and current in standalone mode (open-loop operation) . . . . . . . . . . . . . . . 48
Figure 37. Grid voltage (blue), inverter voltage (red), injected current (green); injected power (math
function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 38. Inverter voltage (green) and current (blue) at 800 W,PF=0.97. . . . . . . . . . . . . . . . . . . . . . 48
Figure 39. Inverter voltage (green) and current (yellow) at 2500 W, PF . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 40. DC-DC converter efficiency at different input voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 41. System efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 42. MOSFET M1- Ch1 gate signal, Ch2 drain-source voltage and Ch 4 drain current. . . . . . . 49
Figure 43. Phase-shifted gate signals (Ch1, Ch2), primary and secondary transformer voltage (Ch3,
Ch4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
AN3095 List of figures
Doc ID 16555 Rev 3 5/55
Figure 44. Low-side device modulation (red and blue track); high-side device modulation (yellow
track and green track) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 45. High-side device modulation in leg 1 (yellow track); high-side device modulation in leg 2
(green track); inverter output voltage (blue track) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
System description AN3095
6/55 Doc ID 16555 Rev 3
1 System description
A general description of the system is shown in Figure 2 with a block scheme representing
hardware implementation.
Figure 2. Block scheme of hardware implementation
It consists of 5 boards as listed below:
Main power board
Multi-output power supply board
Control and signal conditioning board
Output sensing and relay board
Input current sensing board.
The system may be completed by adding two additional boards with input and output EMI
filters which, at the moment, are not included in the final prototype.
The main power board is a dual-stage converter using DC-DC to adapt voltage levels and
impedance from the PV array and a sinusoidal PWM DC-AC to perform grid connection at
230 Vrms and 50 Hz, [see References 3]. Gate driving circuitry, input and output voltage
sensors of the DC-DC converter, as well as high frequency (HF) transformers, are also
placed on the power board. The principle reason for using a HF transformer is the galvanic
isolation provided between the PV module and the grid, to minimize the risk of hazardous
operations on the PV side caused by a fault on the grid side; voltage step-up and also
interruption of the resonance path formed by the parasitic capacitances to ground of the PV
array and the inductance of the LCL filter. Another advantage is the elimination of high
common mode currents allowing the use of unipolar pulse-width modulation for the inverter
with a consequent reduction in current harmonic content compared to bipolar pulse-width
modulation, [see References 4, 5].
Both the multi-output power supply board and control board are connected to the main
power board by means of a 34-pin connector. In this way, the connection/disconnection of
the ancillary boards is very easy and allows the separation of debug and characterization.
AM05396v1

E
M
I
L
E
M
PV Array
Mos Mos Mos Mos Mos Mos Mos
Gate Drivers
Input Volt.
Sensing
LEM
HF
TransIormer
DC Bus
Sensing
LEM
Power & Driver Board
Inductor
Inductor
Relay
E
M
I
Inductor
G
R
I
D
Multi output
POWER SUPPLY
BOARD
Control
Board
Output Sensing & Relays
Control Board with STM32
Multi output Power Supply Board
Input Current Sensing Board
Inverter Filter Inductors
Grid Coupling Inductor
Power Supply Board
and
Connectors
E
M
I
L
E
M
PV Array
Mos Mos Mos Mos Mos Mos Mos
Gate Drivers
Input Volt.
Sensing
LEM
HF
TransIormer
DC Bus
Sensing
LEM
Power & Driver Board
Inductor
Inductor
Relay
E
M
I
Inductor
G
R
I
D
Multi output
POWER SUPPLY
BOARD
Control
Board
Output Sensing & Relays
Control Board with STM32
Input Current Sensing Board
Inverter Filter Inductors
Grid Coupling Inductor
Power Supply Board
and
Connectors
Power Supply Board
and
Control Board connected
to the Power Board through 34-Pin
Connectors
AN3095 System description
Doc ID 16555 Rev 3 7/55
The output sensing and relays board was realized to interface the power system and the
grid. This task is accomplished with the implementation of a proper control algorithm which
requires both grid-current and grid-voltage sensing. For this reason, the board is equipped
with current and voltage Hall effect sensors. Two relays, controlled by an I/O of the
microcontroller, are also placed on the same PCB to interrupt/connect phase and neutral of
the system to phase and neutral of the grid. Moreover, this board is provided with two-way
connectors for electrical wiring of the LCL filter to the main power board.
The multi-output power supply board implements two independent offline flyback
converters, with wide input voltage range, based on VIPER technology, to generate the
following output voltages:
+5 V to supply DC-DC converter gate drivers
+5 V to supply DC-AC converter gate drivers
+5 V to supply the microcontroller
+/-15 V for LEM sensors supply
24 V for relays supply
The main advantage of an offline solution is the availability of a power supply for circuits
dedicated to communication and data transfer even at night or in the case of weak PV field
energy production. The price to pay for such an advantage is higher power consumption
during standby mode of the main power unit.
The specifications in Table 1 for the PV system are used as inputs for the design of the
boards mentioned above. All parameters are assumed to be equal to their nominal value if
not otherwise stated.
Table 1. System specifications
Specification Value
DC-DC input voltage 200 V - 400 V
DC-DC output voltage 450 V
DC-AC output voltage 230 Vac
Nominal output power 3 kW
DC-AC switching frequency 17 kHz
DC-DC switching frequency 35 kHz
Transformer turns ratio 1.2
Grid voltage 230 Vrms +/- 20 %
Grid frequency 50 Hz
Power factor above 10 % rated power >0.9
THD@ full load <5 %
DC-DC converter AN3095
8/55 Doc ID 16555 Rev 3
2 DC-DC converter
The dual-stage inverter for grid-connected applications includes a DC-DC converter to
amplify the voltage and a DC-AC inverter to control the current injected into the grid.
Figure 3. DC-DC and DC-AC converter
The DC-DC converter is depicted in Figure 3 together with the DC-AC converter and LCL
filter. The converter consists of an input capacitor, C1, six switches, M1 - M6, six
freewheeling diodes, two rectifier diodes, D1 and D2, a HF transformer with turns ratio equal
to 1.2 and a DC link capacitor C2.
The transformer provides voltage isolation between the PV array and the grid, improving
overall system safety. Its leakage inductance is used as a power transfer element,
eliminating device overvoltage problems and the need for snubber circuits. Proper phase-
shift control between input bridge legs (M1-M4) and active rectifier legs (M5-M6) allows
transformer current shaping, therefore achieving ZCZVS for all the power devices, as well as
voltage step-up. The adopted phase-shift modulation is shown Figure 4.
Figure 4. DC-DC converter control signals
The same drive signal used for device M1 also controls M4, as the one controlling M3 is also
used for M2. The effect of the input bridge modulation is to generate a square wave on the
VGSM1
VGSM2
VGSM5
VGSM6
AM05398v1
AN3095 DC-DC converter
Doc ID 16555 Rev 3 9/55
input of the HF transformer which varies between +Vin and -Vin, while the effect of the
modulation on the active rectifier is to generate, on the secondary of the HF transformer, a
square wave varying between +Vbus and -Vbus, where Vbus is the voltage on capacitor C2,
phase shifted with respect to the primary one of an angle , equal to the phase shift of the
modulating signals, as shown in the equivalent circuit of figures 5, 6, 7, 8, 9, 10, and 11.
Figure 5. DC-DC converter equivalent circuit
As a result, the primary voltage and the secondary transformer voltage reflected to the
primary determine the rising and falling slope of the current in the leakage inductance.
According to leakage inductance current waveforms, two operating modes may be
distinguished for the converter:
Discontinuous current mode DCM
Continuous current mode CCM
Both in CCM and DCM, three main operating modes or intervals may be distinguished in
half the switching period. Considering the modulation shown in Figure 9, in CCM the
leakage inductance current may be calculated as follows:
Mode 1, interval (t
0
- t
1
):
At t
0
M1 and M4 are turned on at ZVS, M6 is also on. The voltage across the leakage
inductance is:
Equation 1
and the current may be written as follows:
Equation 2
Since this current is negative, as shown in Figure 9, it flows in the circuit as demonstrated in
Figure 6.
AM05399v1

+/-V
in
TX
+/-V
bus

Leakage inductance
V
Lk
n
V
V V
bus
in LK
+
( )( )
n V
V
d
) t ( i t t d 1 V
L
1
) t ( i
in
bus
0 Lk 1 in
k
k L
+ +
10/55 Doc ID 16555 Rev 3
Figure 6. Current flow in mode 1
This mode ends when leakage inductor current reaches zero at t=t
1
.
Mode 2, interval (t
1
-t
2
):
When the leakage inductor current reaches zero, D1 and D2 turn-off with soft switching, as
the current naturally reaches zero. After t=t
1
M6 is still on, primary current changes polarity
and flows through M1 and M4. On the secondary side the transformer is shorted through M6
and D2, as shown in Figure 7. Inductor current may be written as:
Equation 3
Figure 7. Current flow in mode 2
Mode 3, interval (t
2
-t
3
):
At t=t
2
M6 is turned off and M5 is turned on under ZVS. A positive voltage equal to +Vbus is
applied on transformer secondary winding. Leakage inductor current is given by:
Equation 4
The current path in the circuit is drawn in Figure 8.
AM05400v1

D1
LIk
TX
D2
M1 M3
M2 M4
M5
M6
Vin
C2
C1

L
O
A
D
( ) ) t ( i t t V
L
1
) t ( i
0 Lk 1 in
k
k L
+
AM05601v1
D1
LIk
TX
D2
M1 M3
M2 M4
M5
M6
Vin
C2
C1

L
O
A
D
( )( ) ) t ( i 2 t t d 1 V
L
1
) t ( i
2 Llk in
k
K L
+
Doc ID 16555 Rev 3 11/55
Figure 8. Current path in mode 3
Figure 9. DC-DC converter operating waveforms
AM05602v1

D1
LIk
TX
D2
M1 M3
M2 M4
M5
M6
C2
C1

L
O
A
D

M1,M4
M2,M3
M5
M6
IM1,IM2
IM3,IM4
V
pri
, V
bus
ILK
.
IM5,IM6
ID1
ID2
t
3
t
4 t
5
t
6
t
0
t
2
t
1
t
0
AM05603v1

M1,M4
M2,M3
M5
M6
IM1,IM2
IM3,IM4
V
pri
, V
bus
ILK
.
IM5,IM6
ID1
ID2
t
3
t
4 t
5
t
6
t
0
t
2
t
1
t
0
12/55 Doc ID 16555 Rev 3
Due to symmetry during the two halves of the switching period, current expressions and
current paths may be derived with similar considerations for the second half of the switching
period.
If d >1 the current in the leakage inductor may reach zero and there is a boundary between
CCM and DCM.
In DCM there are also three modes of operation, as shown in Figure 10.
Mode 1, interval t
0
-t
1
:
At t=t
0
inductor current is zero. After t=t
0
devices M1and M4 are turned on under zero
current and inductor current rises according to the following equation:
Equation 5
Figure 10. Modulation and transformer current in DCM
Mode 2, interval t
1
-t
2
:
At t
1
M6 turns off and M5 turns on with zero current. Inductor current expression is given by:
Equation 6
and reaches zero at t=t
3
.
Mode 3, t
2
-t
3
Equation 7
The boundary between DCM and CCM depends on the phase-shift angle, input voltage,
output voltage and transformer turns ratio and is given by:
( ) ) t ( i t t V
L
1
) t ( i
Lk 1 in
k
k L
+

t0 t1 t2 t3
AM05604v1
( )( ) ) t ( i t t d 1 V
L
1
) t ( i
2 Llk 2 in
k
K L
+
0 ) t ( i
K L

Doc ID 16555 Rev 3 13/55
Equation 8
By integrating the leakage current expression over the switching period and multiplying the
result by the input voltage value the expression of power transfer may be derived as:
Equation 9
where
s
=2f
s
is the switching frequency in rad/s, =
s
t is the phase-shift angle and
.

once the operation of the converter has been described, based on the specification in
Table 1, the power transfer function may be plotted as shown in Figure 11.
Figure 11. Power transfer function for different input voltages
As the converter operates in boost mode the value of parameter d must be kept greater
than 1 for every value of input voltage in order to maintain controllability, also at low power
levels. In fact, if d<1 the converter is characterized by a minimum power level under which
the converter cannot be controlled. For this reason, transformer turns ratio has been chosen
at equal to 1.2. The value of leakage inductance must also be chosen carefully and it is a
compromise between peak current value and the maximum energy transfer between input
and output.

d
1 d
B
>
+
<

B
2
k s
2
in
B
2
k s
2
in
) ( F
) d 2 ( 2
d
L
V
P
) 1 d ( 2
d
L
V
P
) d d 2 2 ( 2 ) d d 1 ( 4 ) d 2 d 1 ( ) ( F
2
2
2 2
+ +
+ + + +
AM05605v1
0 0.5 1 1.5 2 2.5 3 3.5
0
1000
2000
3000
4000
5000
6000
7000
8000
Phase shift angle [rad]
P
o
w
e
r

[
W
]
Power transfer function with Vin=200 V,300 V,400 V
14/55 Doc ID 16555 Rev 3
Figure 12. Variation of parameter d with input voltage for n=1.2
A leakage inductance value comprised between 35 H and 55 H is suitable to obtain the
desired power level of 3 kW in all the input voltage range for the chosen transformer turns
ratio of 1.2.
AM05606v1
200 250 300 350 400 450
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
nput Voltage [V]
P
a
r
a
m
e
t
e
r

d
Variation of d with Vin for n=1.2
AN3095 DC-DC converter design
Doc ID 16555 Rev 3 15/55
3 DC-DC converter design
After having described the operation of the DC-DC converter, the design may be completed
according to the specifications in Table 1.
Input power: assuming 90 % efficiency the input power is:
Equation 10
Maximum average input current:
Equation 11
Maximum average output current:
Equation 12
Maximum input power device RMS current value:
Equation 13
Where K=0 for triangular waveforms and K=1 for rectangular waveforms. This said, the
maximum RMS current value in DCM is:
Equation 14
And assuming K=0.6 for trapezoidal current waveform in CCM:
Equation 15
Minimum input power device breakdown voltage:
Equation 16
W 3333
9 . 0
P
P
out
in

A 66 . 16
200
3333
V
P
I
min in
in
in

A 5 . 7
V
P
I
min out
out
out

2
2
in max rms
) 1 K ( 3
K K 1
I D 2 I
+
+ +
In
max
2
2
in max rms
I
3
D
2
) 1 K ( 3
K K 1
I D 2 I
DCM _

+
+ +
=13.6 A
A 2 . 27 15 . 1 I D 2
) 1 K ( 3
K K 1
I D 2 I
In max
2
2
in max rms
CCM _

+
+ +
V 520 400 * 3 . 1 V 3 . 1 V
max MPPT Brk
Mos

DC-DC converter design AN3095
16/55 Doc ID 16555 Rev 3

Transformer turns ratio:
As the converter operates in boost mode, to avoid problems of controllability for low power
levels, the value of parameter d must always be greater than one:
Equation 17
Moreover, considering the voltage drop across the leakage inductor it is possible to operate
the converter with n=1.2 without incurring regulation problems for high input voltage values
at low power.
Minimum output power device breakdown voltage:
Equation 18
Power device selection:
According to the calculations above, four STW55NM60ND MOSFETs were selected for the
input bridge and also two STW55NM60NDs for the active rectifier. The main characteristics
of this MOSFET are reported in Table 2 and 3:
Rectifier diode selection:
Two STTH60L06s are selected for the diode leg. The main characteristics are shown in
Figure 3:
Input capacitor value:
The input capacitor, C1, is designed to smooth the high frequency ripple at the input of the
PV array. If the current generated by the module is assumed to be constant and the current
drawn by the converter is assumed to be a pulse train, the following equation gives the value
of the input capacitance:
Equation 19
Table 2. MOSFET electrical characteristics
VDS@Tjmax RDSon_max ID@100C Coss Qg
650 V 0.06 29 A 900 pF 190 nC
Table 3. Diode rectifier electrical characteristics
Vf_max @150 C IF=60 A Vrrm Trr_max IF IRM
1.4 V 600 V 85 n 60 A 10.5 A
12 . 1
dVin
Vout
n 1 d
MAX

V 576 400 * 2 . 1 n * V 2 . 1 V
max MPPT OUTPUT _ Brk
Mos

min array s
array
1
Vin v f 2
P
C
>
Doc ID 16555 Rev 3 17/55
where:
P
array
is the PV field maximum output power, V
array
is the allowable peak-to-peak voltage
ripple at the input of the array, f
s
is the switching frequency and Vin
min
is the minimum
operating value for the input voltage. Assuming 90 % efficiency for the converter and 0.1 %
of admissible peak-to-peak ripple voltage the input capacitance value is:
Equation 20
Three 330 F, 450 V electrolytic capacitors are connected in parallel at the input of the
converter to limit the effect of the high frequency ripple on the PV generator.
Output capacitor value:
In a similar way the value of the C2 bus capacitor may be calculated, taking the fact that the
ripple is sinusoidal at twice the grid frequency into account:
Equation 21
where the peak-to-peak voltage of 9 V corresponds to a voltage ripple of 1 % of the nominal
bus voltage and the grid frequency is 50 Hz.
HF transformer design:
The design is based on the core geometry method. The transformer specifications are
shown in Table 4:
Table 4. HF transformer specifications
Specification Symbol Value
Nominal input voltage V
in
300 V
Maximum input voltage V
inmax
400 V
Minimum input voltage V
inmin
200 V
Input current I
in
27 A
Nominal output voltage V
out
450 V
Output current I
out
22.5 A
Switching frequency f 35 kHz
Efficiency 99 %
Regulation 0.15
Max operating flux density B
m
0.15 T
Window utilization K
u
0.3
Duty cycle D
max
0.5
Maximum temperature rise T
r
70 C
mF 1 . 1
200 * 2 . 0 * 35000 * 2
33 . 3333
Vin v f 2
P
C
min array s
array
1

>
mF 17 . 1
450 * 9 * 50 * * 2 * 2
3000
V v 2
P
C
bus bus grid
out
2

>
18/55 Doc ID 16555 Rev 3
The transformer apparent power is:
Equation 22
Then the electrical condition parameter calculation K
e
may be evaluated:
Equation 23
where Kf=4.44 is the waveform coefficient.
Equation 24
Now, the core geometry parameter is calculated as:
Equation 25
The Kg parameter of a generic transformer core is given by the following equation:
Equation 26
Using two sets of E70/33/32s the following condition is verified:
Equation 27
The number of primary turns for the design flux swing is:
Equation 28
The primary inductance value is:
Equation 29
and the number of secondary turns is:
Equation 30
W 6061 I V ) 1
1
( P
P
P
0 0 0
0
t
+
( )
4 2
m
2 2
f e
10 B f K 145 . 0 K
-

( ) 7606 10 ) 15 . 0 ( ) 000 . 35 ( ) 44 . 4 ( 145 . 0 K
4 2 2 2
e

-
5
e
t
g
cm 65 . 2
K 2
P
K
MLT
K A W
K
u
2
c a
g
CORE

MLT
K A W
K
u
2
c a
g
CORE

>K
g
turns 14
A 2 B
T D V
N
c
max in
1
min
( ) mH 48 . 2 nH 12666 * 14 A N L
2
L
2
p

turns 17 1 N n N
2

Doc ID 16555 Rev 3 19/55
The next step is to choose the wire size in order to realize primary and secondary windings.
At 35 kHz, current penetration depth is:
Equation 31
Then, the wire diameter may be selected as follows:
Equation 32
And the conductor section is:
Equation 33
AWG21, having d=0.072 cm and a wire area of A
WAWG22
=0.0040 cm
2
, may be used for this
design. Considering a current density of J=500 A/cm
2
, the number of primary wires is given
by:
Equation 34
where
Equation 35
Since the AWG21 has a resistance of 420 /cm, the primary resistance is:
Equation 36
and so the value of resistance for the primary winding is:
Equation 37
With the same procedure for the secondary winding it is:
Equation 38
cm 035 . 0
f
62 . 6

cm 07 . 0 2 d
2
2
W
cm 0038 . 0
4
d
A
choose 5 . 13
A
A
S
26 AWG
w
wp
np
14 S
np

2 CCM rms
wp
cm 054 . 0
J
I
A
cm / 30
14
cm / 420
r
p

m 7 . 13 r MLT 2 N R
p 1 p
2 CCM _ rms
ws
cm 045 . 0
J n
I
A
11
A
A
S
21 wawg
ws
ns

cm / 38
11
cm / 420
r
s

m 1 . 21 r MLT 2 N R
s 2 s
20/55 Doc ID 16555 Rev 3
The total copper losses are:
Equation 39
From the core loss curve of N87 material, at 100 C, 0.15 T and 35 kHz, the selected core
has the following losses:
Equation 40
Where V
e
=102000 mm
3
is the core volume of one set of E75/33/32.
The efficiency of the transformer is:
Equation 41
The transformer temperature rise is:
Equation 42
With
Equation 43
W 9 . 20 I R I R P P P
2
s s
in
2
p s p Cu
+ +
W 4 V 2
m
kW
20 P
e
3
V

% 17 . 99 100 *
3000
9 . 24
1
T

,
_

( ) C 68 . 79 P P R 5 . 0 T
o
V Cu th r
+
W
C
4 . 6 R
o
th

AN3095 DC-AC converter
Doc ID 16555 Rev 3 21/55
4 DC-AC converter
The DC-AC inverter is a standard single-phase full bridge based on IGBTs with ultrafast co-
pack diodes, as depicted in Figure 3. The connection to the grid is realized by means of
current control performed in DQ rotating reference frame. An LCL filter is placed between
the bridge and the grid in order to reduce the current harmonics generated by the unipolar
sinusoidal pulse-width modulation (USPWM) at 17 kHz. L filters or LC filters may also be
chosen for the application, but in the first case large values of inductance are required to
perform good high frequency noise damping and large currents through the capacitor may
arise in the second case together with high voltage harmonics. LCL filters show good
performance in terms of current harmonic reduction but they may lead to instability of the
control loop in the presence of large grid impedance. This instability is due to the presence
of extra poles introduced by the additional inductor. The problem may be solved with proper
filter design and by adding a damping resistor in series with the filter capacitor.
The value of L
f
is designed in order to limit the current ripple to about 10 % of the nominal
current value according to:
Equation 44
The filter capacitor value is designed to limit the exchange of reactive power below 5 % of
nominal active power:
Equation 45
To avoid resonance problems for the filter, due to low and high order harmonics, its resonant
frequency, given by , should be in a range between ten times the line

frequency and one half of the switching frequency:
Equation 46
In fact, if the resonant frequency is too small the filter resonance increases the low
frequency harmonics and, in the same way, if it is too high it increases the harmonics
multiple of the switching frequency.
With a filter capacitor value of 3.3 F and a grid inductor value of 2 mH the resulting
resonant frequency is 2771 Hz, which is in the specified range.
( )
( )
mH 05 . 2
17000 * 3 . 1 * 2
72 . 0 * 324 450
f i 2
D V V
L
sw
pk _ grid BUS
f

uF 9
X
1
C
6 . 352
P 05 . 0
V
X
P 05 . 0
X
V
P
c
n
2
grid
c
n
c
2
grid
reactive

f g f
f g
res
C L L
L L
2
1
f
+
kHz 5 . 8 f Hz 500
f 5 . 0 f f * 10
res
sw res grid

DC-AC converter AN3095
22/55 Doc ID 16555 Rev 3
The LCL filter is effective only if proper damping is added. Passive damping, realized with a
resistor series connected to the filter capacitor was used for this application. The value of
the resistor is chosen to be one third of the impedance of the capacitor at the resonant
frequency:
Equation 47
Selection of semiconductor devices
The semiconductors selected for the DC-AC section are 600 V, 35 A IGBTs with internal fast
diodes used to minimize the effect of recovery at turn-on. The choice of IGBTs is a trade off
between cost and efficiency. The part number of the device used is STGW35HF60WD,
which shows very good performance in terms of switching losses. The electrical
characteristics of this device are shown in Table 5.
The power losses in each IGBT may be calculated considering conduction losses, switching
losses and diode losses.
Conduction and switching losses in IGBTs may be evaluated according to the following
equations:
Equation 48

8 . 5
C * * 3
1
R
res
damp
Table 5. STGW35HF60WD electrical characteristics
Part number Saturation voltage
Collector
current
E
off
E
on
Gate
charge
STGW35HF60WD
VCE
sat
@125 C,13 A I
C
@100 C E
off
@125 C,15 A E
on
@125 C,15 A Q
g
1.8 V 37 A 360 J Rg=47 300 J Rg=56 102 nC

+ + +
02 . 0 R
1 cos
72 . 0
450
325
V
V
ma
V 8 . 1 V
W 62 . 1 f
Eoff
off _ Psw
W 94 . 1 f
Eon
on _ Psw
W 6 . 9 ) cos
3
ma
8
1
( * I * R ) cos ma
8
1
2
1
( I * V Pcond
CE
bus
pk _ grid
CE
sw
sw
pk
2
CE pk CE
Where
AN3095 DC-AC converter
Doc ID 16555 Rev 3 23/55
Diode losses may be evaluated according to the following equations:
Equation 49
where
Equation 50
The resulting total losses for the single-phase inverter are calculated below:
Equation 51
resulting in 98% theoretical efficiency for the inverter stage. A simple modification of the
control strategy, together with a different choice of power devices, may improve the
efficiency and performance of the DC-AC stage. The modified circuit is shown in Figure 13.
Figure 13. Conversion systems with modified DC-AC inverter
The low-side power devices, Z2 and Z4, are low-drop IGBTs switching at 50 Hz according to
grid polarity while the high-side devices are MOSFETs switching at high frequency with
pulse-width modulation. Compared to the standard topology, the main advantages are lower
conduction losses of both MOSFETs and low-drop IGBTs, absence of switching losses for
the low-side devices and, eventually, the possibility of using higher switching frequencies
with a reduction of reactive components size and cost and wider bandwidth for the control
loop.
The possible implementation of this solution may be based on the use of STW55NM60ND
for the high-side and STGW35NB60SD, connected in parallel to an external SiC diode, for
the low side. A gain in efficiency between of 0.5 % and 1 % may be measured with such an
implementation.
W 45 . 0 f V t I
8
1
P
W 3 . 1 ) cos
3
ma
8
1
( * I * V P
SW pk rr rr RR _ diode
pk F DC _ diode

V 450 V
pk
A 4 . 5 I
rr
ns 88 t
rr

( ) W 6 . 59 Pcond off _ Psw on _ Psw P P 4 P
RR _ diode DC _ diode tot
+ + + +
AM05607v1

D1
Vgrid
LIk LF
TX
D2
M1 M3
M2 M4
M5
M6
Z2 Z4
Z1
LF
Vin
C3
C0
Z3
LC
CF
Schematic description AN3095
24/55 Doc ID 16555 Rev 3
5 Schematic description
The power board schematic is shown in Figure 14. The input voltage, produced by the PV
array and comprising between 200 V and 400 V, is fed to the power circuit through
connector J7. The input filter consists of 3 high voltage electrolytic capacitors and two 0.1 F
polypropylene capacitors connected at the input of the bridge, to reduce the effects of
parasitic inductances due to cables and PCB tracks. Each of the four input power
MOSFETs, STW55NM60ND, are connected in parallel to a STTH30R06, 600 V 30 A ultra-
fast, soft recovery diode. This diode carries only a small amount of current during ZVS
operation of the DC-DC converter due to the relatively lower forward voltage of the MOSFET
body diode.
The power MOSFETs in the active rectifier are connected in parallel to 4.7 nF, 630VDC
polypropylene capacitors used as voltage snubbers to minimize turn-off losses.
The HF transformer is realized using two E70/33/32 cores with N87 ferrite. In a transformer
having only a primary and a secondary winding, the value of the leakage inductance is
determined by the number of turns in each of the two windings and by the spatial
arrangements of these windings. The leakage inductance increases with an increasing
number of turns and with an increasing distance between the windings. However, the spatial
arrangement of the windings cannot be chosen arbitrarily, mainly because of mechanical
restrictions introduced by the core geometry chosen for the specific application. Then, if a
high value of leakage inductance is needed, an additional coil may be added in series to the
primary or a bigger core may be selected for the transformer. The leakage inductance of the
transformer in this application is designed without an additional external coil to achieve a
more compact set-up and lower cost.
A bank of four 330 F, 500 V electrolytic capacitors, connected in parallel, is placed on the
inverter bus to filter the 100 Hz ripple, together with a 2.2 F, polypropylene capacitor to
filter the high frequency component generated by the DC-DC converter. The output of the
DC-DC converter is connected to J9, a two-way connector mounted on the PCB in
order to allow the independent operation of both conversion stages. For example, by
connecting an electrical load to J9 and a DC voltage source to J7 the operation of the DC-
DC converter may be evaluated independently from the inverter. In the same way,
connecting a DC voltage source to J9 and disabling the modulation of the DC-DC converter
the operation of the DC-AC inverter may be evaluated both in standalone or grid-connected
operation. In standalone mode of operation the system is controlled in open loop, while in
grid connection mode the system operates with closed loop control.
The full bridge inverter consists of two legs implemented with STGW35HF60WD IGBTs.
A 0.1 F, 630VDC polypropylene capacitor (CF1, CF2) is connected across each leg. The
mid point of each leg is then reported on J8 to allow the connection of the two 1 mH
inductors used as high frequency filters together with capacitor C1 (Figure 15). This
capacitor, placed on the output sensing and relays board, is connected to the filter inductors
through a two-way connector J7, placed on the same board. The current in the filter inductor
is sensed by means of a Hall effect sensor CS1 and is used as a feedback for the control
algorithm. Also the grid voltage, sensed with LV1, is a feedback for the control algorithm and
is used for current synchronization to obtain unitary power factor.
Hall sensors provide inherent galvanic isolation between the grid and the control circuitry
and are very simple to use, requiring only a +15 V/-15 V supply voltage and a measurement
resistor. Despite these advantages, their cost is higher compared to other sensing solutions.
AN3095 Schematic description
Doc ID 16555 Rev 3 25/55
For example, a cheaper solution may be implemented using a simple voltage divider or a
shunt resistor together with an analog opto-isolator to provide galvanic isolation between the
power stage and control section. The price to pay in this case is the added complexity of the
sensing circuitry.
The physical connection to the grid is realized by means of two relays, placed on line and
neutral, which are controlled by an I/O of the control board with the STM32F103xx
microcontroller, and supplied by the 24 V bus generated by the multi-output power supply.
The feedback signals are sent to the control board by means of coaxial shielded cables
connected to J14 and J15 on the relays board.
26/55 Doc ID 16555 Rev 3
Figure 14. Schematic of the power stage
AM05608v1
CBUS5 2.2u 630V
C
4
2100p, 630V
G
B
T

H
G
H

4
S
T
G
W
3
5
H
F
6
0
W
D
V
b
u
s
B
U
S

V
o
lt
a
g
e
C
6
4
1
0
0
p
,

1
5

V
-
1
5

V
+
1
5

V
V
S
3
L
E
M

L
V
2
5
-
P
H
T
+
1
H
T
-
2
M
3
-
5
+
4
C
6
5
1
0
0
n
,

2
5

V
C
6
6
1
0
0
n
,

2
5

V
R
4
1
4
7
k

1
0
W

a
n
t
in
d
u
t
t
iv
a

(
N
.
M
.
)
R
4
4
5
6
0
.
6
W

,

1
%

B

t
e
c
h
n
o
l
o
g
i
e
s
s
e
r
i
e

B
P
C
5
C
6
1
1
0
0
n
,

6
3
0
V
S
e
r
ie
U
P
W
2
5
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e
O
h
m
R
5
0
4
7
k

1
0
W

a
n
t
in
d
u
t
t
iv
a

(
N
.
M
.
)
G
3
G
B
T

L
O
W

4
S
T
G
W
3
5
H
F
6
0
W
D
C
F
1
0
.
1
u

6
3
0
V
D
7
STTH60L06W
2 1
G
3
N
C
F
2
0
.
1
u

6
3
0
V
D
8 STTH60L06W
2 1
G
B
T

H
G
H

5
S
T
G
W
3
5
H
F
6
0
W
D
G
B
T

L
O
W

5
S
T
G
W
3
5
H
F
6
0
W
D
S
O
U
R
C
E

M
O
S

H
G
H

3
C
4
3
1
u
,

2
5
V
C
4
6
1
u

2
5
V
S
O
U
R
C
E

M
O
S

L
O
W

3
(
C
F
2

B
E
T
W
E
E
N

D
R
A
G
B
T

H
G
H

5

A
N
D

G
N
D
1
)
J
7
C
O
N
2
12
(
C
F
1

B
E
T
W
E
E
N

D
R
A
G
B
T

H
G
H

4

A
N
D

G
N
D
1
)
C
6
7
1
u
,

2
5

V
C
6
8
1
u
,

2
5

V
D
3
STTH30R06W
D
4
STTH30R06W
D
5
STTH30R06W
2 1
J
8
C
O
N
2
2
1
D
6
STTH30R06W
n
p
u
t

v
o
la
t
g
e

M
E
S
.
C
3
4
1
0
0
p
,

1
5

V
+
1
5

V
-
1
5

V
V
S
1
L
E
M

L
V
2
5
-
P
H
T
+
1
H
T
-
2
M
3
-
5
+
4
C
3
6
1
0
0
n
,

2
5

V
C
3
5
1
0
0
n
,

2
5

V
0
R
3
0
4
7
k

1
0
W

a
n
t
in
d
u
t
t
iv
a
R
3
1
5
6
s
e
r
i
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B
P
C
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B

t
e
c
h
n
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l
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P
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2
5
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e
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h
m
0
.
6
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,

1
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C
3
3100n, 630V
0
J
9
C
O
N
2
12
V
N
=
n
p
u
t

v
o
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t
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6
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,

6
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1
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5
5
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M
6
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G
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2
S
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5
5
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M
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W

2
S
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5
5
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M
6
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3
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5
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3
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5
5
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M
6
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D
C
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1
C
A
P
C
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2
C
A
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C
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3
C
A
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H
G
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5
C
B
U
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C
A
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C
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S
2
C
A
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C
B
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S
3
C
A
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0
.
1

u
F
C
A
P

P
O
L
P
R
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P
.
C
B
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4
C
A
P
d
i
m
.

(
B

X

H

X

L
)
:

9

X

1
7
.
5

X
1
8

m
m
C
7
4
/
C
7
5

6
3
0
V

d
i
m
.

(
B

X

H

X

L
)
:

7

X

1
2
.
5

X
1
8

m
m
D
R
A
G
B
T

H
G
H

4
E
P
C
O
S

E
l
e
c
t
r
.

C
a
p
.
D
R
A
G
B
T

H
G
H

4
5
0
0
V
,

3
3
0
u
F
,

p
a
s
s
o

1
0

m
m
T
1
T
R
A
N
_
H
M
3
1
1
1
8
9
1
0
D
R
A
N

M
O
S

H
G
H

3
E
P
C
O
S

E
le
c
t
r
.

C
a
p
.
5
0
0
V
,

3
3
0
u
F
,

p
a
s
s
o

1
0

m
m
V
b
u
s
O
U
T

A
C

1
0
G
N
D
0
D
R
A
N

M
O
S

H
G
H

1
D
R
A
N

M
O
S

H
G
H

2
V
in
G
N
D
1
Vmax 400 V
Vmax 450 V
G
1
G
N
D
A
C
G
2
G
1
N
G
2
N
S
O
U
R
C
E

G
B
T

H
G
H

5
S
O
U
R
C
E

M
O
S

H
G
H

1
G
5
N G
5
D
R
A
G
B
T

H
G
H

5
O
U
T

A
C

2
S
O
U
R
C
E

G
B
T

L
O
W

4
S
O
U
R
C
E

G
B
T

L
O
W

5
S
O
U
R
C
E

M
O
S

H
G
H

2
S
O
U
R
C
E

M
O
S

L
O
W

2
S
O
U
R
C
E

M
O
S

L
O
W

1
Vmax 450 V
C
1
2
1
4
.
7
n
C
1
2
2
4
.
7
n
C
N
5
0
.
1
u

6
3
0
V
R
4
9
4
7
k

1
0
W

a
n
t
in
d
u
t
t
iv
a
C
N
4
0
.
1
u

6
3
0
V
CBUS6 2.2u 630V
2 1
2 12 1
Doc ID 16555 Rev 3 27/55
The output voltage of the sensor circuits must be adapted to the voltage range of the analog
to digital converter (ADC) of the STM32F103xx microcontroller, which is 0-3.3 V. This task is
accomplished using simple circuits based on operational amplifiers, such as the one shown
in Figure 16 for grid-voltage measurement.
28/55 Doc ID 16555 Rev 3
Figure 15. Output sensing and relay board schematic
AM05609v1
F
R
O
M

C
O
N
T
R
O
L

B
O
A
R
D
F
R
O
M

P
O
W
E
R

S
U
P
P
L
Y

B
O
A
R
D
J
1
1
C
O
N
2
1 2
J
1
2
C
O
N
2
1 2
g
r
id

v
o
la
t
g
e

M
E
S
.
T
O

C
O
N
T
R
O
L

B
O
A
R
D
C
5
1
4
7
n
F

1
6
V
+
2
4

V
R
e
la
y

C
o
n
t
r
o
l
U
4
T
L
4
3
1
/
T
O
C
5
2
4
.
7
n
F

1
6
V
U
2
5
34
26
C
5
3
47nF 16V
U
1
O
M
R
O
N

2
4
V

c
c
,

3
0
A
,

N
O
,

u
n
ip
o
la
r
,

t
y
p
e

6
5
.
3
1
-
0
3
0
0
5
34
26
T
O

L
E
M

S
E
N
S
O
R

W
T
H

2
.
5
m
m
^
2

(

2

T
U
R
N
S
)

W
R
E
V
O
U
T
V
N
G
N
D
U
5
L
4
9
3
1
C
D
T
5
0
-
T
R

D
P
A
K
1
3
2
C
4
2
100p, 630V
C
4
3
1
u
,

2
5
V
C
4
9
1
u

2
5
V
g
r
id

v
o
la
t
g
e

M
E
S
.
-
1
5

V
+
1
5

V
C
3
4100p, 15 V
V
S
1
L
E
M

L
V
2
5
-
P
H
T
+
1
H
T
-
2
M
3
-
5
+
4
C
3
6
1
0
0
n
,

2
5

V
C
3
5
1
0
0
n
,

2
5

V
0
R
3
0
4
7
k

1
0
W

a
n
t
in
d
u
t
t
iv
a
R
3
1
1
0
0
s
e
r
i
e

B
P
C
5
C
4
8
100n, 25 V
B

t
e
c
h
n
o
l
o
g
i
e
s
V
G
R
D
S
e
r
ie
U
P
W
2
5
,N
e
O
h
m
0
.
2
5
W

,

1
%

C
3
3
4.7n, 300Vac
0
V
G
R
D
R
3
4
d
a

1
.
5

a

3
.
3

/
5
W
T
O

C
O
N
T
R
O
L

B
O
A
R
D
V
d
c
C
O
N
3
123
+
2
4

V
-
1
5

V
C
5
0
100n, 25 V
+
1
5

V
0
2

T
U
R
N
S
F
R
O
M

P
O
W
E
R

S
U
P
P
L
Y

B
O
A
R
D
C
S
1
H
A
S

5
0
-
P
+5V
1
0
2
out
3
Vref
4
n
5
NC
6
7
7
8
8
9
9
1
0
1
0
1
1
1
1
1
2
1
2
C
4
7330u 10V
G
R
D

C
u
r
r
e
n
t

M
E
S
.
R
3
3
1
k
+
2
4

V
C
3
8
100n, 25 V
J
7
C
O
N
2
12
C
O
N
N
E
C
T
O
N

O
F

L
2
:

L
C
L

F
L
T
E
R

N
D
U
C
T
O
R
C
O
N
N
E
C
T
O
N

O
F

L
1
:

L
C
L

F
L
T
E
R

N
D
U
C
T
O
R
C
1
2
.
2
u
F
,

6
3
0
V
C
3
9
330n, 25 V
C
3
7
10n, 15 V
D
1
9
1
N
4
1
4
8
1 2
D
2
0
1
N
4
1
4
8
1 2
C
4
0
100n, 25 V
+
5

V
T
O

G
R
D

N
E
U
T
R
A
L
C
4
1
100n, 25 V
Q
1
B
C
5
4
7
B
Q
2
B
C
5
4
7
B
J
8
OUTPUT C ONNECTOR
21
C
4
4
100n, 25 V
R
2
1
.
5
k
R
3
1
.
5
k
C
4
5
1u, 25 V
J
9
C
O
U
P
L
N
G

N
D
U
C
T
O
R

C
O
N
N
E
C
T
O
R
2
1
T
O

G
R
D

P
H
A
S
E
C
4
6
100p, 25 V
G
R
D

C
u
r
r
e
n
t

M
E
S
.
J
1
4
B
N
C
1
2
R
e
la
y

C
o
n
t
r
o
l
+
1
5

V
+
5

V
1
2
J
1
5
B
N
C
1
2
1
+
5

V
2
R
3
2
4
.
7
k

1
%
Doc ID 16555 Rev 3 29/55
Figure 16. Schematic of the AC voltage measurement circuit
The circuit is supplied by the 5 V bus generated by the multi-output power supply and the
measured voltage is fed through connector J11. The output voltage of this circuit is then
equal to the sum of the measured voltage plus an offset voltage according to the following
equation:
Equation 52
Where V
meas
is the voltage on J11, V
cc
is the 5 V supply voltage and V
out
is the voltage on
pin 8 of the operational amplifier. The line current conditioning circuit was designed in a
similar way and the electrical scheme is shown in Figure 17:
AM05610v1
GND_Analog
GND_Analog
ADC_LNE_VOLTAGE
TESTPONT_S2
-
+
U3C
TS954PT
10
9
8
R12
180
AC LNE VOLTAGE SENSOR
J11
BNC
1
2
R11
390
GND_Analog
R13
1k2
+Vcc Analog
12 R / 13 R 11 R
12 R // 13 R
V
13 R // 11 R 12 R
13 R // 11 R
V V
cc . meas out
+
+
+

30/55 Doc ID 16555 Rev 3
Figure 17. Line current conditioning circuit
In this case the output voltage is given by:
Equation 53
Where: V
meas
is now the voltage output of the current sensor, having an offset of 2.5 V
generated by a TL431 configured as the voltage reference.
The same circuit in Figure 17 is used for the sensing of the DC bus voltage, PV array voltage
and PV array current.
In summary, the overall control architecture requires five feedback signals for correct
operation, input current and input voltage are used for maximum power point tracking;
inverter bus DC voltage, grid voltage and grid side current are used for grid-tied operation
and current injection. These signals are sent to the ADC inputs of the microcontroller,
according to the pin assignment of Figure 19 and sampled at 17.4 kHz (Figure 18).
Figure 18. ADC interrupt service routine
AM05611v1
GND_Analog
R9 10K
+Vcc Analog
GND_Analog
R8 560
R10
1.1k
GND_Analog
GND_Analog
R6
4k7
ADC_LNE_CURRENT
AC LNE CURRENT SENSOR
-
+
U3A
TS954PT
3
2
1
4
1
1
R7
10K
C25
100nF
-
+
U3B
TS954PT
5
6
7
GND_Analog
+Vcc Analog
J9
BNC
1
2
+5V
,
_
+
+
7 R
6 R
1 V
8 R 10 R
10 R
V
. meas out
AM05612v1
ADC ISR
SampIing Period Ts = 59us (17kHz)
Timer Res = 16.6ns
PWM (Center aligned mode)
ControI
Loop (AD ISR)
U on overflow U on overflow
Wait State
(main Ioop)
A
N
3
0
9
5
S
c
h
e
m
a
t
i
c

d
e
s
c
r
i
p
t
i
o
n
D
o
c

I
D

1
6
5
5
5

R
e
v

3
3
1
/
5
5
Figure 19. STM32F103xx microcontroller schematic
AM05613v1
C57
180p
GND
RESET#
C52
180p
GND
C54
180p
GND
C58
180p
PC14 OSC32_N
C19
10uF
GND
GND
GND
A0_DAC
GND
A1_DAC
L1
BLM41PG600SN1L
Y1
32.768Khz 472-0887
1 2
C8
10pF
C18
10nF
C7
10pF
PF0
PE7 D4
DATA N (DAC)
3V3
R70 0
SCLK (DAC)
ADC_BUS_VOLTAGE
J4
JUMPER_3
1
2
3
ADC_PANEL_CURRENT
R5
47
PA5 SP1_SCLK
OSCOUT
OSCN
GND
GND
Y2
8Mhz
1
2
PB7 USART1_RX
C10 22pF
FSMC_NE4
C9
22pF
PA6 SP1_MSO
U11
STM32F103ZET6
OSC_N
23
OSC_OUT
24
NRST
25
PC0
26
PC1
27
PC2
28
PC3
29
PA0-WKUP
34
PA1
35
PA2
36
PB12
73
PB13
74
PB14
75
PB15
76
PD8
77
PD9
78
PD10
79
PD11
80
PD12
81
PD13
82
PD14
85
PD15
86
PC6
96
PC7
97
PC8
98
PC9
99
PA8
100
PA9
101
PA10
102
PA11
103
PA12
104
NOT CONNECTED
106
PC10
111
PC4
44
PC5
45
PD0
114
PD1
115
PD2
116
PD4
118
PD5
119
PD6
122
PD7
123
BOOT0
138
PA3
37
V
S
S
_
1
7
1
PA4
40
PA5
41
PA6
42
PA7
43
PB0
46
PB1
47
PB2
48
V
D
D
_
1
1
3
1
PA13
105
PA14
109
PA15
110
PB8
139
PB9
140
PB10
69
PB11
70
PB7
137
PB6
136
PB5
135
PB3
133
PB4
134
PC11
112
PC12
113
PC13-ANT_TAMP
7
PC14-OSC32_N
8
PC15-OSC32_OUT
9
PE14
67
PE13
66
PE12
65
PE11
64
PE10
63
PE9
60
PE8
59
PE7
58
PE6
5
PE5
4
PE4
3
PE3
2
PE2
1
PE1
142
PE0
141
PE15
68
PF15
55
PF14
54
PF13
53
PF12
50
PF11
49
PF10
22
PF9
21
PF8
20
PF7
19
PF6
18
PF5
15
PF4
14
PF3
13
PF2
12
PF1
11
PF0
10
PG15
132
PG14
129
PG13
128
PG12
127
PG11
126
PG10
125
PG9
124
PG8
93
PG7
92
PG6
91
PG5
90
PG4
89
PG3
88
PG2
87
PG1
57
PG0
56
PD3
117
V
S
S
_
2
1
0
7
V
S
S
_
3
1
4
3
V
S
S
_
4
3
8
V
S
S
_
5
1
6
V
S
S
_
6
5
1
V
S
S
_
7
6
1
V
S
S
_
8
8
3
V
S
S
_
9
9
4
V
S
S
_
1
0
1
2
0
V
S
S
_
1
1
1
3
0
V
D
D
_
2
1
2
1
V
D
D
_
3
9
5
V
D
D
_
4
8
4
V
D
D
_
5
6
2
V
D
D
_
6
5
2
V
D
D
_
7
1
7
V
D
D
_
8
3
9
V
D
D
_
9
1
4
4
V
D
D
_
1
0
1
0
8
V
D
D
_
1
1
7
2
V
D
D
_
A
3
3
V
S
S
_
A
3
0
V
R
E
F
-
3
1
V
R
E
F
+
3
2
V
B
A
T
6
GND
D
[
0
-
1
5
]
ADC_PANEL_VOLTAGE
D14 PD9
J7
JUMPER_3
1
2
3
PC15 OSC32_OUT
KEY-LEFT
KEY-RGHT
PD8 D13
KEY-UP
KEY-DOWN
KEY-CENTER
PG12 FSMC_NE4
TCK/SWCLK
TMS/SWDO
TD
TDO/SWO
TRST
PA13 JTAG
3V3
PA15 JTAG
PA14 JTAG
PB0 TM8_CH2N
D8
D10
D11
D9
D7
D12
GND
D[0.. 15]
PG7 KEY-CENTER
D15 PD10
C60
180p
D2 PD0
GND
D3 PD1
C53
180p
D6
D5
PA1 RELAY-GRD
PWM4_3V3
PWM1_3V3
PWM5N_3V3
PWM5_3V3
PWM4N_3V3
PWM3N_3V3
PWM3_3V3
C11
10nF
RELAY_GRD
GND
PA7 SP1_MOS
PB1 TM8_CH3N
C20
100nF
C21
100nF
C22
100nF
C23
100nF
C24
100nF
GND
TX_0
PG14 KEY-LEFT
PD3 KEY-DOWN
D0 PD14
VREF+
D1 PD15
C12
100nF
FSMC_NWE
PG13 KEY-RGHT
PB6 USART1_TX
PC0 ADC123_N10
ENABLE (DAC)
PC1 ADC123_N11
PC2 ADC123_N12
PG15 KEY-UP
PC6
C13
100nF
PB12 ENABLE (DAC)
PC3 ADC123_N13
C14
100nF
PD5 FSMC-NWE
C15
100nF
C16
100nF
PC4 ADC12_N14
PA9 TM1_CH2
3V3
PC5 ADC12_N15
GND
3V3
FSMC_NOE
PB11 SYNC (DAC)
PWM2_3V3
C51
180p
PD4 FSMC-NOE
GND GND
C56
180p
GND
3V3
PC7 TM8CH2
C61
180p
PB14 TM1_CH2N
GND
RESET
C59
180p
PC8 TM8CH3
C62
180p
R4
10k
GND
GND
SYNC (DAC)
GND
C17
100nF
J22
CON3
1
2
3
3V3
PA2 TM2_CH3 PHASE SHFT
GND
PA3 TM2_CH4 PHASE SHFT+DT
R2 10k
3V3
R60 0
GND
D
[0
-
1
5
]
3V3
USER_BUTTON
ADC_LNE_CURRENT
PG8 USER-BUTTON
GND
RX_0
R1
10k
BOOT1 PB2
LDAC (DAC)
PB10 LDAC (DAC)
R3 390
VDDA
ADC_LNE_VOLTAGE

3V3
3V3
GND
C55
180p
GND
A0
32/55 Doc ID 16555 Rev 3
Figure 20. DC-DC converter driver
AM05614v1
C
6
1
u
2
5
V
P
W
M
1
R
1
1
4
7
P
W
M
2
D
2
3
1
5
V
1
W
1 2
R
1
2
4
7
R
5
1
2
R
1
3
4
7
D
1
3
1
5
V
1
W
1 2
R
6
1
2
U
1
M
7
4
H
C
T
7
0
0
7
V
C
C
1
4
6
A
1
3
6
Y
1
2
5
Y
1
0
5
A
1
1
4
A
9
G
N
D
7
1
A
1 2
1
Y
2
A
3
3
Y
6
3
A
5
2
Y
4
4
Y
8
C
1
0
1
0
u
2
5
V
R
7
1
2
R
8
1
2
C
8
1
0
u
2
5
V
D
1
4
S
T
T
H
1
L
0
6
1
2
Q
9
2
S
D
8
8
2
Q
1
1
2
S
B
7
7
2
G
1
1
5
V
L
1 Q
1
0
2
S
D
8
8
2
Q
1
2
2
S
B
7
7
2
G
1
N
D
1
5
S
T
T
H
1
L
0
6
1
2
S
O
U
R
C
E
M
O
S
H
G
H
1
S
O
U
R
C
E
M
O
S
L
O
W
1
C
7
2
.2
u
2
5
V
1
5
V
L
1
R
2
4
4
7
C
2
L
6
3
8
6
D
S
D
2
V
C
C
4
L
N
1
H
V
G
1
3
G
N
D
8
H
N
3
C
N
6
D
A
G
5
N
C
1
0
S
G
N
D
7
L
V
G
9
O
U
T
1
2
N
C
1
1
1
V
B
O
O
T
1
4
S
O
U
R
C
E
M
O
S
L
O
W
2
S
O
U
R
C
E
M
O
S
H
G
H
2
C
9
2
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u
2
5
V
1
5
V
L
2
C
4
L
6
3
8
6
D
S
D
2
V
C
C
4
L
N
1
H
V
G
1
3
G
N
D
8
H
N
3
C
N
6
D
A
G
5
N
C
1
0
S
G
N
D
7
L
V
G
9
O
U
T
1
2
N
C
1
1
1
V
B
O
O
T
1
4
C
1
H
C
P
L
4
5
0
6
N
C
1
C
A
T
H
O
D
E
3
V
C
C
8
A
N
O
D
E
2
V
L
7
N
C
4
G
N
D
5
V
O
6
1
5
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L
1
D
1
0
5
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V
5
0
0
m
W
1 2
R
1
3
3
0
R
2
1
0
k
5
V
D
C
/
D
C
P
W
M
1
Y
1
5
V
L
2
C
3
H
C
P
L
4
5
0
6
N
C
1
C
A
T
H
O
D
E
3
V
C
C
8
A
N
O
D
E
2
V
L
7
N
C
4
G
N
D
5
V
O
6
D
1
1
5
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V
5
0
0
m
W

1 2
R
3
3
3
0
R
4
1
0
k
5
V
D
C
/D
C
P
W
M
2
Y
5
V
D
C
/
D
C
Q
1
3
2
S
D
8
8
2
Q
1
4
2
S
B
7
7
2
G
2
D
C
D
C
L
2
N
M
V
0
5
1
5
S
A
Vcc
2
15 V
4
Gnd
1
0
3
5
V
D
C
/D
C
5
V
D
C
/D
C
C
1
1
0
0
n
1
5
V
C
4
1
0
0
n
1
5
V
D
C
D
C
L
1
N
M
V
0
5
1
5
S
A
Vcc
2
15 V
4
Gnd
1
0
3
1
5
V
L
2
1
5
V
L
1
1
5
V
L
2 Q
1
5
2
S
D
8
8
2
Q
1
6
2
S
B
7
7
2
G
2
N
C
1
1
1
0
0
n
2
5
V
C
1
1
2
1
0
0
n
2
5
V
C
2
1
0
0
n
2
5
V
C
3
1
u
2
5
V
C
1
2
0
1
0
0
n
P
W
M
1
Y
P
W
M
2
YC
5
1
0
0
n
2
5
V
A
N
3
0
9
5
S
c
h
e
m
a
t
i
c

d
e
s
c
r
i
p
t
i
o
n
D
o
c

I
D

1
6
5
5
5

R
e
v

3
3
3
/
5
5
Figure 21. DC-AC converter driver
AM05615v1
C24
100n 25V
R27 56
SOURCE GBT H GH 4
R22
1k 1W-1%
D116
STTH110A
R29 47
-5 V L4
C16
10n
G4N
C27
100p 35V
DRAN GBT HG
C30
100n 25V
15 V H4
SOURCE GBT LOW 4
C8
HCPL 4506
NC
1
CATHODE
3
VCC
8
ANODE
2
VL
7
NC
4
GND
5
VO
6
C12
TD350
N
1
FAULT
3
DESAT
14
LVOFF
7
VREF
2
GND
8
COFF
5
NC
6
CLAMP
9
VL
10
VH
13
NC
4
OUTL
11
OUTH
12
D117
5.1V
1
2
R28
4.7k 1%
R14
100
15 V H4
R15
10k
SOURCE GBT H GH 4
PWM4
SOURCE GBT LOW 4
-5 V H4
R17 47
G4
C12
100p 35V
C119
100n 25V
R16
4.7k 1%
SOURCE GBT H GH 4
SOURCE GBT H GH
C93
47uF 25V
D9
10V
1
2
C9
HCPL 4506
NC
1
CATHODE
3
VCC
8
ANODE
2
VL
7
NC
4
GND
5
VO
6
C7
TD350
N
1
FAULT
3
DESAT
14
LVOFF
7
VREF
2
GND
8
COFF
5
NC
6
CLAMP
9
VL
10
VH
13
NC
4
OUTL
11
OUTH
12
C89
47uF 25V
C50
470p
C23
470p
C53 100n 25V
-5 V L5
15 V L5
5 V DC/AC
C52
100n 15V
SOURCE GBT LOW 5
DCDC L5N
NMD050515S
V
c
c
1
0
7
G
n
d
2
0
5
1
5
V
6
5
V
4
C94
47uF 25V
D24
STTH110A
C25
470p
C91
47uF 25V
C40
10n
15 V L5
C16
HCPL 4506
NC
1
CATHODE
3
VCC
8
ANODE
2
VL
7
NC
4
GND
5
VO
6
SOURCE GBT LOW 5
D118
5.1V
1
2
R42
100
15 V L5
R43
10k
PWM5N
C41
100n 25V
R45 56
R46
1k -1%
R47 47
-5 V L5
G5N
C47
100p 35V
C51
100n 25V
R36
1k 1W-1%
SOURCE GBT LOW 5
C29
470p
C17
TD350
N
1
FAULT
3
DESAT
14
LVOFF
7
VREF
2
GND
8
COFF
5
NC
6
CLAMP
9
VL
10
VH
13
NC
4
OUTL
11
OUTH
12
C88
47uF 25V
R48
4.7k 1%
SOURCE GBT H GH 5
D19
STTH110A
SOURCE GBT LOW 5
C90
47uF 25V
R19
10k 1%
R18
10k 1%
D17
STTH110A
C31
10n
15 V H5
C14
HCPL 4506
NC
1
CATHODE
3
VCC
8
ANODE
2
VL
7
NC
4
GND
5
VO
6
SOURCE GBT HGH 5
D16
5.1V
1
2
R32
100
15 V H5
R33
10k
PWM5
C32
100n 25V
R34 56
R35
1k -1%
R39 47
-5 V H5
G5
C37
100p 35V
C38
100n 25V
SOURCE GBT H GH 5
C15
TD350
N
1
FAULT
3
DESAT
14
LVOFF
7
VREF
2
GND
8
COFF
5
NC
6
CLAMP
9
VL
10
VH
13
NC
4
OUTL
11
OUTH
12
R40
4.7k 1%
DRAN GBT HGH 5
SOURCE GBT HGH 5
D20
10V
1
2
D21
10V
1
2
15 V L4
-5 V L4
5 V DC/AC
C26
100n 15V
DCDC L4N
NMD050515S
V
c
c
1
0
7
G
n
d
2
0
5
1
5
V
6
5
V
4
SOURCE GBT LOW 4
C87
47uF 25V
D22
10V
1
2
C92
47uF 25V
R37 56
SOURCE GBT H GH 4
15 V H4
-5 V H4
C17
100n 15V
5 V DC/AC
DCDC L4
NMD050515S
V
c
c
1
0
7
G
n
d
2
0
5
1
5
V
6
5
V
4
R20
10k 1%
R23
10k 1%
15 V H5
SOURCE GBT HGH 5
V DC/ AC
C39
100n 15V
-5 V H5
DCDC L5
NMD050515S
V
c
c
1
0
7
G
n
d
2
0
5
1
5
V
6
5
V
4
C28
10n
15 V L4
SOURCE GBT LOW 4
D12
5.1V
1
2
R25
100
15 V L4
R26
10k
PWM4N
34/55 Doc ID 16555 Rev 3
The outputs of the microcontroller are the PWM signals used to control the power devices in
each leg of the conversion system.
Power MOSFETs and IGBTs must be interfaced to the control circuit while maintaining
galvanic isolation. Two slightly different solutions were implemented for the DC-DC and the
DC-AC converter. In the first, a L6386 IC with a bootstrap capacitor for a floating drive
supply was selected because of the low cost and the capability of driving a high-side and a
low-side device with a single IC, therefore simplifying the layout of the board. The opto-
isolator receives the signal generated by the microcontroller and performs the level shifting
of this signal from 0-5 V to 0-15 V. The opto-isolator output pin is connected to the L6386
input pin. A totem pole circuit, consisting of a PNP-NPN BJT pair, connects the output of the
IC to the gate of each MOSFET, amplifying the driving current and allowing fast switching,
both at turn-on and turn-off. The +15 V supply voltage of the IC and opto-isolator is provided
by an isolated DC-DC converter, as shown in Figure 20. A similar solution was used to drive
the IGBTs in the inverter bridge. The main difference is the use of a single driver IC, TD350,
characterized by 0.75 A/1.2 A source/sink current capability and includes some dedicated
control and protection functions such as IGBT desaturation, two level turn-off and fault
detection output. The circuit implemented is shown in Figure 21.
Doc ID 16555 Rev 3 35/55
Figure 22. 5 V,1 A flyback converter with VIPER17HN
AM05617v1
C
1
8
1
0
0
u
,
1
6
V

e
l
C
1
9
1
0
0
u
,
1
6
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l
.
R
1
6
1
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4
1
4
7
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n
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C
1
3
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.
2
n
F
D
1
B
A
T
4
6
C
4
2
2
u
F

2
5
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R
1
0
R
3
3
3
k
L
1
4
.
7
u
H
C
1
0
Y
K

4
7
u
F

2
5
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C
7
2
2
n
F
C
6
1
.
8
n
F
D
4
S
T
P
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5
L
4
0
C
9
M
C
Z

1
0
0
0
u
F

1
0
V
V
R
1
T
S
3
4
3
1
B
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2 3
1
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8
1
8
k

1
%
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9
3
.
9
k

1
%
R
1
0
4
7
0
k
-
+
B
R
1
B
R
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G
E
4
1
3
2
C
1
1
1
0
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F
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3
4
.
7
u
F

4
0
0
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D
3
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T
H
1
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0
6
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1
C
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2
1
2
F
1
1
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t
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C
1
1
0

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h
m

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C
1 2
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2
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9

-
1
0
3
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2
5
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2
1 3
4
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1
1
0
0
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X
2
D
2
1
N
4
1
4
8
R
1
4
1
8
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1
2
3
3
k
C
8
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1

2
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C
2
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4
0
0
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R
1
3
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.
2
k
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1
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1 2
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1
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A
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F
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4 5
9 7
2 1
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3
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1
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5
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6
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2
2
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1
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1
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k
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2
C
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2
1 2
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G
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2
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4
9
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2
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1
3
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4
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4
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2
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D
2
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1
3
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T
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V
D
D
F
B
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1
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I
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1
7
H
N
4 2
8 1
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7
V
O
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V
N
G
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D
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4
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4
9
4
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2
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5
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+
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D
C
/
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r
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d
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d
1
C
1
7
1
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,
1
6
V

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l
.
36/55 Doc ID 16555 Rev 3
Figure 23. Multi-output flyback converter with VIPER27HN
AM05616v1
2
4
V
C
O
N
2
12
V
O
U
T
V
N
G
N
D
U
6
L
7
8
1
5
A
B
D
2
T
-
T
R
1
3
2
J
5
/
1
5
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C
O
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3
123
1
2

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+
5

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C
/
D
C
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6
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1
5
V
C
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3
123
G
N
D

D
C
/
D
C
5

V

C
B
+
5

V

D
C
/
A
C
G
N
D

C
B
G
N
D

D
C
/
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7
8
1
2
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2
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r
id
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r
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2
3
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3
4
1
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5
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1
5

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3
6
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5
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3
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5
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1
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3
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5
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5

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1
2
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3
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1
5

V
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4
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3
4
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1
2
3
4
5
6
7
8
9
1
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1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
9
2
1
2
3
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2
6
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7
2
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2
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6
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1
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1
4
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5
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6
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3
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6
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3
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2
5
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+
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Doc ID 16555 Rev 3 37/55
The isolated DC-DC converters used in the driver circuits are supplied by a 5 V bus
generated by an offline flyback converter, with wide input voltage, using VIPER 17HN
according to the electrical scheme of Figure 22. The circuit is capable of delivering up to 5
W and feeds the control circuitry of the main DC-DC converter, the DC-AC inverter and the
control board through 5 V voltage regulators.
In a similar way, the 24 V and +/-15 V bus is generated with a VIPER27HN device,
implementing a multi-output flyback solution.
STM32F103xx-based current control strategy for inverter grid connection AN3095
38/55 Doc ID 16555 Rev 3
6 STM32F103xx-based current control strategy for
inverter grid connection
A single-phase grid-connected inverter, with unipolar pulse-width modulation, operates from
a DC voltage source and is characterized by four modes of operation or states. Two modes
take place during the positive load current period and two modes in the negative load
current period, as shown in Table 6.
The switching patterns are defined by a control algorithm which generates the desired
outputs starting from the information provided by the feedback signals. For example,
algorithms for the grid connection are based on the use of current controllers, consisting of a
single loop or multiple loops according to the desired level of dynamics and accuracy.
Multiple-loop controllers are generally preferred, thanks both to their superior performance
and the relative ease of implementation in modern microcontrollers. With single-voltage loop
control methods, the inverter output voltage is compared with a sinusoidal reference,
proportional to the grid voltage and the generated error is then sent to the input of a current
regulator to create a sinusoidal reference for the PWM modulator. Despite its simple
implementation, this approach does not provide good regulation under non-linear loads and
is characterized by steady-state error. For these reasons, both output voltage and current
are used in control algorithms to provide better dynamic response and damping of the
resonant peak caused by the output LC or LCL filter. However, the time varying nature of the
controlled variables prevents an optimal regulation of output voltage and current. To
overcome such problems, a predictive current controller or deadbeat controller may be
implemented. The first approach, based on the assumption that a precise model of the
controlled system is available, predicts the inverter voltages required to force the measured
current to follow the reference current, but has the disadvantage of being difficult to
implement. The second method, while providing really fast dynamic response, is very
sensitive to system noise and is dependent on system parameters, [see References 12, 13,
14, 15, 16].
Recently, new methods such as the PR (proportional resonant) current control method have
been adopted to control the PV inverters with zero steady-state error and the possibility of
selective harmonic compensation with low computational effort. However, implementations
in low cost fixed-point microcontrollers have been proven to be difficult due to limited
computational capability and restricted numerical representation.
Another possible current-control method uses DQ synchronous reference frames and
provides both the advantage of zero steady-state error, thanks to the use of PI controllers,
and simple implementation.
Table 6. Operating modes of grid-connected voltage source inverter
Mode Z1 Z2 Z3 Z4 D3 D4 V
out
I
out
1 On Off Off On Off Off Vbus +
2 On Off Off Off On Off 0 +
3 Off On On Off Off Off -Vbus -
4 Off On Off Off Off On 0 -
AN3095 STM32F103xx-based current control strategy for inverter grid connection
Doc ID 16555 Rev 3 39/55
For these reasons, this method was implemented on a 32-bit ARM-based STM32F103xx
microcontroller and its performance was verified through simulations and experimental
results on the grid connected inverter.
A block diagram of the implemented control algorithm is shown in Figure 24.
Figure 24. Block diagram of the implemented control
Every algorithm for grid-connected inverter operation is based on the estimation or direct
measurement of grid-voltage frequency and phase angle. Both parameters are fundamental
for correct operation and special care must be taken in their detection to avoid the influence
of any external noise. The detection method used in this implementation for a single-phase
inverter is based on a synchronous reference frame PLL. While in three-phase inverters the
use of DQ based PLL is quite common, for single-phase inverters, the necessity of a virtual
bi-phase system arises. In fact, to create a rotating DQ reference, starting from a stationary
frame, at least two independent phases are required. This problem is overcome with the
creation of a virtual voltage, V
, phase-shifted with respect to the real grid voltage, V
, of
90. This task may be easily accomplished with firmware. If the two voltage components V

and V
are available, the transformation from the stationary reference frame to the DQ
rotating frame is given by:
Equation 54
where is the angle between the DQ reference frame and the stationary reference frame
(Figure 25). The reverse transformation is given by:
Equation 55
AM05618v1
DQ PLL
e
(Grid Angle)
AC Voltage
DC
AC
Grid Angle estimation
d,q
,
DC
DC
V
*
PV
DQ coordinates by a virtual bi-phase system
Coupling Reactor
Inverter
Current
Grid Voltage
PI
(Phase shift)
Voltage &
Current
PV Current
PV Voltage
Power Estimation
SW
90
I
q
I
d
V
*
bus
Q
*
=0
V
q
V
d
I
d
I
q
DQ Power
Estimation
PI
I
*
q
I
*
d
PI
Cross Coupling
Control
Reverse Park
,
d,q
Q
i
i
d
e
(Grid Angle)
PI
T
Phase Shift
Controller
LCL Filter
DC/AC Converter
Direct Park.
Digital control on C
Voltage
Sensing
V
bus
Delay
Panel Voltage
& Current
Sensing
e
(Grid Angle)
coordinates by a virtual bi-phase system
Grid Voltage gg
I
q
I
d
V
*
bus
Q
*
=0
V
q
V
d
I
d
I
q
I
*
q
I
*
d
Q
i

i
d
e
(Grid Angle)
Direct Park.
V
bus
Delay
DQ
T
DQ PLL DQ PLL
e
(Grid Angle)
AC Voltage
DC
AC
d,qq
,
d,q
,
DC
DC
V
*
PV
DQ coordinates by a virtual bi-phase system
Coupling Reactor
Inverter
Current
Grid Voltage
PI PI
(Phase shift)
Voltage &
Current
Sensing
PV Current
PV Voltage
Power Estimation Power Estimation
SW SW
90 90
I
q
I
d
V
*
bus
Q
*
=0
V
q
V
d
I
d
I
q
DQ Power
Estimation
DQ Power
Estimation
PI PI
I
*
q
I
*
d
PI PI
Cross Coupling
Control
Cross Coupling
Control
Reverse Park
,
d,q
,
d,q
Q
i
i
d
e
(Grid Angle)
PI PI
MPPT
Phase Shift ff
Controller
Phase Shift
Controller
LCL Filter
DC/AC // Converter
DDCC
AACC
DDCC
DDCC
DC/AC Converter
Direct Park.
Voltage
Sensing
V
bus
Delay
Panel Voltage
& Current
Sensing
1
]
1
1
]
1
1
]
1
V
V
cos sin
sin cos
V
V
q
d
1
]
1
1
]
1
1
]
1
q
d
V
V
cos sin
sin cos
V
V
40/55 Doc ID 16555 Rev 3
Figure 25. Stationary reference frame and rotating reference frame
Where
Equation 56
Then the two components on the DQ reference frame are:
Equation 57
Therefore, if =
e
the two components are reduced:
Equation 58
In order to detect the grid-voltage angle, used to perform the transformation, a PLL structure
may be used. In Figure 25, the block diagram of the PLL implemented in this application is
shown.
Figure 26. Implemented PLL structure
AM05619v1

O d
s

q
e

d
e

0
q
s

V
e
V
grid
0
e

1
]
1
1
]
1
e m
e m
sin V
cos V
V
V
) sin( V cos sin V sin cos V Vq
) cos( V sen sen V cos cos V Vd
e m e m e m
e m e m e m
+
+
0 Vq
V Vd
m
AM05620v1
Grid Voltage
O
e
(Grid Angle)
e
FF
AnaIog
to DigitaI
Converter
90
O
e
V
o
Vgrid
V
d,q
u,
PI PI
Vd
Vq
-
Vd
`
0

SW
HW
Park
Transformation
AC MAIN
VoItage
Sensing
& ScaIing
Doc ID 16555 Rev 3 41/55
The grid voltage and the 90 phase-shifted voltage are used to perform the reference frame
change, or park transformation, and create two voltage components on the DQ reference
frame called V
d
and V
q
. One of the two components is controlled to zero with a PI regulator.
The output of the PI regulator is the grid frequency which may be integrated to obtain the
grid angle.
It is worth knowing that if the V
q
component is controlled to zero then the V
d
component
follows the grid-voltage rotation. In this case, the active power injected into the grid may be
controlled, transforming the current in the same reference frame and by acting on the
amplitude of the Id component. The Iq component must also be controlled in order to ensure
zero reactive power injection. On the contrary, if the V
q
component is controlled to zero in
the PLL, the active power is controlled with the Iq current component and the Id current
component is used to control the reactive power to zero or to the desired value.
This said, the advantages of such a control structure are clear: first of all the current
components on the synchronous reference frame are constants and may then be controlled
with standard PI regulators ensuring zero steady-state error; the second advantage is a
decoupled control of active and reactive power.
The reference values for the active and reactive component of the current are set by two
additional PI regulators in the outer control loop. The active reference current component is
generated by confronting the DC bus voltage with the reference voltage value. The error
between the actual value and the reference DC bus voltage is sent to a PI regulator whose
output is the active current component value (Figure 26).
Similarly, the reactive current reference value is set by another PI regulator whose input is
the error generated between the reactive power command and the actual estimated value.
Figure 27. DQ components of the current
The difference between reference components of the current and the actual DQ
components are the inputs of the PI regulators in the inner control loop. The outputs of the
PI regulators in the inner loop are two voltage components, V
d
and V
q
. By performing a
reverse park transformation, two AC voltages are generated back to the stationary reference
frame, and therefore the generation of the modulating signals of the DC-AC converter may
be executed by the microcontroller.
The amount of power injected into the grid depends on the power available from the PV
array. This power is then processed by the DC-DC converter which is controlled in order to
maximize the energy yield from the array, independent to temperature variations and
irradiation conditions, by controlling its input impedance. The control of the input impedance
requires both PV array current and voltage sensing and some simple calculations executed
AM05621v1

d
s

O
d
e

0
I
I

I
o

I
q
e

I
d
e

0
q
s

q
e

42/55 Doc ID 16555 Rev 3
by the well known maximum power point algorithm. The main functions of the MPPT
algorithm are shown in Figure 28.
Figure 28. Block diagram of the implemented MPPT algorithm
The block diagram is an explanation of the perturb and observe (P and O) method, a very
common and easy way to implement an MPPT technique. The PV array voltage is
compared to a constant reference voltage, which corresponds, once the algorithm has
reached the convergence, to the PV array voltage at the maximum power point, under
specific atmospheric and temperature conditions. The error signal is used as the input of a
PI regulator which generates a command (phase-shift angle) used to drive the power
devices of the DC-DC converter. The reference voltage is the output of the flow chart of
Figure 27 where, based on the calculation of PV output power by sampling input voltage and
current values, the power change is detected, by comparing the present and previous
voltage levels, together with the change of the input voltage. Therefore, the reference
voltage is incremented or decremented according to both array power and voltage change,
[see References 17, 18].
Apart from gird connection and MPPT, some other functions are implemented for the correct
operation of the conversion system. The following is a brief description of these functions:
Input voltage control
Input voltage value is constantly monitored to ensure that the array voltage is always in the
correct operating range, between 200 V and 400 V. The voltage value is also utilized to
minimize the conversion ratio between the input and output of the DC-DC converter. For
example, if the input voltage is between 200 V and 250 V the output voltage is regulated at
400 V. For higher input voltage values the reference bus DC voltage is regulated at 450 V. In
this way, the conversion ratio for the DC-DC converter is minimized and the efficiency
improved. If the input voltage value is below 200 V or above 400 V, the input
under/overvoltage protection is enabled. Consequently, the modulation is disabled in both
stages and the relays disconnect the system from the grid. For the sake of security the
complementary pairs must be disabled synchronously in case of power stage failure/fault
and this is performed by a dedicated emergency stop input embedded in the peripheral.

AM05622v1

AC Mains
Supply Voltage
DC
AC
DC
DC
PV
LCL Filter
DC
AC
DC
DC
DC/AC Converter
A/D
V I
V
ref
Calculation
+

STM32
PI
Regulator
Phase Shift
Controller
Sense
V(k),I(k)
P(k)=V(k)*I(k)
P(k)>
P(k-1
V(k)>
V(K-1)
Vref=Vref
-C
Vref=Vref
+C
Vref=Vref
-C
Vref=Vref
+C
Y N
Y
Y N N
V(k)>
V(K-1)
Doc ID 16555 Rev 3 43/55

Input current control
The same kind of strategy is used to detect any condition of overcurrent in the system. This
protection is enabled when the average input current is above 18 A.
Bus DC voltage control
The output of the bus DC is controlled in order to stabilize the inverter input voltage to the
bus DC reference voltage. The minimum DC bus voltage is a function of the peak-to-peak
AC line voltage in order to minimize total harmonic distortion (THD) of the injected current.
This limit depends on grid-voltage fluctuations and may be calculated according to the
following equation:
Equation 59
where P
dc
is the average power on the DC bus, V
grid_max
is the maximum RMS value of the
grid voltage and Z
c
is the output LCL filter impedance. In other words, the DC bus must
never decrease below the peak grid-voltage value plus the drop across the IGBTs and the
LCL filter. To ensure safe operation, this voltage must never surpass the protection threshold
of 480 V.
In case of bus DC under/overvoltage the system is disconnected from the grid according to
the strategy already described.
Burst mode operation at startup
In the case of an overcurrent or overvoltage event, the DC-DC converter modulation is first
disabled by the control algorithm. Then, the DC-DC modulation is disabled and the interface
relays are disconnected, preventing any power flow from the system to the grid. After that,
the control algorithm performs some checks on the input voltage, bus DC voltage, grid-
voltage and grid-frequency value. If the sensed voltages are in the allowable range (200-400
V input, 380-450 V bus DC, 230 Vrms +/- 10 %, 49.7 Hz-50.3 Hz grid voltage) the DC-DC
converter is started in burst mode in order to charge the bus DC voltage at the reference
voltage level. This same check procedure is executed at startup, before the connection to
the grid is actually performed. During burst mode of operation the DC bus voltage is
regulated with hysteretic control. The boundary values of the hysteresis window Vb
1
, Vb
2

are chosen to limit the DC bus voltage ripple to 5 % of the reference value. Once the bus
capacitor is charged, the control loop mode of operation is enabled and the connection to
the grid performed.
Line voltage and frequency detection and anti-islanding
The PLL continuously measures the line voltage and frequency in all operating states. If the
voltage or frequency exceeds the high or low limits, the inverter ceases to deliver power to
the grid. These conditions are also used to implement a passive method for island operation
detection. An island operation occurs when the utility power is disconnected for
maintenance or fault reasons while the inverter is still delivering power. With a passive
method, detection of islanding from the utility grid is achieved via AC under/overvoltage and
under/overfrequency detection functions.
Output overcurrent
Due to fault conditions or AC line transient conditions, the maximum current may be
exceeded. In this case, the inverter ceases to deliver power to the grid according to the
strategy explained above. The current threshold value is set to 15 A.
,
_
+
max _ grid
c dc
max _ grid min _ ref bus
V
Z * P
V 2 V
44/55 Doc ID 16555 Rev 3

Open loop operation
This mode of operation was implemented to allow system debug independently from grid
operation. This mode, used for maintenance, test and debug, allows system operation only
with manual control by acting on a set of pushbuttons on the microcontroller board. The DC-
DC converter power transfer may be adjusted by acting on the phase-shift parameter
through the pushbutton placed on the microcontroller board. In the same way, the power
transfer of the DC-AC converter may be modified acting on the modulating index.
The dead time of the power bridges in each converter may also be adjusted.
LCD display
The microcontroller board is equipped with a graphic LCD display. The selectable functions
are:
1. Open-loop mode
2. Closed-loop mode
3. Calibration
4. DC-DC converter manual control
5. DC-AC converter manual control
It is important to note that the calibration function must be performed by the operator when
the system is first connected to the grid. In this way, any offset affecting the feedback signals
used for control mode operation is compensated via firmware. When the calibration function
is executed the display shows a grid current offset of about 2.5 V and a grid-voltage offset of
about 1.8 V.
AN3095 Experimental results
Doc ID 16555 Rev 3 45/55
7 Experimental results
Control issues have been thoroughly investigated and the possibility of implementing the
algorithm using a 32-bit ARM-based microcontroller from STMicroelectronics is verified. The
dedicated control board, developed for this purpose, is equipped with an STM32F103xx
microcontroller, characterized by a 32-bit CORTEX TM-M3 core with suitable peripherals.
The core, running at 72 MHz, is able to perform up to 90 MIPS. A high performance CPU,
based on Harvard architecture, plus suitable peripherals such as two advanced PWMs, fast
and accurate 12-bit A/D conversions with double S and H circuit and high resolution timers,
allows the implementation of very sophisticated control algorithms.
The control loop has been synchronized with the A-D conversions triggered by the ON
states of the two PWM timers. This brings benefits in terms of accuracy, avoiding the
acquisition of analog quantities (e.g. currents) during commutations of the power devices.
The execution time of the most relevant tasks is reported in Table 7.
The entire control loop is executed in about 30 s (50 % CPU-load) with a sampling time of
57 s. Further code may be executed in the remaining 50 %, allowing the implementation of
a HMI (human machine interface) such as LCD driving or a graphical user interface via SPI,
in order to have a complete smart-platform.
For this application, the three main control issues regarding a PV converter, namely, MPPT,
grid synchronization and power management control, have been included within the
firmware. All the PWM signals, necessary for power management, are generated with
proper dead-time, settable with a resolution of 16.6 ns by acting on the firmware developed
for this application. The algorithm may control both the active and reactive power in the DQ
synchronous frame, while the implemented MPPT algorithm is based on the P and O
method and may be optimized with simple modifications to the source code. The inverter
current is transformed, using Park equations, in the two components referred to the rotating
DQ reference frame of the grid voltage. These components, Id and Iq, are proportional to
active and reactive generated power, respectively. The reference current value of q axis, I*q,
is calculated in order to regulate the voltage of the DC bus Vbus. Reactive power is
maintained at zero through I*d, as only the injection of active power into the mains is
allowed, according to international standards. PI outputs are transformed back into AC
quantities, using the inverse park transformation, providing the signals for inverter
modulation. The most critical task of the power management control is the estimation of the
Table 7. Execution time of the main control functions
Function Execution time
n.5 A/D acquisitions 1 s
MPPT 1.5 s
DQ_PLL+internal PID 10 s
Direct park transf 5 s
PI regulator 3 s each
Reverse park transf 5 s
Sine modulation 1.5 s
Total control loop execution time @ 72 MHz 30 s
Experimental results AN3095
46/55 Doc ID 16555 Rev 3
grid angle. The required software and hardware operations of the PLL have been performed
with the same microcontroller used for the main digital control. The experimental results may
be seen in Figure 29 and 30, where the grid angle (in yellow) is drawn together with the
voltage component on the d axis (green track) of the synchronous reference frame, which is
controlled to zero. Figure 31 shows the synchronization between the estimated angle and
the two voltages on the stationary reference frame, namely, the grid voltage (red track) and
the 90 phase-shifted voltage (blue track), [see References 19, 20].
Figure 31. Grid angle (yellow), grid voltage (red), 90 phase-shifted voltage (blue)
The phase-shift modulation (Figure 32) for the DC-DC stage is also implemented in the
digital control loop. The STM32F103xx microcontroller allows a high resolution phase shift
(16 ns), thanks to 16-bit timers, with a consequent advantage in terms of output voltage
regulation of the DC-DC converter. In Figure 33, the driving signals of M1 and M6 are
drawn, together with the HF transformer current in CCM and the M1 drain current under
ZVS operation. Commutation of the device M1 may be seen in Figure 34, where the control
signal is shown together with the drain source voltage and drain current at 200 V and 5 A
input. Figure 35 shows phase-shift and control signals (Ch1, Ch2), transformer primary
voltage (Ch3), and secondary voltage (Ch4).
Figure 29. Grid angle and V
d
component Figure 30. Grid angle and grid voltage

Doc ID 16555 Rev 3 47/55
The PWM embedded peripheral used for the DC-AC stage is configured to generate a
triangular carrier at 17.4 kHz with a resolution of 16,6 ns and programmable dead-time
insertion to avoid cross-conduction. For the sake of security the complementary pairs must
be disabled synchronously in the case of power stage failure/fault (e.g. overcurrent) and this
is performed by a dedicated emergency stop input embedded in the peripheral.
Inverter output voltage and current are shown in Figure 36, 37, 38 and 39 at different power
levels and both in standalone and grid-connected operation. The efficiency of the DC-DC
converter and overall system is shown in Figure 40 and 41, with different values of input
voltage. Further improvements in terms of efficiency are possible using the hybrid inverter
topology (two low frequency IGBTs and two high frequency MOSFETs). In this case the
modulating strategy controlling the high-side devices (MOSFETs) and the low-side devices
(IGBTs) must be modified according to the information in Figure 42 and 43, where the
modulation used for the high-side and low-side devices is shown. The proposed converter
performs with a power factor value higher than 90 % for any power level above 1 % of
Figure 32. DC-DC phase-shift modulation Figure 33. Phase-shifted signals, transformer
current in CCM, power MOSFET M1
drain current

Figure 34. Power MOSFET M1- Ch1 gate
signal; Ch2 drain-source voltage
and drain current Ch4
Figure 35. Phase-shifted gate signals (Ch1,
Ch2), primary and secondary
transformer voltage (Ch3, Ch4)

48/55 Doc ID 16555 Rev 3
nominal output power and current THD percentage slightly higher than 5 % at 2500 W
output power, as measured in Figure 44 and 45.
Figure 36. DC-AC voltage and current in
standalone mode (open-loop
operation)
Figure 37. Grid voltage (blue), inverter voltage
(red), injected current (green);
injected power (math function)

Figure 38. Inverter voltage (green) and current
(blue) at 800 W,PF=0.97
Figure 39. Inverter voltage (green) and current
(yellow) at 2500 W, PF

Doc ID 16555 Rev 3 49/55
Figure 40. DC-DC converter efficiency at
different input voltages
Figure 41. System efficiency

Figure 42. MOSFET M1- Ch1 gate signal, Ch2
drain-source voltage and Ch 4 drain
current
Figure 43. Phase-shifted gate signals (Ch1,
Ch2), primary and secondary
transformer voltage (Ch3, Ch4)

AM05634v1
DC/DC Converter Efficiency
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0 500 1000 1500 2000 2500 3000
Output Power [W]
E
f
f
i
c
i
e
n
c
y
200V
300V
390V
AM05635v1
50/55 Doc ID 16555 Rev 3
Figure 44. Low-side device modulation (red
and blue track); high-side device
modulation (yellow track and green
track)
Figure 45. High-side device modulation in leg
1 (yellow track); high-side device
modulation in leg 2 (green track);
inverter output voltage (blue track)

AM05638v1
Power Factor Vs Output Power
0.6
0.7
0.8
0.9
1
0 500 1000 1500 2000 2500 3000
Output Power [W]
P
o
w
e
r

F
a
c
t
o
r
AM05639v1
Current THD
4
7
10
13
16
0 500 1000 1500 2000 2500 3000
Output Power [W]
T
H
D

%
AN3095 Conclusions
Doc ID 16555 Rev 3 51/55
8 Conclusions
This application note describes the design and performance of a power conversion
architecture characterized by high efficiency, good integration levels and galvanic isolation,
with the aim of demonstrating STMicroelectronics complete and high performing product
portfolio to implement any PV conversion system. For this reason, the power converter,
based on a dual-stage topology, has been investigated and experimentally evaluated for
photovoltaic applications. The converter performs MPPT and grid connection by means of
an ARM Cortex M3-based STM32F103xx microcontroller, which is proven to be well suited
for such an application. In fact, the implemented DQ axis control scheme shows excellent
regulation of both active and reactive power, as is also required for low power applications in
the near future. Simulation and experimental results have confirmed the consistency of the
proposed solution for PV generation systems.
References AN3095
52/55 Doc ID 16555 Rev 3
9 References
1. Review of PV Inverter Technology Cost and Performance Projections, 2006, NREL
Report No. SR-620-38771
2. The 4th edition of Solar Generation - a publication in cooperation between The
European Photovoltaic Industry Association and Greenpeace. September 2007
3. A review of single-phase grid-connected inverters for photovoltaic modules, IEEE
Transactions on Industry Applications, vol. 41, n. 5, sept/oct. 2005, pp. 1292-1306
4. Developing a 'next generation' PV inverter, in Proc. 29th IEEE Photovolt. Spec. Conf.,
May 19-24, 2002, pp. 1352-1355
5. A High Gain Transformer-Less DC-DC Converter for Fuel-Cell Applications, 36th
IEEE Power Electronics Specialists, Conference, 11-14 Sept. 2005, p. 2514 - 2520
6. High-frequency link inverter for fuel cells based on multiple-carrier PWM, IEEE
Transactions on Power Electronics volume 19, issue 4, sept. 2004 pp:1279 - 1288
7. Performance characterization of a high-power dual active bridge DC-to-DC converter,
IEEE Transactions on Industry Applications; volume 28, Issue 6, Nov.-Dec. 1992
pp:1294 - 130
8. Comparison study of phase-shifted full bridge ZVS converters, IEEE 35th Power
Electronics Specialists Conference, 2004, PESC 04, volume 1, pp: 533 - 539. 20-25
June 2004
9. Performance Optimization of a High Current Dual Active Bridge with a Wide Operating
Voltage Range, 37th IEEE Power Electronics Specialists Conference, PESC 06, 18-22
June 2006, pp:1-7
10. Transformer-Coupled Multiport ZVS Bi-directional DC-DC Converter With Wide Input
Range, IEEE Transactions on Power Electronics, volume. 23, n. 2, March 2008, pp:
771 - 781
11. A Three-phase Soft-switched High-power-density DC/DC Converter for High-power
Applications, IEEE Transactions on Industry Applications, volume 27, Issue 1, Jan.-
Feb. 1991 pp. 63 - 73
12. A single-stage three-phase grid-connected photovoltaic system with modified MPPT
method and reactive power compensation, IEEE Transaction on Energy Conversion,
volume 22, Issue 4, Dec. 2007, pp. 881-886
13. Intelligent PV module for grid-connected PV systems, IEEE Transaction Industrial
Electronics, vol. 53, Issue 4, Jun. 2006, pp: 1066-1073
14. Photovoltaic power conditioning system with line connection, IEEE Transaction on
Industrial Electronics, vol. 53, no. 4, Jun. 2006, pp. 1048-1054
15. Overview of control and grid synchronization for distributed power generation
systems, IEEE Transaction on Industrial Electronics, vol. 53, Issue 5, Oct. 2006, pp.
1398-1409
16. Advanced grid synchronization system for power converters under unbalanced and
distorted operating conditions, in Proc. 32nd IEEE Annual Conference, IECON06, Nov.
2006, pp: 5173 - 5178
17. Optimization of perturb and observe maximum power point tracking method, IEEE
Transactions on Power Electronics, vol. 20, no. 4, July 2005, pp. 963 - 973
18. Comparison of photovoltaic array maximum power point tracking techniques, IEEE
Transaction on Energy Conversion, vol. 22, no. 2, Jun. 2007, pp. 439-449
AN3095 References
Doc ID 16555 Rev 3 53/55
19. Analysis and Software Implementation of a Robust Synchronizing PLL Circuit Based
on the pq Theory, IEEE Transactions on Industrial Electronics, vol. 53, Issue 6, Dec.
2006, pp: 1919 - 1926
20. Stability of Photovoltaic and wind turbine grid-connected inverters for a large set of
grid impedance values, IEEE Transactions on Power Electronics, vol. 21, n. 1, Jan
2006, pp. 263-272.
Revision history AN3095
54/55 Doc ID 16555 Rev 3
10 Revision history

Table 8. Document revision history
Date Revision Changes
02-Aug-2010 1 Initial release.
21-Jun-2011 2
Modified: Figure 14
Added reference to the STEVAL-ISV002V2 demonstration board on
coverpage.
08-Nov-2012 3 Modified: Figure 22 and 23
AN3095
Doc ID 16555 Rev 3 55/55

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Schematic description AN3095

, phase-shifted with respect to the real grid voltage, V

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