design

Edited by Bill Travis

ideas
Scheme adds sequencing and shutdown control to regulator ....................89 MathCAD functions perform log interpolation ............................................90 Scheme improves on ow-cost keyboard ..........................................94 ADC interface conditions high-level signals............................................96 Two op amps provide averaged absolute value..............................98
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Scheme adds sequencing and shutdown control to regulator

Said Jackson, Equator Technologies Inc, Campbell, CA

odern microprocessor- or FPGA-based circuits require separate and independent power-supply voltages for the core and the I/O circuits. Some devices require stringent control of the turn-on characteristics and sequencing of these multiple power supplies to avoid internal parasitic current flows and consequent latch-ups. Although regulators exist with specific soft-start and shutdown inputs, it may be more cost-effective to use regulators that do not inherently provide these features and to add these features with external discrete devices. This Design Idea shows how to use an inexpensive Linear Technology (www.linear.com) LTC3701 dual switching regulator to provide a sequenced, and

standby-controlled, power supply for an Equator Technologies (www.equator. com) broadband-signal processor. You can also adjust the circuit for FPGA or generic microprocessor applications. The features of the circuit in Figure 1 increase the regulators stability beyond what you can achieve with the standard Linear Technology application-note circuit. The LTC3701 switching regulator, IC1, provides two independently adjustable output voltages with very high voltage accuracy at a cost compatible with consumer-type applications. Because of cost constraints, it does not provide the softstart or shutdown features present in other switching regulators. This design adds three discrete transistors to the conven-

tional regulator circuitry to provide both arbitrary power-on-sequencing control and a simultaneous-shutdown feature. Q3, Q4, and Q5 are inexpensive discrete
R1 R1 R1 R1 R1 = = = = = 37.4k = 1.20V VCORE. 47.5k = 1.30V VCORE. 66k = 1.50V VCORE. 93.1k = 1.80V VCORE. 160k = 2.50V VCORE. COILCRAFT 5 DO3316P-332 L1 6 3.3 H 2 5.4A IRMS 1 + 1 3 Q1 FAIRCHILD 2 FDC638P D1 ONMBRS 320T3 VCORE 1% R1 37.4k 0805 C3 220 F 6.3V R4 75k 0805 0.1%

KELVIN SENSING

Figure 1
1 2 3 4 7 11 5 6 8 SENSE 1 SENSE 1+ VIN ITH/RUN VFB1 IC1 PGATE1 SGND LTC3701EGN PLLLPF PGND PGOOD PGATE2 VFB2 ITH/RUN2 EXTCLK/MODE SENSE 2 SENSE 2+ 16 15 14

5V VIN

C1 580 pF 0603

VCORE VIN 5V R3 10k 8 7 65 C5 580 pF R5 0603 10k PACK4 3 C2 47 pF 0603

R2 0.015

C6 0603 47 pF R6 10k

13 12 10 9

C4 22 F 10V 1210

1 2 34 SLEEP SLEEP 1 Q3 2 BSN20

5V VIN C8 580 pF 0603 KELVIN SENSING 4 R7 0.015 C9 22 F 10V 1210 Q2 FAIRCHILD FDC638P L2 1 2 6 5 1 2.2 H 2.3A IRMS COILCRAFT DO1608C-222 + C10 220 F 6.3V 3.3V 1% R8 232k 0805 0.1% R10 75k 0805

C7 580 pF 0603

3 R9 33k Q4 2N3904- 1 SMD 2

Q5 BSN20

D2 ONMBRS130T3

Adding a few transistors to a switching regulator adds power-sequencing and shutdown control to a power supply. www.edn.com October 30, 2003 | edn 89

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IS STOPPED devices that control the voltage ACQUISITION voltage above approxi100k SAMPLES/SEC on the regulators ITH/Run pins. mately 1V. You may need The ITH/Run pins of IC1 proto adjust the value of R9 if vide an external compensation your design requires core to the internal feedback loops; voltages below approxithey can also serve to shut mately 1V.You can replace down the device when you pull Q3 and Q5 by potentially cheaper industry-stanthem to ground. A microdard 2N2007 devices at processors TTL/CMOS-comthe expense of slightly patible input signal (Sleep) higher capacitive loading controls the power state of the on the ITH/Run pins of circuit. You can put the circuit IC1. C2 and C6 are cominto shutdown mode by either pensation capacitors that letting the Sleep pin float high the Linear Technology litor pulling it higher than ap1 500 mV/DIV 1.49V Y X 3 1V/DIV 75 mV 1 (1)=800 mV 349.96 SEC erature does not mention proximately 1.5V. Q3 then con2 (3)=5.880V 3.88004 mSEC nects the ITH/Run1 pin to but that are highly effec=6.680V 4.23000 mSEC Figure 2 1/X= 236.406 Hz ground, which causes the tive in preventing subharVCORE core-voltage supply to The 3.3V supply turns on several milliseconds after VCORE attains an estabmonic oscillation arising shut off. The VCORE voltage then lished level. from dynamic current drops toward ground, and Q4 loading on the outputs. stops conducting when VCORE falls below proximately 0.8V. This action turns off Q5 (See the Linear Technology Web site for approximately 0.8V. The gate of Q5 pulls and allows the ITH/Run2 pin voltage to information on subharmonic oscillato the 5V unregulated input voltage, and start rising. The 3.3V power supply thus tion.) Q5 shorts the ITH/Run2 pin to ground, turns on. The combined effect of driving The gate-drain-source capacitance of which turns off the 3.3V regulator. The Q4 and Q5 from the VCORE voltage is that Q3 and Q5 also add to the stability of the circuit is now in standby mode, and both the 3.3V I/O voltage always turns on only loop filter. Note that sequencing the turnafter the VCORE voltage attains an estab- on ramps of the power supplies also has power supplies are off. Pulling the Sleep pin lower than ap- lished level. The end result is to sequence the benefit of reducing the inrush current proximately 0.8V turns on the power the power supplies over a period of 4 into the power supply by staggering this current and preventing simultaneous supply and sequences the voltages in the msec (Figure 2). The circuit is symmetric, and changing current loading of the primary bypass cafollowing manner: Q3 stops conducting, and the voltage on the ITH/Run1 pin can the base drive of Q4 and interchanging pacitors by both power supplies. The serise, thanks to internal current sources in the drain signals of Q3 and Q5 reverses the lected component values allow for more IC1. The VCORE voltage regulator then sequencing order of the power supplies than 2A of current on the 3.3V line and starts to operate, and VCORE rises to its set for chips that require the I/O voltage to more than 3.5A of current on the VCORE voltage, 1.2V by default. Q4 starts con- rise before the core voltage. You can ad- line. ducting as soon as VCORE rises above ap- just the value of R1 to generate any core

MathCAD functions perform log interpolation

James Bach, Delphi Delco Electronics Systems, Kokomo, IN

athCAD provides a number of interpolation and curve-fitting functions, so that, given a set of XY data points, you can estimate the Y value for any given X coordinate. Unfortunately, these functions work poorly with data that is to be displayed in a nonlinear (logarithmic) manner. Examples of these functions are: Log-Lin: phase/magnitude-versusfrequency (Bode plots); Log-Log: impedance-versus-frequency (reactance plots); and Lin-Log: impedance-versus-tem-

Figure 1

At X coordinates between data points, MathCADs linterp function creates a bulging effect. (continued on pg 94) www.edn.com

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perature (thermistor data). Using the built-in linterp function, MathCAD estimates and plots the data (Figure 1). As you can see, at X coordinates between the original data points, the linterp function creates a bulging effect. The following trio of simple interpolation functions allows the correct interpolation of nonlinear data on its appropriate scale. These routines function by prewarping the incoming-data matrices before feeding them into the existing linterp function; for logarithmic Y-axis functions, you raise 10 to the result of the linterp function to restore the values to the proper decade:

Figure 2

Using the LogLogInterp function, the bulges in Figure 1 disappear.

Using the newly created LogLogInterp function, the straight-line data is displayed (Figure 2).

Scheme improves on low-cost keyboard

Martin OHara, Telematica Systems Ltd, Cranfield, Bedfordshire, UK
ou can easily imRC prove on a previous MICROCONTROLLER 100 Design Idea to proS1 S2 S3 S4 S5 SX duce a slightly simpler reC1 R R R R R 2 3 4 5 X sistor arrangement with 47 nF better timing balance be1k 1k 1k 1k 1k R1 tween switches, using a 1k Figure 1 single resistor value (Reference 1, Figure 1). The use of a single resistor value, RS, in a series chain This simple keypad arrangement uses a single resistor value to select the switches. for the switch resistors gives the timing parameters a simpler rials cost. The timing balance between an SMD assembly with just two compoformat and should reduce bill-of-mate- switches should now also be more even. nent types: switch and resistor. In the The improved balance eases original idea, in cases of multiple keys extending the keyboard for being pressed, the timing is some odd adding key inputs. The addi- multiple of parallel resistors and could tional benefit of this arrange- accidentally represent a key that was not ment is to make the circuit eas- selected. With the arrangement of Figier to adapt for faster or slower ure 1, the lowest order key dominates; microprocessors, because you hence, the keypad has hard-wired prican easily adapt the circuit by ority setting and always results in a sechanging the single switch re- lected key timing, and no intermediate sistor or capacitor values to al- timing period should occur. ter the charge-discharge characteristics (Figure 2). It can Reference 1. Thevenin, Jean-Jacques,Novel idea also make building the circuit into a keypad housing easier, implements low-cost keyboard, EDN, A 400-kHz square wave from the Figure 2 especially if you use mem- April 3, 2003, pg 69. microprocessor shows no key, key 1, brane keys. The entire circuit is and key 5 pressed.

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ADC interface conditions high-level signals

Moshe Gerstenhaber and Stephen Lee, Analog Devices, Wilmington, MA
esigners who build 5V equipment for the industrial market VS 7 share a widespread probR3 AD628 10k lem. At one extreme, R4 they must build equip100k IN _ VB V1 8 ment that supports 10k R2 A1 + 10V bipolar voltages, 100k OUT +IN + A2 5V 1 5 often riding on a high _ R1 AD628 common-mode level, a 10k requirement enforced by 3 2 4 6 RG VREF VS CFILT 3.32k 30 years of legacy industrial equipment. At the VR C AD7540 13.3k 3.32k other extreme, the anaC FILT RG VS VREF log signal needs condi5V 3 2 4 6 REFERENCE tioning to match the fullR R2 1 AD628 _ 2.5V scale range of a lowAD780 100k 10k +IN A2 + 5 VR 1 voltage, single-supply 10k OUT R4 A1 + ADC. Designers need to 100k -IN _ VA 8 PRECISION scale and level-shift sigV2 REFERENCE nal levels throughout R3 AD628 their system to 10k F i g u r e 1 7 accommodate VS the high voltage levels 5V that sensor manufacturers dictate and the low This circuit attenuates and level-shifts a 10V differential signal while operating from a single 5V supply. voltage levels that the 2 shows a 10V input signal ADC dictates. Operating from a 50k SAMPLES/SEC HI RES (top), the signals at the outsingle 5V supply, the circuit in put of each AD628 (midthis Design Idea provides an indle), and the differential terface of large bipolar inputs to output (bottom). The bena single-supply, low-voltage, difefits of this configuration go ferential-input ADC. The circuit beyond simply interfacing in Figure 1 comprises two difwith the ADC. The circuit ference amplifiers, connected in improves specifications such antiphase. The differential outas common-mode-rejection put, V1V2, is an attenuated version of the input signal: ratio, offset voltage, drift, V1V2(VAVB)/5. and noise by a factor of 2 The difference amplibecause the errors of each Figure 2 fiers reject the commonAD628 are not correlated. mode voltage on inputs VA and The output demonstrates VB. The reference voltage, VR, 85-dB SNR (Figure 3). The which the AD780 develops and two AD628s interface with 10.0V CH3 2.00V M1 mSEC CH1 2.4V the ADC and the amplifier an AD7450 12-bit, differen2V 2V 1.00 mSEC share, sets the output commontial-input ADC. The ADmode voltage. A single capaci- The waveforms show a 10V input signal (top), the signals at the output 7450 easily rejects residual tor, C, placed arcros the CFILT of each AD628 (middle), and the differential output (bottom). common-mode signals at pins, lowpass-filters the differthe output of the difference ence signal, V1V2. The 3-dB pole fre- plifies the difference signal by 1.5. Thus, amplifiers. Figure 4 shows the commonquency is: fP1/(40,000C). A2 am- the total gain of this circuit is 3/10. Figure mode error at the output of the AD628.

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common-mode error measured, differentially, from the output of the two AD628s. The bottom waveform, measuring 80 V, is the resultant commonmode error.

The topmost waveform is a 10V, common-mode input signal. The middle waveform, measuring 150 V, is the

INPUT 20V p-p

COMMON-MODE ERROR OF DIFFERENTIAL OUTPUT

Figure 3 Figure 4

COMMON-MODE ERROR OF COMMON-MODE OUTPUT

The circuit in Figure 1 has an 85-dBV SNR.

The common mode input (top) measures 20V p-p. The common-mode error of the differential output (middle) is 200 V p-p. The error of the common-mode output (bottom) is 80 V p-p.

Two op amps provide averaged absolute value

Dobromir Dobrev, Jet Electronics, Sofia, Bulgaria
he circuit in Figure 1 is useful C2 C1 when you need amplitude demodu470 nF 47 nF lation or an averaged absolute-valVA ue conversion. The circuit comprises two R2 R3 R4 22k 220k 220k stages, the first of which, IC1A, is a differential-output absolute-value convertR1 er. The second stage, IC1B, is a tradition20k _ _ al differential amplifier. The VIN IC1A IC1B D 1 VOUT combination of the two stages performs TL082 TL082 BAV99 + + single-ended absolute-value conversion but only if R3R2. The C1 capacitors integrate the current flow and yield avR2 R3 R4 22k 220k 220k eraged voltages VA and VB. In addition, the capacitors ensure low ac-impedance points at nodes VA and VB when the outVB put diodes are reverse-biased. C2 C1 F i g u r e 1 The additional C2 capacitors in 470 nF 47 nF parallel with R4 resistors impart a second-order-lowpass-filter characteristic This single-ended, averaged absolute-value converter is useful for amplitude demodulation. to the circuit and remove the remaining ac signal. From a practical point of view, stants 1R2||R3C1 and 2R4C2 to be tages are that the circuit has equal delay you can choose R3 to be five to 10 times equal. The circuit in Figure 1 is simple, for positive- and negative-going signals higher than R2. The gain of the circuit is symmetrical, and cost-effective. It also and that it doesnt need matched (R2||R3/R1)(R4/R3). In most applications, makes it easy to calculate and adjust the diodes. you would choose the filter time con- gain using one resistor, R1. Other advan-

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