Highly Efficient and Compact DC-DC Converter for Ultra-Fast Charging of Electric Vehicles

D. Christen, S. Tschannen, J. Biela Laboratory for High Power Electronic Systems ETH Zurich, Physikstrasse 3, CH-8092 Zurich, Switzerland Email: christen@hpe.ee.ethz.ch

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15th International Power Electronics and Motion Control Conference, EPE-PEMC 2012 ECCE Europe, Novi Sad, Serbia

Highly Efcient and Compact DC-DC Converter for Ultra-Fast Charging of Electric Vehicles
D. Christen, S. Tschannen, J. Biela
Laboratory for High Power Electronic Systems ETH Zurich, Physikstrasse 3, CH-8092 Zurich, Switzerland Email: christen@hpe.ee.ethz.ch
AbstractThe range of electric vehicles is still limited due to long charging times. With fast charging stations that enable to recharge a vehicle battery in a few minutes, the range limitation can be overcome in principle. For such fast charging stations, compact and efcient DC-DC converters with a high output power are required. Therefore, a multi-phase half-bridge DC-DC converter, which is part of an ultra fast charging station capable of charging a vehicle battery in less than 5 min, is presented in this paper. The ultra fast charging station utilises an intermediate storage battery, in order to avoid power pulsations at the grid and to provide additional functionality as e.g. energy storage for renewables. By splitting the intermediate storage battery, the voltage ratings of the semiconductor devices used in the high power DC-DC converter can be reduced, which increases the system efciency. For further increasing the efciency, a triangular current modulation (TCM) scheme is applied, which allows zero voltage switching (ZVS) for all semiconductor devices. To achieve a high power density as well as to implement ripple cancelation on the output current, several power electronic modules are parallel interleaved. A detailed analysis of the proposed system and simulation results are provided in this paper. Based on the above mentioned means the DC-DC converter achieves a system efciency above 99.5% over a wide operating range.
Low Voltage DC-Bus VDC = variable Low Voltage AC Grid VN,ll = 400V DC VPV DC Bidirectional isolated Input Stage AC AC DC DC DC

PVArray

Electrochemical
DC

DC High Power DC-DC Converter DC

DC

DC

Battery
DC AC

Electric Motor

Electric Vehicle

Fig. 1. Charging station concept with an AC-DC input stage, a variable DCbus, intermediate battery storage and high power DC-DC converter (shown in red).

I. I NTRODUCTION During the last years the interest in electric vehicles (EVs) grew strongly due to ecological aspects. However, the long charging times, which usually exceed 30 minutes for a full charge, as well as the range limitation of EVs due to the available battery technologies, are still challenging problems. In order to overcome the charging and the range limitation problem, the company Better Place [1] is proposing to quickly exchange the vehicle battery in exchange stations. This requires to design all electric vehicles in a similar manner, so that the battery could be automatically exchanged.Also in all vehicles the same or only a very limited number of different battery types can be installed in order to limit the number of batteries, that must be on hand in the exchange stations. Furthermore, to avoid an accumulation of batteries, a system for distributing the batteries between the exchange stations is necessary. In total more batteries are necessary since besides the batteries in the vehicles also batteries in the exchange stations, which are recharged during the vehicle batteries are used for driving, are necessary. Another option to overcome the charging and range limitation, are ultra fast charging stations, which allow to rell the batteries within a few minutes [2]. With this concept, the vehicle battery is designed only for a limited range of 150200km, so that the volume and weight of the battery could be reduced and the driving range is extended by the short recharging process. Battery technologies based on lithiumtitanate enable an ultra fast charging of up to 10C-12C as well as high cycle numbers in the range of several thousand
TABLE I S PECIFICATIONS OF THE INVESTIGATED U LTRA FAST C HARGING S TATION FOR ELECTRIC VEHICLES [2]. Grid AC/DC Input Stage 3 400Vrms Bidirectional Isolated Low power ( 22kW) Directly connected DC-bus Variable DC-voltage Discharge current 3C-4C Energy-capacitance 25 kWh Unidirectional Non-isolated High power ( 220kW)

Intermediate Battery Storage

High Power DC-DC

978-1-4673-1972-0/12/$31.00 2012 IEEE

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[3]. In order to achieve such a short charging time, charger concepts with a high output power are required. For example, for vehicle batteries with an energy content of 20kWh, a charger with an output power higher than 200kW is required in order to achieve charging times signicantly below 10 minutes. With this high output power, such chargers fall into category Level III, which denes charging systems up to 240kW peak power and which completes the low power Level I and II charging systems with a maximum power level of 14.4kW [4], [5] that are well suited for on-board and overnight charging. In the literature, many concepts with a constant DC-bus are described [4][7]. However, due to efciency considerations of the complete charging system, a concept with a variable DCbus and fewer power electronic converters is investigated in the project as described in [2] and shown in Fig. 1 & Table I. The shown system consists of a bidirectional isolated AC-DC input stage, which allows to charge the stationary storage system as well as to feed back energy to the grid, and a unidirectional high power DC-DC converter system for ultra-fast charging of EVs. With the intermediate battery storage system, the energy necessary for the ultra-fast charging is provided, so that power pulsations of the grid are avoided. Furthermore, the intermediate storage battery can be used in the context of smart grid applications (e.g. power shaping) as well as to connect and buffer energy gained for example by PV elements. Due to the higher energy capacity of the intermediate storage battery compared to the vehicle battery, also the ultrafast charging process of the vehicle battery does not exceed a maximum discharge current of 3C- 4C per cell of the intermediate storage battery. In this way, a long life time of the stationary battery could be achieved. The AC-DC input stage of the considered charging station consists of two converters, a T-type inverter and a DC-DC converter system, which provides isolation and can be used to balance the voltages of the stationary battery. In this paper, the focus is on the high power DC-DC converter (highlighted in red in Fig. 1) enabling ultra-fast charging of EVs. With this DC-DC converter the charging time of batteries with an energy capacity in the range of 16kWh [8] could be reduced to 5 minutes. Typically, the battery voltage of lithium ion cells varies strongly with respect to the State of Charge (SoC). However, the voltage prole in the range of 10% up to 90% SoC, where quick charging is performed, is relatively at [9]. The carbattery voltage taken for the following considerations is in the range of 240 V up to 420 V with a nominal voltage of 330V according to the battery pack voltage of the iMiEV [8] or the iON [10]. During charging the maximum output voltage ripple is limited to 5% of its nominal value, which avoids inuence of the ripple current on the battery life time [11]. Further specications for the converter topology are listed in Table II. To fulll the specications mentioned above and simultaneously achieve a high efciency and a high power density, in

this paper a multi-phase interleaved half-bridge converter with a split input voltage, which is operated in TCM is presented. The derivation of the analytical models of voltage and current of the proposed half-bridge converter are presented in Section II. In Section III the implemented control algorithms are explained. Section IV discusses the loss analysis and the efciency of the converter system. Additionally, a comparison of the proposed system to a standard buck-type solution is given. II. C ONVERTER T OPOLOGY High-power charging is a challenging task due to high currents of several hundred amperes as well as a wide output voltage range. In order to simultaneously achieve a high efciency and a high power density, non-isolated DC-DC converters are the most suitable topologies, since the isolation to the grid is realised in the AC-DC stage (see Fig.1). In [12], several bidirectional non-isolated converters are compared, including cascaded buck-boost, half bridge, Cuk and SEPIC converters. Due to the low number and size of the passive components and the low conduction losses in the semiconductor devices, the half-bridge converter achieves the highest efciency of the evaluated topologies. To reduce the size of the passive components [11], [13] [15] propose multi-phase converter systems. By interleaving the phase currents of the different modules, a smooth output current can be achieved. The total volume of the inductors is reduced by a factor of 1/N and due to the small ripple of the output current the size of the input and output lter is minimised as well. Furthermore, a modular multi-phase converter system has also the advantage of achieving high efciencies under part load conditions by adapting the number of active phases (also called power shedding). The efciency can further be increased by reducing the required blocking voltage of the semiconductor devices. There are several strategies to reduce the voltage stresses of the semiconductor devices. Different kinds of three level converters like the neutral point clamped and the ying capacitor converter are presented in [16][18]. In [19] a novel strategy by introducing a splitting of the input voltages as for example shown in gure 2 is proposed. The reduced operating voltage enables to use MOSFETs with a lower blocking voltage. This results in a reduction of the conduction and switching losses, so that the power density could be increased.
TABLE II S PECIFICATION FOR THE H IGH -P OWER DC-DC C ONVERTER Nominal car battery voltage Output voltage range Nominal output power DC-bus voltage Split DC-Voltage Output voltage ripple Vbat,nom Pout v1 v1b vout 330 V 240 V ... 420 V 220 kW 420 V 230 V 5%

LS5d.3-2

v1a v1

+ + + -

LF,1 CF,1

S1

Lout CF,2
+ -

v1-vBat
vbat

S2

v1b-vBat Iout Imax

V

vL,i

v1b
a)

+ -

iL,i

v1,min
Discharging Charging

v1 vbat
Vehicle Battery Operating Area

Iout n I0 Ir,min t
t0 t1 t2 t3 t4 t5 t6

v1b,max

v1b
b) 10% 90% SoC

Fig. 3. Current and voltage waveforms of the 3-phase interleaved half-bridge converter.

Fig. 2. a) Multi-phase interleaved half-bridge converter with a split input voltage in order to reduce the required blocking voltage of the MOSFETs. b) Ranges of the vehicle and the intermediate storage battery required for the operation of the DC-DC converter with split voltages.

Combining the different strategies results in the proposed multi-phase interleaved half-bridge converter as presented in Fig. 2a). In the following, the main operating principle is explained. A. Multi-phase interleaved half-bridge converter Compared to the standard buck topology, the blocking voltage of the switches of the converter system shown in Fig.2 could be reduced due to the split voltage, and only depends on the output voltage range. To guarantee full controllability of the converter structure, the battery voltage vbat always has to be in a dened operating range, whose upper and lower limits are dened by the input voltages v1 and v1b (cf. Fig. 2b). The maximum tapped voltage v1b,max is restricted to be smaller than the minimum battery voltage vbat,min . In addition, the input voltage v1 always has to be higher than vbat,max . In the considered application, the duty cycle ratio of the buck converter topology is xed by the battery voltages with vbat v1b . (1) v1a As already mentioned, a TCM operating scheme as described in [20] is applied to achieve ZVS for the semiconductor devices. During the switching periods (t1 ... t2 & t4 ...t5 ) the resonant network, consisting of the parasitic switch capacitances CDS,i and the output inductor Lout,i , enables a nearly lossless charging/discharging of the capacitors. The current and voltage transitions during one period as shown in Fig.3 are explained in the following. D=

At t0 switch S1 is conducting, while S2 is in the blocking state. Hence, the voltage across inductor Lout is positive and current iL is increasing. At t1 switch S1 is turned off. A resonant oscillation between the output inductor Lout,i and the parasitic capacitances CDS,i starts. When the voltage across S2 becomes zero and its body diode starts conducting S2 can be turned at zero voltage (ZVS) at t2 . Now a negative voltage is applied across the output inductor and iL decreases. Since the absolute value of the inductor current has to exceed a certain limit, S2 remains turned on until this limit is reached at t4 . At t4 switch S2 is turned off and analogous to [t1 ... t2 ] an oscillation starts. At t5 the voltage across S1 becomes zero and therefore, S1 can be turned on at zero voltage. To ensure ZVS during the switching transitions a minimum current amplitude is required for the resonant oscillations. Therefore, at t3 the current has to reverse its direction. The required current Ir,min can be determined with equation 2 and depends on the blocking voltage v1a . The charge Qc required for ZVS of the MOSFETs can be determined by integrating their nonlinear parasitic capacitance (Coss ). Ir,min = 2 Qc (2vbat v1a ) Lout (2)

Since in all operating points soft switching should be achieved, the output current only can be controlled by adapting the switching frequency. Assuming a triangular current waveform, the switching frequency for a certain output current of a single module can be determined by equation 3 with Iout,i and Lout,i as output current and inductance of one module. The inversely proportional relation between output power and

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frequency is obvious. fS = Pout 1 v1 vbat D Lout,i 2 (Iout,i + Ir,min ) (3) (4)

(Lm>LS)

iL,m

iL,S
Im,avg=Is,avg t

D N = (v1 vbat ) vbat 2 fs Lout,i

Applying the TCM to a single module causes a large output current ripple. By interleaving the modules in parallel and applying a dened phase shift, the current ripple of the output current is signicantly reduced. Due to the ripple reduction and the higher effective frequency, the volume of passive components of the lter stages can be reduced. Figure 4 shows the minimal achievable relative output current ripple for an ideal interleaving of N modules, depending on the duty cycle D. By interleaving 11 modules for a duty cycle between 0.1 and 0.9 a current ripple below 2% relative to the nominal output current of the converter system can be achieved. III. C ONTROL S TRATEGY AND S IMULATION R ESULTS For controlling the output power/voltage of the converter in TCM operation, two degrees of freedom can be used: the switching frequency fS and the duty cycle D. For the different modules a master-slave relationship is implemented as proposed in [21]. The switching frequency fS and the duty cycle D are determined online by the master module. To achieve a proper interleaving of the modules and avoid subharmonic oscillations, fS has to be the same for all modules so that only D remains as control parameter. In the following two possible control strategies are explained. In a rst approach, the output current of each module is controlled so that all modules have the same average current. The different modules are internally duty cycle controlled over T . Since the steady state value of D is xed by the input and output voltage, by increasing the duty cycle, the average current will increase and vice versa (see Fig. 5). The

a)

 7

iL(D1>D) iL iL(D2<D) b)
Fig. 5. Current control for the interleaved buck-converter with synchronization via the turn-on instant. Figure a) describes the synchronization of a master and a slave module on the on-instant, whereas LM > LS . In b) the inuence of the duty-cycle variation on the average current is depicted.

0.7
Relative Current Ripple

0.6 0.5 0.4 0.3 0.2

N=3

N=4

0.1 N=6 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Duty Cycle

Fig. 4. Dependency of the output current ripple, relative to the current ripple of one module, on the duty cycle and the number of phases (N ) for the buck converter operated with a TCM modulation scheme. (For resons of simplicity only the cases N =2, 4 and 6 are shown).

synchronisation is on the turn-on instant of the master module as described in [21]. The slave modules are turned-on with a pre-controlled phase shift . To prevent hard switching of the slaves, it has to be ensured that the master has the highest inductance, respectively carries the lowest current ripple. The reason is that in all modules the average current is controlled to the same value and fS is dictated by the master, so that slave modules with a lower ripple current/higher inductance value than the master module would not be able to reverse the inductor current to Ir,min . Hence the soft-switching at t4 would be lost in such a module. The value of the inductances, which is required for choosing a master module, can be determined by measurements in advance, or by a initial parameter identication during start-up phase. By changing the switching frequency, the average current of the single modules as well as the average current of the converter system can be adjusted. The main drawbacks of this control-strategy are the high number of current sensors to control the average current of the modules as well as the necessity of knowledge about the inductance values of all the modules for selecting an appropriate master module. Therefore, a second control strategy is investigated, where only the master module current is controlled. The master module determines the duty-cycle which is used as pre-control value for the slave modules. The current in the slave modules is only indirectly controlled. In each module, it is detected, when the current decreases below the required current limit Ir,min for ZVS. When this happens, a detection pulse raises

LS5d.3-4

to high. To determine the phase-shift between the master and the slave modules, the time between this detection pulses is measured. The phase-shift is adapted by controlling the dutycycle (see Fig. 6). To realise this control strategy only the current limit detection has to be implemented for the slave modules and zero current switching is achieved independently of the inductance values of the modules. However, homogenous current sharing between the modules is lost. For validating also the two control strategies and for evaluating the performance, a simulation of the 11 modules with slightly different inductance values (tolerance 10%) is set up in Gecko Circuits [22]. The results for the two control strategies are shown in Fig. 7 and in Fig. 8 where 11 modules are interleaved for an average total output current of 660 A1 . There, it could be seen that the relative ripple amplitude could be kept below 2% in both cases. The ripple at the switching frequency has an amplitude in the range of 3A and the peakto-peak amplitude of the current is approximately 20A. However, non-idealities like tolerances in the inductance values or delays in switching times result in a higher output current ripple than for an ideal system, so that lters at the input and output are required, which also reduce the higher harmonics of the current. There are different strategies proposed in literature [13], [23] to reduce the current ripple of N interleaved phases, where for an even number of modules
1 The used values for the inductances are: L = 7.13H , L = 6.86H , 1 2 L3 = 6.20H , L4 = 6.45H , L5 = 6.93H , L6 = 6.66H , L7 = 6.79H , L8 = 6.50H , L9 = 7.07H , L10 = 6.11H , L11 = 7.13H

iL1 iL2 iL3 iL4 iL5 iL6 iL7 iL8 iL9 iL10 iL11

Current [A]

120 80 40 0 -40 680

iLi,avg

a)

Current [A]

675 670 665 660

iout

b) 655
700 600 500 400 300 200 100 0
iout

c)

Fig. 7. Simulation results for control method 1, where each module current is controlled to the same average value. Since the average current is kept constant, the minimal current varies due to different inductance values.

in a rst step N 2 phases are sorted such that two phases of similar amplitude are shifted by 180 . After the rst step for the (N 2) phases, a resultant vector remains. The angles of the remaining two vectors and the resulting vector are adjusted so, that the resulting vector is minimal. In case of an uneven number of modules, the same procedure is adapted, but in the last step four instead of three vectors are used to minimise the ripple vector. There, the additional degree of freedom could be used to minimise not only the fundamental ripple harmonics but also higher order harmonics. IV. L OSS A NALYSIS AND P ROTOTYPE S YSTEM In the following, the design of a prototype system of the considered DC-DC converter is presented and the loss distribution is analysed for nominal voltages at the input and the output. The design process is based on the assumption,
iL1 iL2 iL3 iL4 iL5 iL6 iL7 iL8 iL9 iL10 iL11

(Lm>LS)

iL,m
Is,avg Im,avg Ir,min N

iL,S

Current [A]

Current [A]

t DTP t

120 80 40 0

i L3,avg i L8,avg iLi,avg

i=1,2,4, 5,6,7, 9,10,11

a)

a) -40
680

Current [A]

675 670 665 660 iout

iL,S iL,m
t Ir,min

b) 655
700 i 600 500 400 300 200 100 0 out

b)

s/2

c)

Fig. 6. Current control for the interleaved buck-converter with indirect current control. Figure a) describes the synchronization of a master and a slave module via the on-instant (Note: LM > LS ). The average current of the slave module is slightly increased, due to the increased inductance LS . In b) the control strategy to adjust the phase is described. By increasing the duty cycle, fS of the slave is decreased and the according phase-shift increases.

Fig. 8. Simulation results for the second control strategy, which uses the master module for determining the duty-cycle and in the slave modules the current is controlled so that it always stops at Ir,min in reverse direction. With this control strategy ZVS operation is guaranteed for all submodules, but the average current values of the modules slightly differ in case of not equal inductance values. However, the slave modules do not require a current measurement, but only a peak detection.

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Current [A]

TABLE III C ONVERTER L OSSES FOR THE N OMINAL O PERATING P OINT Converter System Number of modules Output Power Maximum output current Total power losses Estimated efciency Inductor (per mod.) Copper losses Core losses Semiconductor (per mod.) Conduction losses Switching losses Input lter (total) Output capacitor (total) Aux. & Ctrl. (per mod.) Aux. & Ctrl. (common)

k1 =
N Pout Iout,max Pv,tot PLCu PL,core PF ET,cond PF ET,s Pf ilt Pcout Paux,m Paux,t 11 220 kW 660 A 891 W 99.59% 8.2 W 3.7 W 43.8 W 13.2 W 14.3 W 0.1 W 9W 20 W

Ir,min IS 1,pp

(7)

Besides the heat sink for the semiconductors, the output inductor is one of the largest components of the converter system. The inductor losses can be divided in the core losses and the copper losses. The core losses are determined with the improved generalized Steinmetz equation (iGSE) presented in [28]. For the realisation of the windings, litz wire is used, so that the increase of the AC resistance due to the proximity and the skin-effect [29] is limited. For the core of the 6.8 H output inductor ve stacked E-cores with four turns are used (E40/16/12, N87, [25]). The input lter is realised as a damped L-C-lter according
Auxillary & Control v1 Copper Power Planes Low Power Fan 2XWSXW ,QGXFWRU + 5 x E40/16/12 EPCOS 50 mm MOSFET (2 parallel) STY139N65M5 157 mm +HDW VLQN 40 mm

that the converter system must t in a relatively at 23inch rack and up to two height units can be consumed by the high power DC-DC converter. To determine the efciency of the overall converter system, rst the losses occurring in a single module are calculated. The single module basically consists of a half-bridge and the output inductor. The input- and output-lters are shared by all interleaved modules. Therefore, in the calculations, the losses of the lters are distributed on the number of active submodules, which depends on the output power (cf. Fig. 10). The losses in the half-bridge are mainly caused by the conduction losses of the semiconductors and the gate-drive losses. Due to the reverse current Ir,min required for achieving ZVS (2), the conduction losses are increased. This has especially at low output power levels and in case of a large number of paralleled MOSFETs a signicant impact on the achievable efciency. The rms currents for the upper and the lower switch can be calculated by equations (5)-(7). The gate-drive losses are estimated with the gate-source voltage and the required gate charge. In addition to the conduction losses, relatively low switching losses are generated in the MOSFETs operating under zero voltage conditions, which are determined based on measurement results. In the prototype system shown in Fig. 9 two STY139N65M5 MOSFETs [24] are paralleled.
2 2

v1b

Shared Input Filter vbat v1 v1b 54 mm

335 mm Converter Modules

475 mm Output Capacitors

Fig. 9. 3D CAD implementation of a single module of the high power DCDC converter. Top, a single converter module consisting of the half-bridge and the output inductor is shown. At the bottom, the overall converter system with its dimensions is depicted. TABLE IV L IST OF COMPONENTS OF THE PROTOTYPE SYSTEM Switching devices Inductor core Filter inductor core Input lter capacitor Output lter capacitor 2 parallel 6.8 H 1 55 H 11 11 110 F 100 1 F STY139N65M5 E40/16/12 [25] AMCC-4 [26] B32778G411K [25] CGA9P4X7T2W105K [27]

IS 1,rms=

Ir,min

Dk1 3

+ IS 1,max

D(1k1 ) 3

(5)

IS 2,rms=

Ir,min

(1D)k1 + IS 2,max 3

(1D)(1k1 ) 3 (6)

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100.0 99. 9 99. 8 Maximum Efficiency with optimal number of Modules &RQYHUWHU HIILFLHQF\ IRU  0RGXOHV

(IILFLHQF\ > @

99. 7 99. 6 99. 5

N=11 N=3 N=6

99. 4 99. 3 99. 2 99. 1 99.0 0 50 100 N=1

150

200

250

Pout [kW]

Fig. 10. Efciency of the overall converter system as function of the output power. Due to the different number of active phases a high efciency over a wide operating range is achieved.

to [30]. At the output, only a lter capacitor is required as the current ripple is relatively small due to the interleaving of the converter modules. The losses for the lter inductor are calculated with the same procedure as the losses of the output inductor. To determine the losses in the lter capacitors the ESR of the capacitors and the rms current are used. The conduction losses of the wiring between the modules and the connection to the vehicle as well as to the storage battery are neglected in a rst step. The losses for the nominal operating point of the planed prototype system shown in Fig.9 at Pout =20 kW and fS =45 kHz are summarised in Tab.III. The overall converter system has a volume of about 8.6 lit . The switching frequency varies between 40 kHz at full load and 150 kHz at light load to adjust the output current. The achievable efciency for the different numbers of active phases against the output power is plotted in Fig.10. A maximum efciency over 99.6% can be achieved at an output power of 150 kW. If the system is compared to a standard buck topology (see Fig.11), as for example presented in [13], [14], it is obvious that the required blocking voltage of the semiconductors must

be increased so that also the on resistance of the MOSFETs increases. In the following a comparison concerning the switching and inductor losses of these two solutions is performed. There, the inuence on the input and output lter structures is neglected. The comparison is performed for one module at an output power of 20 kW and a switching frequency of 45 kHz. For both topologies, the same modulation scheme for soft switching is applied. In the described prototype system 650 V MOSFETs are used for the calculation, since these have the lowest onresistance per TO247 housing for this application available on the market. But due to the splitting of the input voltage, 400 V MOSFETs would meet the requirements. According to [31], the on-resistance of a MOSFET approximately scales with the breakdown voltage (VBD ) to the power of 1.3. Therefore, the on resistance of the MOSFETs, and also the conduction losses, scale with a factor of approximately 2.2. In addition, the switching losses as well as the current ripple are increased with the standard buck converter due to the higher switched voltages. At the considered operating point, the inductance value for the buck converter without splitting has to be increased to Lout,buck = 11.2H . To compare the performance of the two inductances, an optimal design is calculated, whereas the average energy density of the inductors is kept constant. The chosen material is N87 ferrite and the windings are realised in both cases with litz wire (strand diameter dstrand =0.1 mm). For the proposed system the optimised inductor losses are 10.0 W at a volume of 0.1 dm3 , while for the standard system losses of 14.5 W occur at a volume of 16.5 dm3 . For the optimised design, the proposed system dissipates in total 608.2 W losses at the nominal operating point (Pout =220 kW). This is about half the losses of the standard solution with 1163.5 W. In both cases the losses in the lters are assumed to be identical. In addition to the lower losses, the proposed system enables a signicant reduction of the inductor and the heat sink volume. V. C ONCLUSION In this paper, a concept for high power DC-DC converters suitable for ultra-fast charging stations for electric vehicles is presented. The converter is based on a split DC input voltage and utilises a boundary operation mode to achieve soft switching as well as interleaving for reduction of the output current ripple. Besides the operating principle and the control of the interleaving, also the design of a prototype system is discussed. For the prototype system a system efciency above 99.5% can be achieved over a wide operating range and the relative current ripple amplitude at the output is below 2%. Compared to a standard buck-converter, which has to switch the full DC-link voltage, the losses can be reduced by more than 40% if optimised MOSFETs are used for the presented concept.

LF,1 v1
+ + Sw1

Lout CF,2 +

CF,1
Sw2

vBat, Car

Fig. 11. Standard buck topology (e.g. [14]) used for comparison of the proposed DC-DC converter.

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ACKNOWLEDGMENT The authors would like to thank Swisselectric Research and the Competence Center Energy and Mobility (CCEM) very much for their strong nancial support of the research work. R EFERENCES
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