LNA Design with the MGA-17516 Matched Pair, Low Noise Amplifier

Application Note 5442

Introduction
Most base stations (BTS) can transmit a signal to a mobile device further and stronger than they can receive the signals coming back from it. This is known as link imbalance and is made worse by the feeder loss between the base station and the antennas.[1] The low noise amplifier (LNA) in a communications system is the first level of amplification of the incoming signal at the system antennas. Lo noise amplifies are found in almost all RF and microwave receivers in commercial and military applications. In commercial applications, LNA designs aim towards high integration, low voltage and current bias. They are usually placed at the front-end receiver system, immediately following the antenna. An LNA must amplify extremely low signals without adding noise, thus preserving required system signal-to-noise ratio at extremely low power levels. The complex signals in todays digital communication systems also require an LNA designer to carefully consider stability and noise figure performance.

MGA-17516 base station applications

The MGA-17516 is an ideal choice for a wireless infrastructure base station application, particularly in the tower mounted amplifier (TMA), front end LNA, multi-carrier power amplifier (MCPA) and radio cards as illustrated by the shaded triangles in the base station architecture in Figure 1. In this application note, MGA-17516 application circuits for the frequency band of 1.7 GHz to 2.0 GHz are discussed in detail.

Tower Mounted Amplier/LNA Single-Ended (SE) Diversity LNA Diversity LNA Main Main LNA Radio Cards Balanced LNA

Multi-Carrier PA (MCPA)

Figure 1. Typical base station architecture and MGA-17516 applications

Spectrum Allocation
With the complexity of the electromagnetic spectrum, it is useful to review the major mobile station and base station frequency allocations. Table 1 shows the bands suitable for the MGA-17516.

MGA-17516 LNA Overview

MGA-17516 is housed in a miniature 4.0 x 4.0 x 0.85 mm, 16-pin Quad-Flat-Non-Lead (QFN) package. The MGA-17516 is specified at Vdd = 5 V and biased at Vgg = 0.57 V, which will typically set drain current, Id, to 50 mA. This bias condition delivers an exceptionally low noise figure of 0.52 dB, a high gain of 17.2 dB, an IIP3 of 13.7 dBm and a P1dB of about +21.5 dBm at 1.85 GHz. Typical applications for the MGA-17516 are cellular base station transceiver radio cards, tower mounted amplifiers, combiners, repeaters and remote/digital radio heads. The footprint and pin configurations is shown in Figure 2. Pin
5 8 13 16 GND Others

Table 1. Frequency Allocation in MHz

System
CDMA 1900 WCDMA GSM 1800e GSM 1900 TDMA 1800 iDEN

Uplink (reverse)
18501910 19201980 17101785 18501910 17101785 806821

Downlink (forward)
19301990 21102170 18051880 19301990 18051880 851866

Usage
RFin 1 RFin 2 RFout 1 RFout 2 Ground Not used

Description
RF input or gate of FET 1 RF input or gate of FET 2 RF output or drain of FET 1 RF output or drain of FET 2 Device ground Can be left unconnected Pin 13 Pin 14 Pin 15 Pin 16

The uplink is defined as transmission from mobile station (MS) to base station (BTS), and the downlink is defined as transmission from base station to mobile station.
The MGA-17516 is an economical, identical pair, low noise, GaAs MMIC amplifier with a compact 16 mm2 footprint and 0.85 mm height. Its low noise, high gain and high linearity are ideal for 1.7 GHz to 2 GHz band cellular infrastructure applications. The device can be used in both single and balanced mode circuits.

EAXXX RE16A ZZZZ

Pin 12 Pin 11 Pin 10 Pin 9

GND

Pin 1 Pin 2 Pin 3 Pin 4

Figure 2. MGA-17516 footprint and pin configuration

Pin 8 Pin 7 Pin 6 Pin 5

MGA-17516 Balanced Amplifier Demonstration Board Design

PCB structure
The MGA-17516 demonstration board is a three-layer PCB with a 10-mil top layer and a 52-mil bottom layer. The first layer uses Rogers RO4350 material with a dielectric constant of 3.48. The second layer, which is used for mechanical rigidity, is FR4 with a dielectric constant of 4.2. The metal layers use 0.5-oz. copper. The unpopulated demonstration board is shown in Figure 3. The stacking structure of the PCB is illustrated in Figure 4. The total thickness of the board is 62 mils. SMA connectors (EF Johnson 142-0701-851) can be attached at the board edges. DC pin headers are soldered at the top edge of the top layer.
1483.001 (mils)

Demonstration board modification for single-end operation

The demonstration board can also be used as a singleended application board by cutting off the coupler section on both the right and left sides of the board. The SMA connectors are then soldered at the input and output transmission lines directly. As shown in Figure 5, a cut approximately 6 mm in from each edge must be made to remove the coupler sections. Populated demonstration boards for single-ended and balanced amplifier configurations are shown in Figure 6 and 7 respectively. In Figure 6 note where the coupler PCB area has been removed.

936.013 (mils) Figure 3. MGA-17516 balanced amplifier demonstration board ~ 6 mm ~ 6 mm Figure 4. Stacking structure of the demonstration board PCB Figure 5. Modification of the balanced amplifier demonstration PCB for single-ended operation Figure 6. MGA-17516 single-ended amplifier demonstration board 3 Figure 7. MGA-17516 balanced amplifier demonstration board

MGA-17516 DC Biasing Circuits and Design

Passive bias
Biasing the Avago MGA-17516 is accomplished by the use of a voltage divider circuit that consists of R2 and R3, as illustrated in Figure 8. The voltage for the divider is derived from the drain voltage that provides a form of voltage feedback to help keep drain current constant. The purpose of R1 is to enhance low frequency stability of the device by providing a resistive termination at low frequencies. Capacitor C5 provides a low frequency bypass for R1. Capacitor C3 provides a high frequency bypass. R2 = Vgs IBB (Vds Vgs) R2 Vgs Equation 1 Here is a simple example based on choosing an IBB of 0.44 mA, a VDD of 5 V and a VDS of 5 V: R2 = 0.57 V 0.44 mA = 1.3 k:

R3 =

(5.0 V 0.57 V) (1.3 k:) 0.57 V

= 10.1 k:

With a Vgs of 0.57 V, drain current, Id, will be approximately 50 mA. Figure 8 shows the complete passive bias schematic for a low noise amplifier design using the MGA-17516. The repeatability of the biasing depends on device-to-device variation of Vgs. For better bias setting repeatability, an active bias circuit is recommended.

R3 =

Equation 2

Where: IBB is the desired current flowing through the R2/R3 voltage divider network.

+ R2 Vd=+5.0 V

C4 R1 C3

R3

R5

C6 C5

L1 RF Input C1 Figure 8. Single-ended MGA-17516 amplifier with a passive bias circuit R6

L2 RF Output C2

Active bias
The main advantage of an active bias scheme is the ability to hold the drain-to-source current constant with temperature variations and device Vgs variation. A very inexpensive method of accomplishing this uses two PNP bipolar transistors arranged in a current mirror configuration, as shown in Figure 9. Due to resistors Ra and Rc this circuit is not acting as a true current mirror, but if the voltage drops across Ra and Rc are kept identical then the circuit does display some of the more useful characteristics of a current mirror. For example, transistor Q1 is configured with its base and collector tied together. This acts as a simple PN junction, which helps temperature compensate the emitter-base junction of Q2. To calculate the values of Ra, Rb, Rc, and Rd the following parameters must be known or chosen first: 1. Ids, the device drain-to-source current 2. IR, the reference current for active bias 3. Vdd, the power supply voltage 4. Vds, the device drain-to-source voltage 5. Vgg, the typical gate bias voltage 6. Vbe1, the typical base-emitter turn on voltage for Q1 and Q2 Resistor Rc, which sets the desired device drain current, is calculated as follows: Rc = Vdd Vds Ids + Ic2 Equation 3 For stability IC2 is chosen to be ten times the typical gate current. IC2 is also equal to the reference current, IR. The next three equations are used to calculate the remaining bias resistors. Ra = Vdd Vds IR Equation 4

Note that the voltage drop across Ra must be set equal to the voltage drop across Rc, but with a current of IR. Rb = Vds Vbe1 IR Equation 5

Resistor Rb sets the bias current through Q1. Rd = Vg Ic2 Equation 6

Resistor Rd sets the MGA-17516 gate voltage. By forcing the emitter voltage (VE) of transistor Q1 equal to Vds, this circuit regulates the drain current much like a current mirror. As long as Q2 operates in the forward active mode, this holds true. In other words, the collectorbase junction of Q2 must be kept reverse biased.

Q1 Rb Ra + Vdd Rd C4 C3 R1 Q2 Rc C6 C5 R4

R3

L1 RF Input C1 Figure 9. MGA-17516 1.85 GHz LNA active bias circuit

L2 RF Output

R5

C2

Stability Analysis
Circuit stability is also one of the important parameters in amplifier design. Unless a circuit is actually oscillating on the bench, it may be difficult to predict instabilities without actually presenting various VSWR loads at various phase angles to the amplifier. Unconditional stability means that with any load presented to the input our output of device, the circuit will not become unstable. Instabilities are usually caused by three phenomena: internal feedback of the transistor, external feedback around the transistor caused by external circuit or an excess of gain at frequencies outside of the band of operation [2]. S-parameter files (S2P) which are available from http://www/avagotech.com will aid in stability analysis. Calculating Rollett stability factor, K, and generating stability circles are two methods made considerably easier with software simulations. An amplifier will be unconditionally stable if the following necessary and sufficient conditions are met: K= 1 _S11_2 _S22_2 + _D_2 2_S12 S21_ > 1, The K stability plots only address the performance near the desired operating frequency. It is still important to analyze out-of-band performance in regards to abnormal gain peaks, positive return loss and instability. A simulation tool is of great help when trying to optimize an amplifier for stability. An MGA-17516T stability factor plot made with ADS software is shown in Figure 10. It is evident that the stability of the MGA-17516 is good across the frequency (f < 20 GHz). The instability at lower frequency (f < 1.5 GHz) can be fixed by the input matching and low frequency bypass capacitors, which will be shown in the later part of this application note.
5 4 Stability Factor (K) 3 2 1 0 0 2 4 6 8 10 12 freq, GHz 14 16 18 20

_D_ < 1 When the K stability factor is greater than unity, the circuit will be unconditionally stable for any combination of source and load impedance. If K is less than unity, the circuit is potentially unstable, and oscillation may occur with a certain combination of source or load impedance presented to the amplifier.

Figure 10. MGA-17516 stability factor, K, over frequency

MGA-17516 Amplifier Design Process

Design goals
The MGA-17516 operates as a normal FET requiring both input and output matching as well as DC biasing, but unlike a depletion mode transistor, the enhancement mode FET requires a single positive power supply. This means a positive voltage is placed on the drain and the gate in order for the transistor to turn on. In this paper, three designs will be covered: 1. Single-ended, low noise amplifier with the best noise figure 2. Single-ended amplifier with the best input return Loss 3. Balanced low noise amplifier with the best noise figure A successful LNA design presents considerable challenges due to simultaneous requirement for high gain, low noise figure, good input and output matching and unconditional stability across the frequency band. The primary goals for an RF amplifier design are: 1. Low noise figure / Best return Loss 2. Adequate gain 3. Stability, K > 1 4. High linearity, relatively high IIP3 and P1dB at the frequency of operation 5. DC bias Design goals for two different types of amplifier were chosen for the MGA-17516, as shown in Table 2.

Linear analysis and CPWG transmission line design

For a linear analysis of the amplifier circuit shown in Figure 9, the transistor can be represented with two-port S-parameters using the Touchstone format. The S2P file can be downloaded from Avago Technologies wireless design center web site, http://www.avagotechwireless.com. The circuit components can then be added to the simulation circuit. The more detailed the simulation, the more accurate the results will be. An accurate circuit simulation is the first step in a successful amplifier design. Proper transmission line design is important for a successful amplifier design. In this design, all microstrip sections use a 10-mil thick PCB layer of RO4350 dielectric material. The board has a coplanar waveguide (CPWG) transmission line with a characteristic impedance of 50 : at the 1.85 GHz design frequency. With the free AppCAD simulation software available from Avago (http://www/avagotech. com/docs/6001), the CPWG dimensions are easily calculated. The AppCAD CPWG design screen is shown in Figure 11.

Figure 11. CPWG design using the Avago AppCAD software

Table 2. MGA-17516 Amplifier Design Goals

Parameter at 1.85 GHz
Gain Noise Figure, NF Input 3rd Order Intercept Point, IIP3 Output P1dB Compression, OP1dB Input return loss, IRL Output return loss, ORL Supply current, Vdd / Idd Frequency

Low Noise Amplifier

17-18 dB < 0.55 dB > 9 dBm 5 V / 50 mA 1.85 GHz

Best IRL Amplifier

> 18 dB >10 dB >10 dB 5 V / 50 mA 1.85 GHz

Low Noise Amplifier Design for Best NF

Noise circle and gain circle analysis
In order to minimize the amplifier noise figure, the input matching circuit of this demonstration board amplifier is tuned to present *opt to the input of the MGA-17516. In the ADS simulation, microstrip transmission lines are used in place of CPWG lines. Microstrip and CPWG lines are very similar in terms of length and dimension; therefore, microstrip lines are used to ease the simulation process. Figure 12 shows the complete simulation circuit model of the MGA-17516 and microstrip transmission lines. Figure 13 shows the location of *opt, the noise circle and the gain circle for the MGA-17516. Noise circles refer to the contours of constant noise figure for a two-port when plotted in the complex plane of the input admittance of the two-port. The minimum noise figure is presented by a dot, while for any given noise figure higher than the minimum, a circle can be drawn[2]. Gain circles also refer to the contours of constant gain for a two-port when plotted in the complex plane of the input admittance of the two-port. The maximum gain is presented by a dot, while any given gain which is lower than the maximum gain is drawn as a circle.

GRM15 C7 Part Number=GRM155L81E 103KA 01 VIA GND V2 MLIN TL22 MCORN Corn1 VIA GND V3

GRM15 C8 Part Number=GRM155L81E 103KA 01 MLIN TL23 MCORN Corn2

MLIN TL20

MLIN TL18

R R1 R=15 Ohm MLIN TL21 GRM18 C11 Part Number=GRM1885C 1H300JA01 VIA GND V1 MLIN TL24 MLIN TL16 GRM18 C12 Part Number=GRM1885C 2A100JA01 VIA GND V4

R R3 R=6.8 Ohm MLIN TL19

MTEE_ADS Tee2

MTEE_ADS Tee5 MLIN TL25

MLIN TL17 CC I_0603CS SNP2 R R7 R=120 Ohm MLIN TL3 MLIN TL8 LQG18 L9 Part Number=LQG 18HN1 5NJ00

MLIN TL9 GRM18 C10 Part Number=GRM1885C1 H3R3C Z01 MTEE_ADS Tee6 MLIN TL15 MLIN TL13

GRM18 C9 Part Number=GRM1885C 2A150JA01 1 Term Term1 Num=1 Z=50 Ohm MLIN TL1 MLIN TL2 MTEE_ADS Tee1 MLIN TL7 Ref 2 MLIN TL14

R R4 R=0 Ohm

S2P SNP1 File="C:\users\2008_Folder\Rapala_E_prj\data\Data_Form_RnD\Jan_12\MGA_16516_5V 52mA_09112.S2P"

Term Term2 Num=2 Z=50 Ohm

LStab Circle L_Stab Circle L_Stab Cicle 1 L_Stable Circle 1=1_stab_circle (S, 51)

SStab Circle S_Stab Circle S_Stab Cicle 1 S_Stable Circle 1=1_stab_circle (S, 51)

Stab Fact Stab Fact Stab Fact1 Stab Fact1=stab_fact (S)

MuPrime MuPrime MuPrime1 MuPrime=mu_prime (S)

Mu Mu Mu1 Mu1=mu (S)

S - P A R A M E T E R S S_Param SP1 Start=50 MHz Stop=20 GHz Step=50 MHz Options Options1 Temp=25 Tnom=25

O P T I O N S

m u R a t a MURATA Include muRata

M S u b MSUB MSub1 H=10 mil Er=3.48 Mur=1 Cond=1.0E + 50 Hu=3.9e + 03 4 mil T=1.4 mil TanD=0 Rough=0 mil

N E T L I S T TDK_ML_DK_Include TDK_ML_DK_Include

I N C L U D E

V_RelTol= V_AbsTol= I_RelTol= I_AbsTol= Give AII Warnings=yes Max Warnings=10

Figure 12. ADS schematic simulation setup 8

conj_S11 Noise_circle Min Noise_circles GAcircles

*OPT S11*

Gain Circle { 19, 20, 21 } dB NF Circle { 0.52, 0.62, 0.72 } dB

Figure 13. Positions of *OPT, noise circles, and gain circles at 1.85 GHz

Matching for Best NF

The input impedance matching movement towards opt is clearly shown in Figure 14. From the chart, a shunt inductor and a series capacitor are needed to transform the 50 : port to a point closer to *opt. In real circuits with practical inductors, the effects of the microstrip line that connects the inductor and the input pin of the device must be taken into consideration when designing the input matching network.

*OPT Noise_circle Min Noise_circles

Shunt Inductor (L1)

Series Capacitor (C1)

Figure 14. Input matching for the Fmin point 9

Bill of material: Single-ended amplifier

Each FET amplifier is biased at a Vds of 5 V and an Id of 50 mA. Typical Vgs is 0.57 V. The complete populated singled ended amplifier is shown in Figure 6. Component placement is shown in Figure 15, and the bill of materials is shown in Table 3. The complete single-ended amplifier schematic is shown in Figure 16.

Figure 15. Component placement for the single-ended amplifier demonstration board

Table 3. Component Part List for the MGA-17516 Single-ended Amplifier

Components
C1 C2 C3 C5 C4, C6 L1 L2 R1 R2 R3 R4 R5

Value
1000 pF 1000 pF 4.7 PF 4.7 PF 9 nF 9 nH 8.2 nH 15 : 1.3 k: 10 k: 0: 9.1 :

Type
Murata Murata Murata Murata Murata Coilcraft Toko Rohm Rohm Rohm Rohm Rohm

Size
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402

Purpose
DC block and input matching DC block and output matching Bypass capacitor Bypass capacitor Low frequency bypass capacitor Input matching for low noise figure (High Q Factor) Output matching Low frequency stability Voltage divider for biasing Voltage divider for biasing Jumper Low frequency stability

10

+ R2 Vd=+5.0V

C4 R1 C3

R3

R5

C6 C5

L1 RF Input C1 Figure 16. Single-ended, LNA design schematic R4

L2 RF Output C2

Measured performance: Single-ended LNA

The measured noise figure and gain of the completed amplifier are shown in Figures 17 and 18. Noise figure is less than 0.55 dB from 1.7 GHz to 2 GHz. Gain is typically 16.9 dB at 1.85 GHz. The simulated noise figure was slightly better than the measured noise figure of the circuit for in-band performance because of the secondary noise losses, such as connector loss.
0.7 Measured NF Simulated NF 0.6 N.Figure (dB) Gain (dB) 20 25 Measured Gain Simulated Gain

0.5

15

0.4

10

0.3 1500

1600

1700 1800 1900 Frequency (MHz)

2000

2100

5 1500

1600

1700 1800 1900 Frequency (MHz)

2000

2100

Figure 17. Single-ended LNA amplifier: Measured and simulated noise figure over frequency

Figure 18. Single-ended LNA amplifier: Measured and simulated gain over frequency

11

Measured input return loss and output return loss are shown in Figure 19 and Figure 20 respectively. The input return loss at 1.85 GHz is 6.6 dB with a corresponding output return loss of 14.7 dB. From both figures, it is evident that both simulated and measured IRL and ORL graphs are very similar. Figure 21 shows both measured and simulated isolation. The stability factor, both simulated and measured, is shown in Figure 22. The simulated curve beyond 6 GHz is inaccurate due to the limited maximum frequency performance of the SMT components used in the simulation setup. The amplifier input intercept point (IIP3) was measured at a nominal +17.7 dBm at a DC Vds bias of 5.0 V and an Idd of 50 mA, as shown in Figure 23. Output P1dB was measured at +20.5 dBm at 1.85 GHz, as shown Figure 24.
0 Measured IRL Simulated IRL -5 IRL (dB) ORL (dB) -10 -15 -20 -15 1500 -25 1500 0 -5 Measured ORL Simulated ORL

-10

1600

1700

1800 1900 Frequency (MHz)

2000

2100

1600

1700 1800 1900 Frequency (MHz)

2000

2100

Figure 19. Single-ended LNA amplifier: Measured and simulated IRL over frequency

Figure 20. Single-ended LNA amplifier: Measured and simulated ORL over frequency

0 Measured Isolation Simulated Isolation Isolation (dB) -20 Stability, K

5 4 3 2 1

-40

Measured Stability K Simulated Stability K 0 5000 10000 Frequency (MHz) 15000 20000

-60 1500

1600

1700 1800 1900 Frequency (MHz)

2000

2100

Figure 21. Single-ended LNA amplifier: Measured and simulated isolation over frequency

Figure 22. Single-ended LNA amplifier: Measured and simulated stability factor, K, over frequency

12

20

Single-ended Amplifier Designed for Best Return Loss (conjugate match)

Gamma in (*in) analysis
The MGA-17516 was designed for the best input return loss by terminating the device input with a conjugate of *in. The amplifier was designed for a Vds of 5 volts and an Ids of 50 mA. In conjugate matching, we make an assumption that the *in is equivalent to S11. According to Equation 7, if S12 is very small, then *in approximately equals S11.
2000

IIP3 (dBm)

18

16 Measured IIP3 14 1700 1750 1800 1850 1900 Frequency (MHz) 1950

Figure 23. Single-ended LNA amplifier: Measured IIP3 over frequency

CS S12 S21 Cin = S11 + 1 S22 CL

Equation 7

24

OP1dB (dBm)

22

As shown in Figure 13, *opt and S11* are far apart from each other on the Smith Chart. As discussed in the preceding design, the low NF design did not give optimum input return loss. In applications where the amplifier NF is not the most important parameter, a simultaneous conjugate match can be implemented to yield maximum possible gain.

Conjugate match for best return loss

20 Measured OP1dB 18 1700 1750 1800 1850 1900 Frequency (MHz) 1950 2000

A simultaneous conjugate match also gives a very good return loss at both input and output ports. The movement towards the input conjugate match point is shown in Figure 25. Simulations using the s2p data show that a shunt inductor of 6.2 nH and 20 pF series capacitor at the input is needed to move the 50 impedance towards the S11* point. After the input is matched to the S11*, the same method is used to match to the S22* point for optimum output return loss performance. With the help of an ADS simulation, a 33 nH shunt inductor and 30 pF series capacitor was needed to match the output circuit. However, to achieve the matching condition on the demonstration board, a slight modification / tuning was needed.

Figure 24. Single-ended LNA amplifier: Measured OP1dB over frequency

13

Series Capacitor (C1)

Shunt Inductor (L1) conj_S11

Conjugate match point

Figure 25. Input matching for conjugate matching method

Bill of material: Conjugate match amplifier

Each FET amplifier is biased at a Vds of 5 V and an Id of 50 mA. Typical Vgs is 0.57 V. The complete populated amplifier is shown in Figure 6. The component placements are identical with the low noise amplifier design as shown in Figure 15. The bill of materials is shown in Table 4. The complete schematic is shown in Figure 26.

Table 4. Component Part List for MGA-17516 (Conjugate Match Amplifier)

Components
C1 C2 C3 C5 C4, C6 L1 L2 R1 R2 R3 R4 R5 R6

Value
20 pF 33 pF 10 pF 9 pF 4.7 nF 3.6 nH 39 nH 12 : 1.3 k: 10 k: 0: 120 : 9.1 :

Type
Murata Murata Murata Murata Murata Toko Toko Rohm Rohm Rohm Rohm Rohm Rohm

Size
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402

Purpose
DC block and input matching DC block and output matching Bypass capacitor Bypass capacitor Low frequency bypass capacitor Input matching for best input RL Output matching for best output RL Low frequency stability Voltage divider for biasing Voltage divider for biasing Improve stability, K factor Low frequency stability

14

+ R2 Vd=+5.0V

C4 R1 C3 L1

R3

R5

C6 C5

L2

RF Input C1 Figure 26. Schematic for single-ended, conjugate match amplifier R4 C2

RF Output

Measured performance: Single-ended, conjugate matched LNA

The measured IRL and ORL for the conjugate matched LNA are shown in Figure 27 and Figure 28. Measured at 1.85 GHz, the IRL is 11 dB and the ORL is 13 dB. As shown in Figure 29, the gain for the complete amplifier is about 17.9 dB at 1.85 GHz. The isolation for the amplifier is more than 20 dB at 1.85 GHz, as shown in Figure 30.
0 -5 ORL (dB) -10 -15 -20 -25 1500 0 -5 -10 -15 -20 -25 1500 Measured ORL Simulated ORL

IRL (dB)

Measured IRL Simulated IRL 1600 1700 1800 1900 Frequency (MHz) 2000 2100

1600

1700 1800 1900 Frequency (MHz)

2000

2100

Figure 27. Measured and simulated IRL for the conjugate matched LNA

Figure 28. Measured and simulated ORL for the conjugate matched LNA

25 Measured Gain Simulated Gain

Isolation (dB)

0 Measured Isolation Simulated Isolation -20

20 Gain (dB)

15

-40

10 1500

1600

1700

1800 1900 Frequency (MHz)

2000

2100

-60 1500

1600

1700 1800 1900 Frequency (MHz)

2000

2100

Figure 29. Measured and simulated gain for the conjugate matched LNA 15

Figure 30. Measured and simulated isolation for the conjugate matched LNA

Figure 31 shows the K stability factor for both simulated and measured performance across a 20 GHz frequency. Figure 32 shows noise figure performance at 1.85 GHz is around 0.7 dB. Figure 33 and Figure 34 show linearity measurements for the conjugate match amplifier. Measured at 1.85 GHz, IIP3 is around +14.4 dBm and OP1dB is around +21 dBm.
5 4 N.Figure (dB) Stability, K 3 2 1 0 0 5000 10000 Frequency (MHz) 15000 20000 1.4 1.2 1.0 0.8 0.6 0.4 1500 Measured N.Figure Simulated N.Figure

Measured Stability K Simulation Stability K

1600

1700 1800 1900 Frequency (MHz)

2000

2100

Figure 31. Measured and simulated stability factor, K, for the conjugate matched LNA

Figure 32. Measured and simulated noise figure for the conjugate matched LNA

16 Measured IIP3 15 OP1dB (dBm) IIP3 (dBm)

22

21

14

20

13

19 Measured OP1dB

12 1700

1750

1800 1850 1900 Frequency (MHz)

1950

2000

18 1700

1750

1800 1850 1900 Frequency (MHz)

1950

2000

Figure 33. Measured IIP3 for the conjugate matched LNA

Figure 34. Measured P1dB for the conjugate matched LNA

Table 5 shows the comparison between the low noise amplifier design and the conjugate matched amplifier just discussed. Measurements were made from 1.7 GHz to 2.0 GHz.

Table 5. Measured Parameters on LNA and Conjugate Matching Amplifier

Parameter
Frequency Idd Input RL Output RL Gain N. Figure IIP3 OP1dB K (Up to 20 GHz) 16 GHz mA dB dB dB dB dBm dBm

Low Noise Amplifier

1.7 50 6.4 13.6 17.7 0.5 16.5 20.6 >1 1.8 50 6.6 14.2 17.1 0.52 17.5 20.6 >1 1.9 50 6.6 15.1 16.7 0.54 17.9 20.5 >1 2.0 50 6.7 16 16.2 0.56 18.8 20.7 >1

Conjugate Matched Amplifier

1.7 50 13.9 10.3 18.7 0.79 13.7 20.7 >1 1.8 50 12.1 12.1 18.1 0.72 14.3 20.9 >1 1.9 50 10.9 14 17.7 0.63 14.4 21.1 >1 2.0 50 10 16.1 17.3 0.6 14.2 21.3 >1

Balanced Low Noise Amplifier Design

Introduction to balanced amplifiers
For cellular tower-mounted applications, a high intercept point, 5 V supply operation and low current consumption are required. Figure 35 shows the top level schematic of the balanced LNA. The balanced topology has several important features and advantages over the single-ended amplifier, such as: 1. Intercept point is 3 dB higher than a single stage 2. 50 : input and output match 3. Redundancy which minimizes a hard failure A balanced configuration ensures a good input and output match and helps ensure stability. However, the splitter/combiner network must be low loss, physically small, and have good phase and amplitude matching over the bandwidth of interest. Finally, the bandwidth should be high enough to include the uplink frequencies (mobile device to base station) for cellular standards around 1800 MHz.

Splitter/Combiner selection
An important consideration for a balanced amplifier is the splitting and combining of RF signal. Power dividing and power combining are generally accomplished by using a power divider or a hybrid coupler. Power dividers and hybrid couplers are passive microwave components that can be printed on a substrate (in microstrip form) or can be obtained in surface mount package. When designing the splitter network for a balanced LNA, it is important to minimize the insertion loss and return loss while providing equal power to each of the two amplifiers. Although power dividers are used in balanced amplifier design, low loss hybrid couplers are proven to be superior for several reasons. Hybrid couplers are four-port devices characterized by good matching, isolation and a fixed 90 phase shift between the output ports. Two popular hybrids are the branch-line and broadside-coupled hybrid. The bandwidth of a branch-line hybrid is limited to 10-20%, but a single section broadside coupler can have bandwidth as large as an octave. A broadside coupler also requires only half the amount of line used in a branch line hybrid, and can therefore be smaller in size. Reflected power from each of the two identical LNA inputs recombines at the isolated port of the hybrid coupler and is dissipated in the resistive termination. This feature of the hybrid coupler allows Avago to design each LNA for optimum noise figure performance, without actually worrying about return loss from each of the two LNAs. Usually, if a hybrid coupler is used on the input side then an identical hybrid coupler can be used on the output side to recombine the signals. Nevertheless, the selection of the coupler is mainly due to the application of the amplifiers. Table 6 shows some guidelines to help select the couplers. In LNA applications, the insertion loss of the coupler at the input port greatly influences the overall NF of the LNA. Thus, a low-insertion-loss coupler is necessary for a LNA that has extremely good NF performance like MGA17516. To demonstrate the MGA-17516 as a balanced LNA, the Anaren/Xinger XC1900L-03S surface mount coupler was chosen for its low 0.20 dB maximum insertion loss and tight amplitude performance.

Figure 35. Balanced amplifier configuration

17

Table 6. Coupler Selection Guidelines

Applications
LNA Power amplifier RF amplifier

Input Coupler
Very good insertion loss Moderate insertion loss Moderate insertion loss

Output Coupler
Moderate insertion loss Good power handling capability Moderate insertion loss

Table 7. Anaren/Xinger XC-1900L-03S Hybrid Coupler Specification

Test Parameter
Bandwidth Insertion loss Isolation VWSR Amplitude balance Phase Power rating Dimension Tjc Operating temperature

Specification
1.7 2.0 GHz 0.12 dB (max) 23 dB (min) 1.17 (max) 0.13 dB (max) 90 2.0 120 W (CW) (average) 650 x 480 x 69 mil 36C/W -55 C to +95 C

To obtain the best performance from the hybrid coupler, CPWG or microstrip lines must be designed carefully. A good recommendation on the coupler PCB design can be found at http://www.anaren.com. The balanced demonstration board was verified by measuring the return loss at the SMA connector with both ends of the lines terminated with 50 :, as shown in Figure 36. As shown in Figure 37, the balanced demonstration board with an Anaren XC-1900L-ES coupler had a measured return loss of more than 15 dB at 1.85 GHz on both the input and output ports.

0 -5 Return Loss (dB) -10 -15 -20 -25 -30 0 Figure 36. Balanced board terminated with 50 : (size 0603) resistor 500 1000 1500 2000 Frequency (MHz) 2500 3000 Coupler (Input Side) Coupler (Output Side)

Figure 37. Measured return loss of Anaren/Xinger XC-1900L-ES coupler on the balanced amplifier board

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Balanced amplifier bill of material

As discussed previously, the single-ended amplifier was designed for a Vds of 5 V and an Ids of 50 mA. For a balanced amplifier, Ids must be doubled to 100 mA. The populated board is shown in Figure 7. The schematic for the balanced amplifier board is shown in Figure 38. Component placement is shown in Figure 39, and the bill of materials is shown in Table 8.
+ R2 Vd=+5.0 V

C4 R1 C3 L1

R3

R5

C6 C5

L2 RF Input Anaren Coupler R11 R12 L3 C9 C10 R7 R9 C11 C12 L4 C1 C7 R4 R10 R13 Anaren Coupler R14 RF Output

C2 C8

R11

R8

Vd=+5.0 V +

Figure 38. Schematic for the balanced amplifier design

The board gives the designer several design options for the RF circuitry. The evaluation board was designed so that the input and output impedance matching networks can be adjusted to optimize performance, particularly for noise figure over the 1.7 GHz to 2 GHz frequency range. For a LNA RF layout, the main constraint is that the circuit must maintain a balanced configuration; the path lengths in each arm of the amplifier must be equal. The effect of uneven path lengths will result in out-of-phase summing of the signals and lower output power and worse linearity than expected.

Figure 39. Component placement for the balanced amplifier demonstration board 19

Table 8. Component Part List for the MGA-17516 Balanced LNA Design
Components
C1, C7 C2, C8 C3, C9 C5, C11 C4, C6, C10, C12 L1, L3 L2, L4 R1, R7 R2, R8 R3, R9 R4, R10 R5, R11

Value
1000 pF 1000 pF 9 pF 9 pF 4.7 nF 9 nH 8.2 nH 15 : 1.3 k: 10 k: 0: 9.1 :

Type
Murata Murata Murata Murata Murata Coilcraft Toko Rohm Rohm Rohm Rohm Rohm

Size
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402

Purpose
DC block and input matching DC block and output matching Bypass capacitor Bypass capacitor Low frequency bypass capacitor Input matching for low noise figure (High Q Factor) Output matching Low frequency stability Voltage divider for biasing Voltage divider for biasing Low frequency stability (if needed) Low frequency stability

Measured performance: Balanced amplifier

As measured on the single-ended and balanced demonstration boards, MGA-17516 performance can be seen in the following graphs. All these measurements included the loss from the SMA connectors, board traces and hybrid couplers (for the balanced amplifier). As shown in Figures 40 and 41, the input and output return losses of the balanced amplifier were far better than 20 dB over 1.7 GHz to 2 GHz.
0 0

-10 ORL (dB) Balanced Amp Single-Ended Amp -40 1500 1600 1700 1800 1900 Frequency (MHz) 2000 2100 IRL (dB)

-10

-20

-20

-30

-30 Balanced Amp Single-Ended Amp -40 1500 1600 1700 1800 1900 Frequency (MHz) 2000 2100

Figure 40. Measured IRL for balanced and single-ended amplifiers over frequency

Figure 41. Measured ORL for balanced and single-ended amplifiers over frequency

20

The gain of the balanced amplifier was very similar to the gain of the single-ended amplifier, as shown in Figure 42. The gain on the single-ended board was slightly higher than the gain of the balanced board. This was caused by the insertion loss of the input and output couplers. The gain was more than 16.5 dB for both configurations at 1.85 GHz. The noise figure performance for the single-ended amplifier is around 0.10 dB better if compared to the balanced amplifier. This is due to the insertion loss of the input coupler on the balanced board. As shown in Figure 43, at 1.85 GHz the noise figure for single-ended amplifier is about 0.5 dB and for the balanced amplifier it is about 0.6 dB. The reverse isolation of the single-ended board and balanced amplifiers, as shown in Figure 44, was more than 25 dB between 1.5 GHz and 2.5GHz. The stability factor, K, for both balanced and single-ended LNA designs is shown in Figure 45.
20 Balanced Amp Single-Ended Amp 0.8 N.Figure (dB) 18 Gain (dB) 1 Balanced Amp Single-Ended Amp

0.6

16

0.4

14 1500

1600

1700 1800 1900 Frequency (MHz)

2000

2100

0.2 1500

1600

1700 1800 Frequency (MHz)

1900

2000

Figure 42. Measured gain for the balanced and single-ended amplifiers over frequency

Figure 43. Measured noise figure for the balanced and single-ended amplifiers over frequency

-10 Balanced Amp Single-Ended Amp Isolation (dB) -20 Stability, K

5 4 3 2 1 Balanced Amp Single-Ended Amp

-30

-40 1000

1500 2000 Frequency (MHz)

2500

5000

10000 Frequency (MHz)

15000

20000

Figure 44. Measured isolation for balanced and single-ended amplifiers over frequency

Figure 45. Measured stability factor (K) for balanced and single-ended amplifiers over frequency

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Measured wideband characteristics are shown in Figures 46 and 47 for both balanced and single-ended amplifiers respectively.
40 Gain Gain, IRL, ORL, Isolation (dB) Gain, IRL, ORL, Isolation (dB) 0 ORL -40 Isolation -80 IRL 0 ORL -40 Isolation -80 0 1000 2000 3000 4000 Frequency (MHz) 5000 6000 0 1000 2000 3000 4000 Frequency (MHz) 5000 6000 40 Gain

IRL

Figure 46. Wideband measurement: Balanced amplifier

Figure 47. Wideband measurement: Single-ended amplifier

Table 9 summarizes MGA-17516 measured performance on both single-ended and balanced demonstration boards. Measurements were made with a Vdd of 5 V and Vgs of 0.57 V.

Table 9. Measured Performance Comparison

Parameter
Frequency Idd Gain Input RL Output RL NF P1dB IIP3 GHz mA dB dB dB dB dBm dBm

Single-ended Board
1.7 50 17.7 6.4 13.5 0.5 20.6 16.5 1.8 50 17.1 6.5 14.3 0.52 20.6 17.5 1.9 50 16.7 6.6 15.1 0.54 20.5 17.9 2.0 50 16.6 6.7 16 0.55 20.7 18.9

Balanced Board
1.7 100 17.5 22.8 28.3 0.6 23.6 18 1.8 100 17.0 20.4 24.3 0.63 23.7 18.6 1.9 100 16.5 18.8 21.7 0.64 23.6 19 2.0 100 16.5 18.5 20.8 0.64 23.5 19.4

22

MGA-17516 channel isolation

The isolation was measured with both channels being powered as shown in Figure 48. The isolation is defined by the difference of two measurements using a two-port network analyzer. To illustrate, the first measurement was made between input and output of the top channel and is called S21. The second measurement was between the input of the top channel and the output of the bottom channel and is called S41. During this second measurement, all unused ports must be terminated with 50 : to ensure accuracy.

Vgs = 0.57 V

Vdd = 5.0 V

S21 In1 Out1

In2

Out2 S41 Vgs = 0.57 V Vdd = 5.0 V

Figure 48. Test setup for isolation between top and bottom channels

The isolation is calculated by subtracting S4, denoted by the dashed line in Figure 48, from S21, denoted by the solid line in Figure 48.
Isolation (dB)

-20

-30

The dashed line is the isolation from the bottom channel to the top channel. As measured on the single-ended board, MGA-17516 isolation was -37 dB at 1.85 GHz.

-40

-50 Top Channel Isolation Bottom Channel Isolation -60 1500 1700 1900 2100 Frequency (MHz) 2300 2500

Figure 49. Isolation between the MGA-17516 top and bottom channels

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Summary and Conclusion

The Avago Technologies MGA-17516 LNA offers a very high performance, power efficient and cost effective solution for low noise amplifier designs. This application note has described two types of designs: a 1.85GHz LNA design and a 1.85GHz conjugate matched amplifier design. RF designers can design an MGA-17516 based amplifier optimized for noise figure or as a conjugate matched amplifier. Avago sales offices offer demonstration boards, and AppCAD simulation software is available from the web at http://www.avagotech.com/docs/6001. S2P parameters (MGA-17516 S2P) can be downloaded from: the www. avagotechwireless.com also.

References
1. Design of Class-E Radio Frequency Power Amplifier Al-Shahrani, Saad Mohammed 2. RF and Microwave Handbook Mike Golio (CRC Press) 3. Applications Note AN-1222: A Low Noise High Intercept Point Amplifier for 1930 to 1990 MHz using the ATF-54143 PHEMT A.J. Ward 4. Application Note AN-1320: Low Noise and High Linearity Applications using the Avago ATF-531P8 Saul Espino 5. Application Note AN-1281: A High IIP3 Balanced Low Noise Amplifier for Cellular Base Station Applications Using Enhancement Mode PHEMT ATF-54143 Transistor and Anaren Pico Xinger 3 dB Hybrid Couplers

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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 2005-2011 Avago Technologies. All rights reserved. AV02-2211EN - April 7, 2011