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High Electron Mobility Transistors (HEMTs)

Source Wg Gate Drain


1000 800
VG = 2 V
VG = 1 V

ID (mA/mm)

Active Region S. I. Buffer

600
gm = 200 mS/mm

d Open channel

400 200 0 0 2 4 6 8 10 12 14 16

Lg Source Wg Gate

Drain

VDS (V)
Active Region S. I. Buffer

Lg

Pinch off

Similar to normally-on MOSFETs but no substrate doping. For accurate formula, refer to Sze: Physics of Semiconductor Devices

Output Power Calculation (AC, not DC)


A

I max
BIAS POINT

IDS
Q

linear Pout, max = I SWING


B

VSWING ISWING 8

Minimize Vknee
V knee

VDS

Maximize Vbreakdown Maximize Imax Maximize ns or nsvs


GaAs pHEMT AlGaN/GaN HEMT 5 (~ Vpinchoff) 100 (over 200 reported for small Lgd) 1.2 (over 2 reported) 14 (32 highest reported)

Vbreakdown

VSWING

Vknee (V) Vbreakdown (V) Imax (A/mm) Pout, max (W/mm)

1 20 0.6 1.4

Sample power calculations


Let Vknee be 4 V, and Vbd be 120 V, and Iswing be 120 mA for a 100 micron gate width device. Calculate the maximum output power in dBm and in W/mm Solution: Total maximum output power = 1/8 (120 4) 120 mW = 1740 mW. So output power in dBm = 10 log1740 = 32.405 dBm. Output power density is 1740 mW/100 micron = 17400 mW/mm = 17.4 W/mm.

If the gain is 15 dB, what is the input power?


Solution: 10 log (Pout/Pin) = 15 Pout = Pin x 101.5 = Pin x 31.62 Pin = 17.4/31.62 = 0.5502 W/mm.

If the dc input power is also given then the Power-Added Efficiency (PAE) can be calculated as (Pout Pin)/Pdc
Slide # 3

Performance criteria for microwave transistors


Output Power: Total microwave power available (W/mm) Gain: G = Pout/Pin, log G = Log Pout Log Pin (Gain usually measured in dB, but Pin and Pout are in dBm) Ft : Maximum frequency of oscillation or the frequency at which the short circuit current gain is 1 Fmax: The frequency at which the power gain is 1 for a perfectly matched load Power added efficiency (P.A.E): (Pout Pin)/Pdc, Pin = input microwave power, Pdc = total dc power in at the gate and drain terminals. Linearity: The measure of gain against input signal level. High linearity means lower harmonic content in the output signal Noise Figure: SNRin/SNRout (usually expressed in dBm by taking the log) Stability: long term and short term operational stability
Slide # 4

AlGaN/GaN HEMT: wish list


High VBr
Minimize
Buffer leakage: GaN:Fe Gate leakage: Insulated-gate

Other device structures to improve VBr

High power efficiency


When efficiency is low Power dissipation at semiconductor devices Ron efficiency

How to maximize efficiency


Eliminate surface traps (passivation/epitaxial solutions) Eliminate bulk traps (growth condition tuning) Decrease leakage (low dislocation density/insulators?)

Slide # 5

Growth Challenge I: heteroepitaxy


Tiny changes in growth conditions have strong effect on GaN properties (T,d, V/III) + very sensitive coalescence process = process much less robust than homo-epitaxy Lattice mismatch High dislocation density in epitaxial layers and at the interface of the heteroepitaxial layers.

time

Slide # 6

Growth Challenges II: alloy epitaxy


GaN technology still less mature than GaAs and InP technology Crystal growth is dominantly heteroepitaxial Alloys: todays high efficiency devices AlxGa1-xN InxGa1-xN xAl < 0.4 xIn < 0.4

AlN

InN

High Al (x=0.5 ~ 1) is currently under intense research (UV LEDs and detectors etc.)

GaN

Alloys with high Al and/or In compositions


difficulties related to interplay of Material properties and Epitaxy process
Stacia Keller et al. UCSB

Slide # 7

AlGaN/GaN high electron mobility transistor: basics


Unlike AlGaAs/GaAs HEMT requiring intentional doping to form charge, 2DEG in AlGaN/GaN HEMT are polarization-induced. No intentionally doping is needed. Electrons come from surface states. 2DEG
Polarization charge Donor-like surface traps (empty)

_ _ _ __ _ __ _ __ _ _ _ _ _ __ _ _

Gate

Source

AlxGa1-xN

Drain

+_ ++ ++ +_ ++ ++ _+ _ +_+ _ _+ _+_+ _ _+ _ +_+ _ _+ _+_+ _ _+ _ +_


Channel 2-DEG GaN

+ + + Donors

Surface states

+++++-

UID AlGaN

Polarization charge

+ + + + + + +

2DEG

AlGaAs/GaAs HEMT

AlGaN/GaN HEMT
Slide # 8

AlGaN/GaN HEMTs: Formation of the 2DEG


Layer structure
20-30 nm Al0.3Ga0.7 N
2DEG

Schematic band diagram

AlGaN

GaN

Ec

Ec d +ve EF

GaN buffer(1-2 m)

Nucleation layer (~ 20 nm) Sapphire/SiC substrate

comp

B
2 DEG

+ B 0 ns = 2 [ B + E F (ns ) Ec ] e de The 2DEG is an explicit function of the surface barrier, AlGaN thickness, and the bound positive charge at the interface
Slide # 9

surf

Comparison with GaAs HEMT Physics


Schematic band diagram AlGaAs/GaAs HEMT
Ec EF

AlGaN

GaN

Ec d

+ve

comp

B
2 DEG

AlGaAs donor layer

GaAs buffer

surf

AlGaAs spacer

No doping is required for the 2DEG to be present at the interface. Higher sheet charge and higher conduction band discontinuity for AlGaN/GaN heterostructure
Slide # 10

Heart of HEMT: 2DEG


for high power, high frequency HEMTs:
high xAl, coherently strained, trap free AlGaN/GaN heterojuction, (abrupt + smooth on an atomic level) carrier confinement, high breakdown voltage, high currents
AlGaN u.i.d. AlGaN:Si ? GaN S.I.

2DEG (density and mobility) Determined by - xAl - interface roughness - alloy scattering - dislocation, etc. Slide # 11

Al2O3/SiC

Ambacher et al, JAP 87(1) 2000

Properties of the 2DEG


2DEG Mobility vs. density
Spacer layer thickness vs. 2DEG density and mobility

dspacer depends on intended application

For AlGaAs/GaAs heterostructures, the spacer layer thickness is important for 2DEG mobility and density The 2DEG does not freeze out at very low temperature unlike the 3D doping The 2DEG mobility does not decrease with decrease in temperature unlike the 3D case The 2DEG mobility can increase with increase in 2DEG density due to increased screening unlike the 3D doping Slide # 12

2DEG Influence of the Al-composition


xAl>0.2: MOCVD
2 [cm / Vs]

300K

~ 1/xAl

1500 1400 1300 1200 1100 1000 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.2 0.4 0.6
-2 13 [10 cm ]

xAl :

- interface problems - strain induced defects - higher impurity incorporation - alloy ordering/clustering ns ~ xAl

300

- charge increases due to spontaneous polarization and piezoelectric effects xAl<0.2: 300K ~ xAl

0.0

ns

xAl

- better confinement of the 2DEG at higher xAl - low xAl = low ns: less efficient screening of defects

relaxed Slide # 13

Temperature dependence of v-F curve


3

3 Electron Velocity (107 cm/s)

Electron Velocity (107 cm/s)

GaN
2

300 K 500 K 700 K

GaAs
2

300 K 500 K 700 K

0 0 200 400 Electric Field (kV/cm) 600

0 0 4 8 12 16 Electric Field (kV/cm) 20

Usually the regions are separated into regions of constant and zero mobility A velocity overshoot is expected for GaN similar to GaAs case, but usually not seen, possibly due to high background doping At higher temperature, the degradation of v-F curve for GaN is much smaller than GaAs
Slide # 14

Temperature dependent mobility

Increasing alloy composition in barrier


Debdeep Jena Ph.D dissertation

Slide # 15

Electron transport
Phonon scattering:
---most important at room temperature

Alloy disorder scattering


---potential disorder from ternary alloy ---important at low and room temperature

Surface roughness scattering


---important at low temperature

Ionized impurities scattering Dislocation scattering Dipole scattering


Mattheissen rule for total mobility:

where i refers to the mobility corresponding to different sources Alloy disorder scattering is the limiting factor at low temperature. Alloy disorder scattering also plays an important role at room temperature when carrier concentration is high. It is due to the ternary nature of AlGaN.
Debdeep Jena Ph.D dissertation

net

=
i

Slide # 16

Methods for reducing scattering


Controllable scattering mechanisms
Background impurity scattering: By growing the material purer Alloy scattering: By putting a thin binary alloy (AlN) at the interface Dislocation scattering: By growing on lattice and thermally matched substrate Interface roughness scattering: By growing very smooth interfacial layers

Rest of the scattering processes are usually physics limited


Slide # 17

2DEG High-mobility AlN interlayers

30 25 cm )
-2

2.5 Mobility (10 , cm /Vs) AlGaN/GaN AlGaN/AlN/GaN 2 1.5 1 0.5 AlGaN/GaN AlGaN/AlN/GaN

AlGaN 1 nm AlN S.I. GaN

20 15 10 5 T = 17 K 0 0.1 0.2 0.3 0.4 Al mole fraction x 0.5

(10

12

sapphire

T = 17 K
0 0 0.1 0.2 0.3 0.4 Alloy composition x 0.5

dAlN = 1 nm

by MBE, I.P. Smorchkova et al., J. Appl. Phys. 90 (2001) 5196

Similar results obtained by MOCVD

no alloy scattering
Slide # 18

AlN as a barrier layer


0.08
6

2DEG density (10 cm )

Al0.22Ga0.78N/GaN AlN/GaN

-2

0.06

5 4 3 2 1 0 0 5 10 15 20 25 30

Probability

AlGaN/GaN interface

0.04 0.02 0.00 24 26 28 30 32 34 36

13

Distance (nm)

AlN barrier thickness (nm)

Simulations Alloy disorder scattering:


---Wavefunction penetration ---Ternary material: AlGaN Use AlN as barrier material
---No alloy disorder scattering: higher mobility ---Higher polarization charge density: higher carrier concentration

Reduce alloy scattering:


---Increase Al composition ---Binary material: AlN

However, after gate metal deposition, it was found to be almost ohmic due to tunneling!

Slide # 19

AlGaN/AlN/GaN Heterostructure
Incorporation of a thin AlN (<1nm) into a standard AlGaN/GaN HEMT The thickness of AlN interfacial layer is below critical thickness for formation of 2DEG. The main purpose is to improve mobility. Thin AlN layer forms a larger effective Ec, which affects both mobility and carrier concentration.

25 nm Al0.3GaN 0.7-1 nm AlN UID GaN

SiC Substrate

Slide # 20

Charge and mobility vs. AlN thickness AlGaN/AlN/GaN HEMT


1600 1.8 1.6 1.4 1.2 1.0
Charge(Simulation) Charge(Experiment) Mobility(Experiment)

2DEG Density (10 cm-2)

1000

optimum thickness
0.0 0.5 1.0 1.5 2.0 2.5 3.0

800 600

Thickness of AlN (nm)

Theory predicts that ns increases with AlN thickness In real growth, thick AlN suffers by the relaxation. Above 0.5nm, charge saturates and mobility drops
Slide # 21

1200

Mobility (cm V s )

13

-1

-1

1400

Band Diagram
25 nm Al0.33Ga0.67N/ 1 nm AlN/GaN HEMT
3

25 nm Al0.33Ga0.67N/GaN HEMT

Thin AlN

Energy (eV)

Effective EC

Energy (eV)

- + - + - + +

2
AlGaN GaN

EC

-1 0 10 20 30 40 50

10

20

30

40

50

Thickness (nm)

Thickness (nm)
2

AlGaN t AlGaN
ns =
E
' c , eff

t AlGaN

q q + t AlN + d 0
q2

B +

Ec' ,eff
ns =

AlGaN t AlGaN

0
q

B +

0
q
2

EC, AlGaN

t AlGaN + d0

= EC , AlGaN +

AlN t AlN
Slide # 22

Hall data and DC I-V


Hall Data: Conventional undoped AlGaN/GaN ns = 1.1 1013 cm-2 = 1200 cm2/V s Undoped AlGaN/AlN/GaN: ns = 1.22 1013 cm-2 = 1520 cm2/V s Si-doped AlGaN /AlN/GaN: ns = 1.48 1013 cm-2 = 1500 cm2/V s
1000 800
VG = 2 V
VG = 1 V

ID (mA/mm)

600
gm = 200 mS/mm

400 200 0 0 2 4 6 8 10 12 14 16

VDS (V)

Mobility was improved with a slight increase of 2DEG Si doping increased 2DEG density while retaining high mobility
Slide # 23

Power Performance
Undoped AlGaN
35 40

Si-doped AlGaN
35 40
Pout Gain PAE 8.47 W/mm

Pout (dBm), Gain (dB)

25 20 15 10 5 0 0

30

Pout (dBm), Gain (dB)

30

Pout Gain PAE

8.1 W/mm

35

30 25 20 15 10 5 0 0

35 30

PAE (%)

20 15 10 5 5 10 15 20 25 0 30

20 15 10 5 5 10 15 20 25 0 30

Pin (dBm)

Pin (dBm)

On SiC substrate. SiN passivated. 8.1W/mm with a peak PAE of 23% was obtained at 8GHz at VD=50V, ID=130mA/mm from an undoped AlGaN barrier HEMT. 8.47W/mm with a PAE of 41% was obtained at 10GHz at 8GHz at VD=45V, ID=160mA/mm from a Si-doped barrier HEMT.

Slide # 24

PAE (%)

25

25

Effect of Si doping density


8
4
Electron, Hole Concentration (10 cm )

Nd/Polarization=1.2

Nd/Polarization=0.8

Nd/Polarization=0.5
6

Energy (eV)

2 0 -2 -4 0 50 100 150 200 250 300 350


0 50 100 150 200 250 300 350

parallel conduction holes


0

2 0

50 100 150 200 250 300 350

Thickness (nm)

Thickness (nm)

Thickness (nm)

ns = 1.7 1013 cm-2 npara = 0.3 1013 cm-2

ns = 1.36 1013 cm-2

ns = 1.04 1013 cm-2 ps = 0.18 1013 cm-2

Too much Si doping results in free electrons in graded layer, leading to parallel conduction Too little Si doping is not enough to remove holes ~80% compensation puts fermi level in the middle of bandgap
Slide # 25

18

-3

Design rules for AlGaN/GaN HEMTs: Materials perspective


Thickness of the barrier layer: affects 2DEG concentration and vertical gate field (which controls gate leakage current, VD, breakdown, and can also affect device degradation) Al composition of the barrier layer: affects 2DEG concentration and EC, which confines the 2DEG Nucleation and buffer layer: affects dislocation density, and surface morphology (both affect mobility, one by charged line scattering and other by interface roughness scattering) and parasitic conduction. Substrate for epitaxial growth: affects the heat conductivity and ultimate output power performance as well as defect density, and parasitics.
Slide # 26

Transistor fabrication layout


Submicron Ni/Au mushroom gate 3 defined by e-beam Ti/Al/Ti/Au ohmic contact annealed at 2 800C (0.3 to 0.6 -mm)
SEM image of a submicron mushroom gate

Air-bridge to connect 4 isolated source pads Cl2 based ECR 1 mesa isolation

SEM photo showing air-bridge over the gate metal (T-layout)

Slide # 27

Design rules for AlGaN/GaN HEMTs: Fabrication perspective


2 x 125 m U-gate 2 x 75 m T-gate

D S G S S

D S G

The gate footprint and the cross-sectional area and width controls the frequency response
Lg lower means fT goes up Cross-section and gate width control gate resistance (this is why mushroom gates are used)

The gate drain spacing as well as gate footprint determines the breakdown voltage
Lg lower means VBR down Gate-drain spacing up means VBR up

The geometry of the device also plays a role


The U-geometry device has 10 15 % lower gm, Idss due to self heating Slide # 28

Large periphery devices


Parallel fingers or fishbone layout for 12 x 125 m devices:
Parallel fingers Fishbone

Air bridges Larger periphery devices used for higher actual output power NOT power density (usually more than 1 mm gate finger width) The fabrication processes are complicated as this involves airbridging the source or the drain. Large periphery design issues: electrical and thermal
Slide # 29

Design issues for large periphery devices


Electrical issues:
The voltage drop along the gate length causes lower PAE Phase difference at the gate fingers reduce overall PAE Finite Ron reduces PAE. This becomes severe in presence of trapping as Ron increases

Thermal issues:
Device heating is a problem at higher output power, since power wasted is also larger The maximum possible output power depends on the conductivity of the substrates. SiC substrates are commonly used. Thinned sapphire substrates have also been used. The number of gate fingers as well as the gate finger pitch determine the maximum temperature rise in a device.
Slide # 30

DC characteristics of AlGaN/GaN HEMTs


10.3100 m devices (~35% Al)

The negative slope in the dc characteristics of sapphire is either due to heating or trapping The dc characteristics are better for HEMTs fabricated on SiC than on sapphire possibly because of reduced dislocation density and increased thermal conductivity The difference becomes more severe with scaling
Slide # 31

RF performance
Small signal
30

Large signal
60
Pout Gain PAE

Pout (dBm), Gain (dB)

30

h21 UPG

3.4W/mm 50

25 20 15 10 5

h21, UPG (dB)

20

30 20 10 0 5 10 15 20 0 25

10

10

100

f (GHz)

Pin (dBm)

ft of 22GHz and fmax of 40GHz were obtained from a 0.7um-gate-length HEMT at drain bias of 10V and drain current of 240mA/mm.

On sapphire substrate. No SiN passivation. 3.4W/mm with peak PAE 32% was obtained at 10GHz when VD=15V and ID=230mA/mm.

Slide # 32

PAE (%)

40

RF performance
Small signal
35
40 h21 UPG

Large signal
Pout (dBm), Gain (dB)
Pout Gain PAE 12W/mm

50 40

30 25 20

h21, UPG (dB)

44%

30 20

20 10 0

15 10 10 0 0 5 10 15 20

10

100

Frequency (GHz)

Pin (dBm)

ft of 21GHz and fmax of 39GHz were obtained from a 0.7um-gate-length HEMT at drain bias of 15V and drain current of 280mA/mm.

On SiC substrate 12W/mm with a peak PAE of 44% was obtained at 4GHz at VD=50V, ID=270mA/mm

Slide # 33

PAE (%)

30