International Journal of Research in Computer Engineering and Electronics.

VOL :2 ISSUE :6 (Dec 2013)

Page # 1

ISSN 2319-376X

Analysis of Ultra Wide Band Four stage Distributed Low Noise Amplifier in TSMC 0.18m Process
Habib Muhammad Nazir Ahmad [1], Mohammad Shafquatul Islam[2] , Arman Riaz Ochi [3]

Abstract
In communication circuitry detection of ultra weak signals at reception end is delicate. In order to have precision performance and acceptable gain in ultra wide band frequency range the noise performance and power consumption for low noise amplifier is significant. Among different techniques, this paper presents the simulated result for a distributed low noise amplifier with four stage amplification to ensure minimum noise figure as well as low power consumption. The simulation work is based on TSMC 0.18m process parameter. Index terms- Ultra Wide Band (UWB), Distributed circuit theory, Low Noise Amplifier (LNA), Distributed Low Noise Amplifier
(DLNA), Noise Figure (NF), Transmission Line (TL).

I INTRODUCTION In Ultra Wide Band (UWB) receiver's front end Low Noise Amplifier (LNA) must retain good performance (i.e., low noise figure, high gain, wide bandwidth, proper input-output isolation etc ). In UWB band (3.110.6 GHz), LNA receives small signals and when amplifies tend to maintain good signal to noise (SNR) ratio. Recent manuscripts have reported to achieve stable gain and low noise LNAs , several techniques have been proposed to accomplish required wide band matching at the input of LNA. There are four types of input matching circuits available which includes resistive, 1/gm method using common gate configuration, shunt feedback and wideband band pass termination method.
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[1] Habib Muhammad Nazir Ahmad is an Assistant Professor, Ameri can International University Bangladesh. [2] Mohammad Shafquatul Islam is Lecturer at American Intenaional University Bangladesh. [3] Arman Riaz Ochi is Lecturer at American Internaional University Bangladesh.

Though the resistive feedback architecture has acceptable wide band , they suffer from poor NF and gain [1] Common-gate low-noise amplifier (CG-LNA) [2] and CMOS resistive feedback amplifiers, designed for the UWB lower frequency band (i.e., 3 6GHz), exhibit poor performance in the UWB upper band due to the devices parasitic capacitances. The inductance of Ls in CG-LNA extends the bandwidth of the input matching. However, the Noise Figure of the CG LNA is considerably larger than that of the CMOS commonsource or cascode LNAs. Previously employed in common-source LNAs in [3] and [4], the gm-boosting technique was proposed by [5] to improve the NF performance of a UWB CG LNA. References [6] and [7] independently designed the first lumped LNA circuits for the UWB radio using a cascode circuit and highorder wideband band pass filters (BPF)s to provide wideband input matching. But an important point regarding NF's reported in [6] and [7] were that it's not flat across the 7.5 GHz bandwidth. And in band NF of LNA [6] mismatch related with frequency dependent resistance (50 ) found from the gate terminal of transistor.

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A distributed method with multiple gain stages along actual or artificial transmission lines (TLs) can show wideband characteristics. In distributed circuits the source impedance is matched to the termination impedance. In the process the input and output capacitances of gain stages will be absorbed to the input and output TLs.

F=

=1+

(1)

Zin

2. DISTRIBUTED CIRCUITS THEORY

The following block diagram (figure-1) shows a Distributed Amplifier consisting of TLs and gain stages where gain stages can be a common source amplifier stage. TLs can be realized as cascaded LC circuits. The circuit Bandwidth can be determined by the cut off frequency of TLs as in frequency domain the parasitic capacitance of transistor's are absorbed into the con

RG

Zin

LS

(a)

(b)
RL L1 C1 LG

RF

Zin

Zin RS

L2

C2

LS

(c)

(d)

Fig. 2: Different approach to calculate input impedance

AV
1

out

C A

C A

V
in

C : Input Parasitic Capacitance of gain stage plus external capacitances i :

Fig. 1: Capacitance estimation stants of TLs [8]. Though distributed circuits consume more power than conventional lumped circuits, the architecture is highly manageable in terms of technology scaling. For Distributed circuit with N stages the power consumption will be N times that of a single stage amplifier. In distributed circuits the source impedance is matched to the termination impedance. Considering the gm stage with resistive matching shown in Fig. 2 (a). The lower bound noise factor F of the gm stage with bias current of I is

If the gm stage consumes N.I just to match the current consumption of an N stage distributed amplifier, then gm increases proportional to N, hence the device noise contribution is reduced by factor of 1/N. Although the noise contribution from the RG remains unchanged, no matter how much power is burned in the gm stage. Now considering an N stage distributed amplifier comprising N identical gm stages, where these stages are distributed along the input/output TLs. The input matching network is again resistive realized by the resistive termination of the TLs. However, in distributed circuits the input/output matching is intrinsically provided by the use of transmission lines. The noise from RS travels toward the output from each path and reaches coherently to the output just similar to the main desired signal. Therefore, the total output noise power due to the source resistance is: Total Output Noise due to Source Resistance =

But the noise from the resistive matching termination reaches at the output form N paths with different delays. As a result, they all become uncorrelated at the

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output. One can thus easily calculate the total output noise power due to the resistive termination, which is the sum of the noise powers contributed by each path. i.e., Total Output Noise due to Gate Resistance = Thermal noise sources from all gm stages will add up at the output portion and can be calculated by the following: Total Output Noise due to gm = NkT gd0 Therefore at lower bound the Noise Factor of an N stage distributed amplifier can be calculated FN = =1+ ( +

stage within each cascode cell. Both ZG and ZG stay constant over a wide range of frequencies. In this design, both ZG and ZD are chosen to match the 50 source/load resistances. The gate and drain TLs boost the BW by absorbing the input and output parasitic capacitances of each cell. These TLs do not, however, affect the frequency rolloff due to large parasitic capacitance seen at the internal node of a conventional cascode cell, where the drain of the common-source transistor is shortcircuited to the gate of the common-gate transistor. The proposed DLNA topology is based on a uniform distributed architecture, therefore, LCk = LCr = LC, for all k r. In the absence of LC, the circuit bandwidth is primarily limited by the pole associated to the internal node of the cascode cells whose value is -1 where Co,cs is the output capacitance of the common-source transistor, Ci,cg is the input capacitance of the common-gate transistor, and gm,cg is the transconductance of the common-gate transistor in each cascode cell.

For Distributed circuit, increasing number of stages lead to more power consumption but it will reduce the noise contribution of the active device as well as noise contribution of the matching resistance hence improve the total noise factor. In fact under the same amount of power consumption, Distributed Amplifier exhibits lower noise factor than lumped amplifiers. The conventional DA is potentially unstable. In addition, any voltage/current variation in either gate or drain TLs terminations will be coupled to the other TL through CGD of the common-source transistor. A DA with cascode cell can mitigate these deleterious effects [8,9,10]. However, common-gate transistors of each cascode cell begin to contribute significant noise to the output at high frequencies, thereby degrading the circuits NF. Indicated in Fig. 3 is the schematic of the proposed Nstage UWB DLNA comprising uniform gate and drain artificial LC TLs and identical cascode cells. Each cell employs a cascode configuration to guarantee stability across the entire bandwidth by providing isolation between the cells input and output terminals. The inter stage inductors of the gate (drain) TL along with gate (drain) parasitic capacitances of transistors Mak1 (Mak2), 1 k N, constitute cascaded LC ladder circuits with characteristic impedance of where Ci,cs is the input capacitance of the common-source stage and Co,cg is the output capacitance of the common-gate

Fig. 3: Schematic of 4 stage DLNA

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Figures 4 (a) and (b) show the AC equivalent and high-frequency small-signal model of the k-th cascode cell with BW-enhancing inductor LC, seen from the internal node of the cascode cell. The high-frequency model of Fig. 1 is used to obtain the transfer function Vdk (s)/Vgk (s)

To increase the bandwidth while avoiding large frequency peaking, the transfer function Vdk (s)/Vgk (s) should hold specific characteristics including: 1. The numerator should be in the form of a maximally flat polynomial, implying that the damping factor z is 1/2 2. The denominator should exhibit small peaking in frequency domain, which leads to additional BW increase. A damping factor of 1/2 (i.e., p = 0.5) results in a peaking of 1.25dB. Additionally, the parallel resonant frequency n,p becomes equal to the 0-dB frequency, where the magnitude response of the transfer function crosses the 0dB axis after experiencing 1.25 dB peaking By choosing n,p = n,z , the 0-dB cutoff frequency of the transfer function Vdk (s)/Vgk (s) is boosted to n,p. Moreover, it results in a frequency peaking of less than 10%, This criterion along with the above design guidelines 1 and 2 provide sufficient information to calculate the inductance LC and the new 3-dB bandwidth as follows:

Fig. 4: (a) AC equivalent of BW-enhanced cascode cell and (b) small signal model

LC makes the equivalent impedance Zo,cs , seen looking up from Vdk and expressed as 2 Zo,cs(s) = (LCCi,cgs +gm,cg LCs+1)/(gm,cg+Ci,cgs), behave inductively at high frequencies. This impedance effectively determines the series resonant frequency n,z = (LCCi,cg)1/2 of the transfer function Vdk (s)/Vgk (s) of the k-th cell, and is in parallel with the output impedance of common-source transistor Mak1 which is capacitive. Using the circuit model of Fig. 4 (b), the transfer function Vdk (s)/Vgk (s) of the k-th cell is readily obtained as:

The bias for cascode transistors in all constituent cells is provided by a single current mirror, as shown in Fig. 3 The artificial LC gate line provides the wideband input impedance matching, thereby obviating the need for inductive degeneration for each cascade cell of the DLNA circuit. TL inductors are designed such that the same characteristic impedance of 50 is obtained at each tap -point of the gate and drain lines so as to maximize the power transfer toward the load termination. The gate lines inductor LG is larger than the drain lines inductor LD, because the input capacitance is larger than the output capacitance of each cell.

for 1

The parallel resonant frequency can be found as:

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3.NOISE ANALYSIS
The dominant intrinsic noise sources in the DLNA are: (1) thermal noise from the input source impedance (RS = ZG; ZG is the gate lines characteristic impedance defined earlier), (2) thermal noise from the gate and drain terminations, and (3) dominant noise sources associated with each MOS transistor including the channel thermal noise, gate-induced noise, and flicker noise. The noise analysis of partially correlated channel thermal noise Id,k and gate-induced noise Ig,k of the kth stage, the gate-induced noise is first decomposed into its correlated and uncorrelated components [8, 11, 12]; i.e., Fig. 5: Forward Propagation of dominant device noise sources

, where kB is the Boltzmanns constant (1.380651023 Joule/K), T is the absolute temperature, gg,k = 2C2GS,k/gm,k for 1 k N, is a technologydependent constant, and c is the correlation coefficient [defined as whose value for long-channel devices is approximately j0.395 [8, 11]. Moreover, gm,k = gm,csk for 1 k N The noise contribution of MOSFETs of the k-th stage to the output is calculated by accounting for both forward and backward propagations of these noise sources. In calculating the noise contribution of MOSFETs, the TLs are assumed to have identical propagation constants. The DLNAs power gain with the same input and output matching impedances will be maximized if the LC TLs have identical propagation constants

Fig. 6: Backward Propagation of dominant MOSFET noise sources Simple calculations reveal that the noise contributions of the source impedance Rs = ZG, the gate-line termination ZG, and the drain-line termination ZD to the output are calculated as follows (see [13]):
Source impedance

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376X VOL :2 ISSUE :6 (Dec 2013)
Gate termination

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= =

bandwidth, i.e.

Drain termination

where Noise contributions of various noise sources to the output noise power of the DLNA were calculated the definition of the spot NF yields NFtot = NFHF + , where NFHF = 1 + a=N b=N X-3dB = -3dB -3dB A0 = DC gain -3dB = -3dB cutoff frequency of the amplifier (rad/sec) max = MOSFET's maximum frequency of oscillation (rad/sec)

And NFHF denotes the high-frequency NF and ZT = ZG = ZD. The flicker noise corner frequency, fcorner , is simply determined by equating the mid-range frequency value of NFHF with the low-frequency value of NFtot , resulting in

where Ro,cg denotes the output resistance of the common gate stage in each cascode cell.

1. For a flat magnitude response across the UWB band, set f3dB = 13GHz. TheTLs cutoff frequency, fc, defined as: fc = 2/[ ] = 2/[ ] is calculated so as to ensure that N l , l Z. To achieve maximum gain for frequencies up to the UWB upper corner frequency, we set a = 0.70 and b = 0.30. Moreover, N = Nopt, and Nopt is obtained for minimum NF. 2. The maximum bias current for which the MOS transistors of each cell remain in saturation is calculated for the bias circuit used This current is readily calculated as ID,max = VT HN/Nopt ZT . 3. We calculate the maximum DC gain, A0. 4. Equation in [15] gives the DC gain of a conventional distributed amplifier as

, where K1/ f is the process dependent flicker noise constant with typical values less than 1026V2F [14] Differentiating the circuit NF with respect to N yields

As an approximation, the noise contribution of the flicker noise can be neglected, which simplifies

The design optimization procedure utilizes the GBW expression obtained from [23] in terms of the 3dB

This equation holds for the DLNA of Fig. 4 with identically matched transistors Mak2 and Mak1 for the each cascode cell. All the parameters are expressed with respect to gate aspect-ratio of transistors, W/L.

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gate lines inductance is chosen to be 912 pH and the gate input capacitance is 270 fF resulting in a line cutoff frequency of 20.28 GHz VDD = 1.8V and the overall current consumption of 15.45 mA So the total Power consumption 27.81 mW. 5. Using step 4, calculate the W/L. This W/L results in minimum NF and maximum gain. 6. Obtain minimum NF.

4.SIMULATION RESULTS
TSMC 0.18 RF CMOS technology was used to design the DLNA. Optimum W/L ratio is used as 215 m / 0.18 m . The values of parameters = 5 , Fig. 7: Gain of 4 stage DLNA

5.CONCLUSION
Fig. 8: Noise Figure of 4-stage DLNA The Stage can be increased to lower the noise figure and more tweaking in inductance and capacitance can ovide possible improvement at gain and decrement of power dissipation. Reference [8] [16] [17] [18] This Design BW (GHz) 0.1-23 1-25 0.5-14 0-11 3-11 S21 (dB) 14.5 0.9 7.8 1.3 10.6 10 12.5 0.5 NF (dB) 5 4.8-7 3.5-5.7 3.2-6 2.7-4.1 Power (mW) 54 54 52 100 27.81 mW

Table I : Performance Comparison of LNA circuits:

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VOL :2 ISSUE :6 (Dec 2013)

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