What can you do to save power ?? This is a generic question.

In CMOS design following are the main components of power. !ea"age #ower Components. $ #ower caused %y current flow that occurs regardless of voltage transitions& mostly from su%'threshold current of (off) transistors. Scales e*ponentially with voltage and temperature. !ea"age #ower reduction technique. $ This is usually trade off with performance. +ou can use long channel devices to reduce lea"age. ,igh threshold voltage -.t/ transistors are less lea"y. 0oth degrade performance of the device. $ 1ownsi2e devices to reduce lea"age. ,urts performance. $ #rocess techniques31ielectric properties help reduce lea"age. 1ynamic #ower components $ This is the the power dissipation caused %y switching signals. $ #ower 4 C5.675f $ More accurately 1ynamic #ower 4 8ctivity 9actor 5 C 5 .67 5 f : Short Circuit #ower : ;litch #ower. $ Sometimes a more effective measure of dynamic power is dynamic capacitance. $ 1ynamic Capacitance 4 <-8ctivity factor 5 C/3net 1ynamic power reduction techniques - This is essentially minimi2e = 8ctivity 9actor 5 C 5 .67 5 f :Short Circuit #ower : ;litch #ower. / $ >educe 8ctivity 9actor= Mainly %y ;ating Cloc"s ? 1ata. 1on@t let them toggle when they@re not needed to %e active. This is sometimes called toggle filtering as well. $ >educe Capacitance = >educe capacitance on high activity nodes. 1o topological optimi2ation to minimi2e wire length. Increase spacing of the wires. In general you want to shoot for ABC wire capacitance and ABC device capacitance - gate : diffusion / $ Short circuit and ;litch power are generally marginal in good design. +ou want to ma"e sure slew rates are good and avoid other situation that cause short circuit current. $ 1ownsi2e devices where you can afford to reduce device capacitance. Dna%le downsi2ing. Static #ower components. $ This is the power dissipation %ecause of the %ias current in IO or 8nalog circuits. It@s independent of frequency and it@s not the lea"age power. Static #ower reduction techniques. $ 8nalog techniques to address %ias current. Why is E8E1 preferred over EO> in CMOS design3fa%rication ? 8ns = E8E1s are faster than EO> %ecause F E8E1 has EMOS devices in series whereas EO> has #MOS devices in series. F EMOS devices are faster %ecause of higher mo%ility of electrons. Side effect of this is that rising and falling delays of EO> are s"ewed %ecause slower #MOS in

series ma"es rising transition much slower and faster EMOS in parallel ma"es falling transition much faster. F Where E8E1 has %alanced rise and fall delays. 0ecause of stac"a%ility of EMOSes in E8E1 structure lea"age can %e controlled %y adding e*tra device in pull down stac".

What is the Difference Between New() and New[] ??? Ans : > You may have noticed that this new() function oo!s a ot i!e the new[] o"erator# used to set the si$e of dynamic arrays% > &hey 'oth a ocate memory and initia i$e va ues% &he 'i( difference is that the new() function is ca ed to construct a sin( e o')ect# whereas the new[] o"erator is 'ui din( an array with mu ti" e e ements% > new() can ta!e ar(uments for settin( o')ect va ues# whereas new[] on y ta!es a sin( e va ue for the num'er of e ements in the array% What is setu" time ? > *or any se+uentia e ement e%(% atch or f i",f o"# data needs to 'e sta' e when c oc! ca"ture ed(e is active% > Actua y data needs to 'e sta' e for a certain time 'efore c oc! ca"ture ed(e activates# 'ecause if data is chan(in( near the c oc!,ca"ture ed(e# se+uentia e ement ( atch or f i",f o") can (et into a metasta' e state and can ca"ture unintended va ue at the out"ut% > &he time re+uirement that data 'e sta(e for 'efore the c oc! ca"ture ed(e activates is ca ed the setu" time of that se+uentia e ement% What is ho d time ? > *or any se+uentia e ement e%(% atch or f i",f o"# data needs to 'e he d sta' e when c oc!,ca"ture ed(e is active%

> Actua y data needs to 'e he d sta' e for a certain time after c oc!,ca"ture ed(e deactivates# 'ecause if data is chan(in( near the c oc!,ca"ture ed(e# se+uentia e ement can (et into a metasta' e state and can ca"ture unintended va ue at the out"ut% > &his time re+uirement that data needs to 'e he d sta' e for after the c oc! ca"ture,ed(e deactivates is ca ed ho d time re+uirement for that se+uentia %

Are c oc! domain crossin( issues detected 'y -&A too ? > No# c oc! Domain crossin( issues are not detected 'y -tatic &imin( Ana ysis too % As mentioned ear ier# too sim" y tries to find out the worst case setu" and ho d chec!s 'etween aunch and ca"ture ed(e% Desi(ner has to desi(n for c oc! domain crossin(s% .ow to avoid metasta'i ity ? > /f we ensure that in"ut data meets setu" and ho d re+uirements# we can (uarantee that we avoid metasta'i ity% > -ometimes it0s not "ossi' e to (uarantee to meet setu"1 ho d re+uirements# es"ecia y (eneratin( si(na is comin( from a different c oc! domain com"ared to sam" in( c oc!% > /n such cases# what we do is " ace 'ac! to 'ac! f i",f o"s and a ocate e2tra timin( cyc es of c oc!s to sam" e the data% -uch a series of 'ac! to 'ac! f o"s is ca ed a metasta'i ity hardened f o"% > 3ssentia y what we0re doin( is that we a ow first f i",f o" to "otentia y (o metasta' e# durin( first sam" in( c oc! cyc e and we (ive first f o" a fu sam" in(

c oc! cyc e to recover from metasta'i ity% > /f within first cyc e first f o" recovers to correct va ue# we ca"ture correct va ue at out"ut second f i",f o" at 'e((in( of second c oc! cyc e% > /f first f o" recovers to wron( sta(e we0ve to wait for one more cyc e i%e% 'e(innin( of 4rd cyc e of sam" in( c oc! to ca"ture the correct va ue% > -ometimes it0s "ossi' e that first f o" ta!es on(er than one sam" in( c oc! cyc e to recover to sta' e va ue# in which case 4 f i",f o"s in series can 'e used% > 5ore f o"s in series reduces the fai ure in ca"turin( the correct va ue at out"ut at e2"ense of more num'er of cyc es% What can you do to save "ower ?? &his is a (eneric +uestion% /n 657- desi(n fo owin( are the main com"onents of "ower% 8 9ea!a(e :ower 6om"onents% ; :ower caused 'y current f ow that occurs re(ard ess of vo ta(e transitions# most y from su',thresho d current of <off= transistors% -ca es e2"onentia y with vo ta(e and tem"erature% 8 9ea!a(e :ower reduction techni+ue% ; &his is usua y trade off with "erformance% You can use on( channe devices to reduce ea!a(e% .i(h thresho d vo ta(e (>t) transistors are ess ea!y% Both de(rade "erformance of the device% ; Downsi$e devices to reduce ea!a(e% .urts "erformance% ; :rocess techni+ues1Die ectric "ro"erties he " reduce ea!a(e% 8 Dynamic :ower com"onents ; &his is the the "ower dissi"ation caused 'y switchin( si(na s% ; :ower ? 6@>AB@f ; 5ore accurate y Dynamic :ower ? Activity *actor @ 6 @ >AB @ f C -hort 6ircuit :ower C D itch :ower% ; -ometimes a more effective measure of dynamic "ower is dynamic ca"acitance% ; Dynamic 6a"acitance ? E(Activity factor @ 6)1net

8 Dynamic "ower reduction techni+ues ( &his is essentia y minimi$e : Activity *actor @ 6 @ >AB @ f C-hort 6ircuit :ower C D itch :ower% ) ; Feduce Activity *actor: 5ain y 'y Datin( 6 oc!s G Data% Don0t et them to(( e when they0re not needed to 'e active% &his is sometimes ca ed to(( e fi terin( as we % ; Feduce 6a"acitance : Feduce ca"acitance on hi(h activity nodes% Do to"o o(ica o"timi$ation to minimi$e wire en(th% /ncrease s"acin( of the wires% /n (enera you want to shoot for HIJ wire ca"acitance and HIJ device ca"acitance ( (ate C diffusion ) ; -hort circuit and D itch "ower are (enera y mar(ina in (ood desi(n% You want to ma!e sure s ew rates are (ood and avoid other situation that cause short circuit current% ; Downsi$e devices where you can afford to reduce device ca"acitance% 3na' e downsi$in(% 8 -tatic :ower com"onents% ; &his is the "ower dissi"ation 'ecause of the 'ias current in /7 or Ana o( circuits% /t0s inde"endent of fre+uency and it0s not the ea!a(e "ower% 8 -tatic :ower reduction techni+ues% ; Ana o( techni+ues to address 'ias current%
What does a delay of a cell3gate depend upon ? 8ns = It mainly depends upon the input pin slope3slew rate and output load. Which layers are %est used for routing? Why? ,igher layers are %est used for routing. 0ecause higher layers have less >C delay per micron of length. This is %ecause higher layers have wider wider wires& which are more capacitive& %ut have much less resistance& resulting in overall less >C delay. Wor"ing of a 9I9O ?? F 9I9O is used for high throughput asynchronous data transfer. F When you@re sending data from one domain to another domain and if high performance is required& you can not Gust get away with simple synchroni2er- Met...See More

,ow 0loc"ing and non'%loc"ing wor"s ?? initial %egin *4B y H4 I 24J y H4 K end 9or the a%ove mentioned case& the e*ecution order still follows-http=33goo.gl3hiLCDt/ the order in which statements appear. M/ %loc"ing statement N* 4 BO is e*ecuted in a single go. 7/ >,S of non%loc"ing assignment Ny H4 IO is evaluated and !,S update is scheduled. I/ %loc"ing assignment N2 4 JO is e*ecuted. P/ >,S of non%loc"ing assignment Ny H4 KO is evaluated and !,S update is scheduled. A/ !,S update from the second non%loc"ing assignment is carried out& Ny@ is I now. K/ !,S update from the last non%loc"ing assignment is carried out& Ny@ is K now. ,ow 0loc"ing and non'%loc"ing assignment wor"s ??? initial %egin *4M y H4 P 24L p H4 Q end 9or the a%ove mentioned case& the e*ecution order still follows-http=33goo.gl3hiLCDt/ the order in which statements appear. M/ %loc"ing statement N* 4 MO is e*ecuted in a single go. 7/ >,S of non%loc"ing assignment Ny H4 PO is evaluated and !,S update is scheduled. I/ %loc"ing assignment N2 4 LO is e*ecuted. P/ >,S of non%loc"ing assignment Np H4 QO is evaluated and !,S update is scheduled. A/ !,S update from the second non%loc"ing assignment is carried out. K/ !,S update from the last non%loc"ing assignment is carried out. 8s per standard the event queue is logically segmented into four different regions. F 9or sa"e of simplicity we@re showing the three main event queues. F The (Inactive) event queue has %een omitted as RB delay events that it deals with is not a recommended guideline.

'F N8ctive@ event queue = F 8ccording to the IDDD .erilog spec& events can %e scheduled to any of the event queues& %ut events can %e removed only from the (active) event queue. 8s shown in the image& the Nactive@ event queue holds %loc"ing assignments& continuous assignments. primitive IO updates and Swrite commands. F Within (active) queue all events have same priority& which is why they can get e*ecuted in any order and is the source of nondeterminism in .erilog. 'F E08 >egion -Eon'%loc"ing assignment/ = F There is a separate queue for the !,S update for the non%loc"ing assignments. 8s you can see that !,S updates queue is ta"en up after (active) events have %een e*hausted& %ut !,S updates for the non%loc"ing assignments could re'trigger active events. 'F #ostpone region = F!astly once the looping through the (active) and non %loc"ing !,S update queue has settled down and finished& the (postponed) queue is ta"en up where Sstro%e and Smonitor commands are e*ecuted& again without any particular preference of order. 8t the end simulation time is incremented and whole cycle repeats. RverilogTe*ecutionTorder Rvlsinow More Conceptual Uuestion on 0loc"ing and Eon'%loc"ing .!SI EOW http=33goo.gl3f8J9*L

We could %uild a latch from a single MVW quite easily if we feed%ac" the output to one of the MVW inputs. The figure %elow will ma"e everything clearer. Eotice that we could easily construct a latch which is transparent while its cloc" input is high or low %y Gust changing the input the feed%ac" wire is connected to. We then use two latches& one transparent low the other transparent high to construct a flipflop. Rmu* Rlatch Rvlsinow

1esign of EOT& 8E1& O> gate using 7=M MVW. Rnot Rand Ror Rmu* Rvlsinow

Tcl .s #erl 'F use tcl scripts to write synthesis script. 'F use perl to analysis the simulation result and synthesis log file. 'F use tcl in front'end 'F use perl in %ac"'end 'F Tcl are used in the within the tools 'F perl is used to automate the design flow What is 1ifference %etween assertion and if statement ??? 8ES = 8n assertion is %asically a statement that something must %e true& similar to the if statement. The difference is that an if statement does not assert that an e*pression is true& it simply chec"s that it is true& e.g.= if -8 44 0/ ... 33 Simply chec"s if 8 equals 0 assert -8 44 0/X 33 8sserts that 8 equals 0X if not& an error is generated ,ow to 9i* setup and hold timing violations ??? The digital circuit is shown with logic delay -dlyI/ and two cloc" %uffer delays -dlyM& dly7/. ,ow will you fi* setup timing violations occurring at pin 0? 8nswer= Vse the following formula= Tc7q : TdlyI H4 Ts" : Tp ' Tsu Since Tp - cloc" frequency is fi*ed M3Tp 4 f /& Tc7q -cloc" to U/ and Tsu -setup time/ are fi*ed& the setup timing violations are caused %y TdlyI. In order to fi* the setup violations& we can reduce TdlyI. ,ow will you fi* the hold violations occuring at pin 0? 8nswer= Vse the following formula= Tc7q : TdlyI F4 Ts" : Thd Tc7q : TdlyI ' Ts" F4 Thd Since Tc7q -cloc" to U/ and Thd -hold time/ are fi*ed& the hold time violations are caused %y the TdlyI. We can increase the TdlyI. 9or e*ample& add %uffer to the path. We should not mess up with the cloc" s"ew. It would affect too many paths. RsetupTtimeTviolation RholdTtimeTviolation

More 8SIC interview question with answer = http=33goo.gl3f8J9*L

-tatic "ower >s Dynamic :ower : -tatic "ower is "ower dissi"ation for dc su"" y on y% to ca cu ate is )ust usin( the e+uation :?/> (/? /DDK #>?>DD ) usin( dc o"eratin( "oint ana ysis you cou d o'tain those va ue% %%%-ee 5ore

-tatic "ower >s Dynamic :ower : -tatic "ower is "ower dissi"ation for dc su"" y on y% to ca cu ate is )ust usin( the e+uation :?/> (/? /DDK #>?>DD ) usin( dc o"eratin( "oint ana ysis you cou d o'tain those va ue% %%%-ee 5ore

-tatic "ower >s Dynamic :ower : -tatic "ower is "ower dissi"ation for dc su"" y on y% to ca cu ate is )ust usin( the e+uation :?/> (/? /DDK #>?>DD ) usin( dc o"eratin( "oint ana ysis you cou d o'tain those va ue% %%%-ee 5ore

-tatic "ower >s Dynamic :ower : -tatic "ower is "ower dissi"ation for dc su"" y on y% to ca cu ate is )ust usin( the e+uation :?/> (/? /DDK #>?>DD ) usin( dc o"eratin( "oint ana ysis you cou d o'tain those va ue% %%%-ee 5ore

-tatic "ower >s Dynamic :ower : -tatic "ower is "ower dissi"ation for dc su"" y on y% to ca cu ate is )ust usin( the e+uation :?/> (/? /DDK #>?>DD ) usin( dc o"eratin( "oint ana ysis you cou d o'tain those va ue% %%%-ee 5ore

-tatic "ower >s Dynamic :ower : -tatic "ower is "ower dissi"ation for dc su"" y on y% to ca cu ate is )ust usin( the e+uation :?/> (/? /DDK #>?>DD ) usin( dc o"eratin( "oint ana ysis you cou d o'tain those va ue% %%%-ee 5ore

-tatic "ower >s Dynamic :ower : -tatic "ower is "ower dissi"ation for dc su"" y on y% to ca cu ate is )ust usin( the e+uation :?/> (/? /DDK #>?>DD ) usin( dc o"eratin( "oint ana ysis you cou d o'tain those va ue% %%%-ee 5ore

-tatic "ower >s Dynamic :ower : -tatic "ower is "ower dissi"ation for dc su"" y on y% to ca cu ate is )ust usin( the e+uation :?/> (/? /DDK #>?>DD ) usin( dc o"eratin( "oint ana ysis you cou d o'tain those va ue% %%%-ee 5ore

-tatic "ower >s Dynamic :ower : -tatic "ower is "ower dissi"ation for dc su"" y on y% to ca cu ate is )ust usin( the e+uation :?/> (/? /DDK #>?>DD ) usin( dc o"eratin( "oint ana ysis you cou d o'tain those va ue% %%%-ee 5ore
Static power .s 1ynamic #ower = Static power is power dissipation for dc supply only. to calculate is Gust using the equation #4I. -I4 I11U &.4.11 / using dc operating point analysis you could o%tain those value. ...See More

8SIC .s 9#;8 =' M.8n 8SIC is a unique type of integrated circuit meant for a specific application while an 9#;8 is

a reprogramma%le integrated circuit. 7.8n 8SIC can no longer %e altered once created while an 9#;8 can. I.It is common practice to design and test on an 9#;8 %efore implementing on an 8SIC. P.8n 8SIC wastes very little material compared to an 9#;8 and the recurring costs are low. A.9#;8 is %etter than an 8SIC when %uilding low volume production circuits. 8dvantages of One ,ot encoding = F State decoding is simplified& since the state %its themselves can %e used directly to chec" whether the 9SM is in a particular state or not. ,ence additional logic is not required for decoding& this is e*tremely advantageous when implementing a %ig 9SM. F !ow switching activity& hence resulting low power consumption& and less prone to glitches. F Modifying a design is easier. 8dding or deleting a state and changing state transition equations -com%inational logic present in 9SM/ can %e done without affecting the rest of the design. F 9aster than other encoding techniques. Speed is independent of num%er of states& and depends only on the num%er of transitions into a particular state. F 9inding the critical path of the design is easier -static timing analysis/. F One'hot encoding is particularly advantageous for 9#;8 implementations. If a %ig 9SM design is implemented using 9#;8& regular encoding li"e %inary& gray& etc will use fewer flops for the state vector than one'hot encoding& %ut additional logic %loc"s will %e required to encode and decode the state. 0ut in 9#;8 each logic %loc" contains one or more flip'flops . hence due to presence of encoding and decoding more logics %loc" will %e used %y regular encoding 9SM than one'hot encoding 9SM. 8dvantages of 8synchronous >eset= F,igh speeds can %e achieved& as the data path is independent of reset signal. F8nother advantage favoring asynchronous resets is that the circuit can %e reset with or without a cloc" present. F8s in synchronous reset& no wor" around is required for logic synthesis.

What is 8synchronous >eset ??? 8n asynchronous reset will affect or reset the state of the flip'flop asynchronously i.e. no matter what the cloc" signal is. This is considered as high priority signal and system reset happens as soon as the reset assertion is detected.

8dvantages Synchronous >eset = FThe advantage to this type of topology is that the reset presented to all functional flip'flops is fully synchronous to the cloc" and will always meet the >DSDT >DCO.D>+ TIMD. FSynchronous reset logic will synthesi2e to smaller flip'flops& particularly if the reset is gated with the logic generating the d'input. 0ut in such a case& the com%inational logic gate count grows& so the overall gate count savings may not %e that significant. FSynchronous resets provide some filtering for the reset signal such that it is not effected %y glitches& unless they occur right at the cloc" edge. F8 synchronous reset is recommended for some types of designs where the reset is generated %y a set of internal conditions. 8s the cloc" will filter the logic equation glitches %etween cloc" edges.

What is Synchronous >eset ??? 8 synchronous reset signal will only affect or reset the state of the flip'flop on the active edge of the cloc". The reset signal is applied as is any other input to the state machine. ,ow to avoid the pitfalls of Metasta%ility ??? 1esigners use certain synchroni2ation schemes to ensure correct e*change of information %etween asynchronous cloc" domains. One such common scheme is depicted %elow& where a synchroni2ed control signal is used to ena%le the loading of the data %eing sent from the transmitting domain to the receiving domain. 8 Ncontrol@ signal is one that is synchroni2ed directly %y a multi'flop synchroni2er. 8 Ndata@ signal is one that is not directly synchroni2ed %ut whose synchroni2ation is controlled %y a corresponding Ncontrol@ signal. The conditions that need to %e met %y the control and data signals in such a scheme are outlined %elow. The two conditions highlighted in ;reen are candidates for formal analysis to verify. Rmetasta%ility RmultiTflopTsynchroni2er ;et Connected with us = http=33goo.gl3f8J9*L

MDT8ST80I!IT+ =' Whenever a signal changes too close to the cloc" edge it is %eing sampled on& the captured value is non'deterministic due to setup3hold violations. This phenomenon is called Metasta%ility and without proper prevention and verification& metasta%ility propagation could cause serious design errors. 9or synchronous designs& this is not a maGor issue as Static Timing 8nalysis -ST8/ tools can flag these issues with setup3hold chec"s. ,owever& metasta%ility is an unavoida%le issue for signals crossing asynchronous cloc" domains as cloc" domain crossings are not timed %y ST8 tools. 1ue to the asynchronous nature of the transmit and receive cloc"s& it is possi%le that the transmit data might change within the setup and hold window of the receive cloc"& hence resulting in an unpredicta%le value and delay at the output of the flop.

"eyword = RMetasta%ility Rsetupviolations Rholdviolations RST8