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TheICMarket
Thesemiconductorindustryisapproaching$300B/yrinsales
Military 2%
Industrial 8%
Transportation T t ti 8%
CourtesyofDr.BillFlounders,UCBerkeleyMicrolab
In1965,GordonMoorepredictedthatthenumberoftransistors thatcanbeintegratedonadiewoulddoubleevery18to14months i.e.,growexponentiallywithtime Amazingvisionary milliontransistor/chipbarrierwascrossedinthe 1980s. RelativesizesofICsingraph 2300transistors,1MHzclock(Intel4004) 1971 42Million,2GHzclock(IntelP4) 2001 140Milliontransistor(HPPA8500)
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Source:Intelwebpage(www.intel.com)
InternationalTechnologyRoadmapforSemiconductors
LimitsofMooresLaw?
Growthexpecteduntil30nmgatelength(currently:180nm) sizehalvedevery18mos. mos reachedin 2001+1.5log2((180/30)2)=2009 whatthen? Paradigmshiftneededinfabricationprocess
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ICFabrication
Goal:Massfabrication(i.e. simultaneousfabrication) ofmanyICchips chips oneachwafer,eachcontaining millionsorbillionsoftransistors Approach:Formthinfilmsofsemiconductors,metals, andinsulatorsoveranentirewafer,andpatterneach layerwithaprocessmuchlikeprinting(lithography).
Planarprocessingconsistsofasequenceof additiveandsubtractivestepswithlateralpatterning
oxidation deposition p ion implantation etching lithography
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PlanarProcessing g
(patentedbyFairchildSemiconductorin1959:J.A.Hoerni,USPatent3,064,167)
OverviewofICProcessSteps
Test E i Epitaxy BareSilicon Wafer Processed Wafer
CDSEM Metrology
Defect Detection
Etch CourtesyofDr.BillFlounders,UCBerkeleyMicrolab
Lithography 15
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RecurringCosts
Whilethecostofproducingasingletransistorhasdroppedexponentiallyoverthepastfew decades,thebasiccostequationhasntchanged.Costofacircuitisdependentuponthe chiparea.
YieldExample
Example
wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2, = 3 (measure of manufacturing process complexity) 252 dies/wafer (remember, wafers round & dies square) die yield of 16% 252 x 16% = only 40 dies/wafer die yield !
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SystemSpecification
Functional Simulation Specifications
Function/Archt.design
Logic Simulation Behavioral Representation
LogicSynthesis
Circuit Analysis Structural Representation
CircuitDesign
Extractionand Verification Structural Representation
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(Continued)
Extractionand Verification
Structural Representation
PhysicalSynhtesis
Physical Representation
Fabrication
Packaging
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