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IntroductiontoICTechnology & Applications

EE405 Dr.Rizwan Akram

TheICMarket
Thesemiconductorindustryisapproaching$300B/yrinsales

Military 2%

Communications 24% Computers 42%

Industrial 8%

Transportation T t ti 8%
CourtesyofDr.BillFlounders,UCBerkeleyMicrolab

ConsumerEl C Electronics t i 16%


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In1965,GordonMoorepredictedthatthenumberoftransistors thatcanbeintegratedonadiewoulddoubleevery18to14months i.e.,growexponentiallywithtime Amazingvisionary milliontransistor/chipbarrierwascrossedinthe 1980s. RelativesizesofICsingraph 2300transistors,1MHzclock(Intel4004) 1971 42Million,2GHzclock(IntelP4) 2001 140Milliontransistor(HPPA8500)

100 GAT TE LENGTH (nm)

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LOW POW ER H IG H P E R F O R M A N C E 1 2000 2005 2010 YEAR 2015 2020

Source:Intelwebpage(www.intel.com)

InternationalTechnologyRoadmapforSemiconductors

LimitsofMooresLaw?
Growthexpecteduntil30nmgatelength(currently:180nm) sizehalvedevery18mos. mos reachedin 2001+1.5log2((180/30)2)=2009 whatthen? Paradigmshiftneededinfabricationprocess

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ICFabrication
Goal:Massfabrication(i.e. simultaneousfabrication) ofmanyICchips chips oneachwafer,eachcontaining millionsorbillionsoftransistors Approach:Formthinfilmsofsemiconductors,metals, andinsulatorsoveranentirewafer,andpatterneach layerwithaprocessmuchlikeprinting(lithography).
Planarprocessingconsistsofasequenceof additiveandsubtractivestepswithlateralpatterning
oxidation deposition p ion implantation etching lithography

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PlanarProcessing g
(patentedbyFairchildSemiconductorin1959:J.A.Hoerni,USPatent3,064,167)

DEPOSITION ofathinfilm LITHOGRAPHY


Coatwithaprotectivelayer Selectivelyexposetheprotectivelayer Developtheprotectivelayer

ETCH toselectivelyremovethethinfilm Strip(etch)theprotectivelayer


14 CourtesyofDr.BillFlounders,UCBerkeleyMicrolab

OverviewofICProcessSteps
Test E i Epitaxy BareSilicon Wafer Processed Wafer

Deposition/growth Anneal CMP IonImplantation MaskPattern Generation

CDSEM Metrology

Defect Detection

Etch CourtesyofDr.BillFlounders,UCBerkeleyMicrolab

Lithography 15

Whatareshownonpreviousdiagramscoveronlythesocalledfrontend processing fabricationstepsthatgotowardsformingthedevicesand interconnectionsbetweenthesedevicestoproducethefunctioningIC's.The endresultarewaferseachcontainingaregulararrayofthesameICchipor die.Thewaferthenhastobetestedandthechipsdicedupandthegoodchips mountedandwirebonded indifferenttypesofICpackageandtestedagain beforebeingshippedout.

From Howe, Sodini: Microelectronics:An Integrated Approach, Prentice Hall

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RecurringCosts
Whilethecostofproducingasingletransistorhasdroppedexponentiallyoverthepastfew decades,thebasiccostequationhasntchanged.Costofacircuitisdependentuponthe chiparea.

costofdie+costofdietest+costofp packaging g g variable i bl cost t = finaltestyield costofwafer costofdie= diesperwafer dieyield


dieyield =(1+(defectsperunitarea diearea)/)

Alphadependsuponthecomplexityofthemanufacturingprocess(andisroughlyproportional tothenumberofmasks).AgoodestimatefortodayscomplexCMOSprocessisalpha=3. Defectsperunitareaisameasureofthematerialandprocessinducedfaults.Avalue between0.5and1defects/cm2 istypicaltodaybutstronglydependsuponthematurityofthe process. p

(waferdiameter/2)2 waferdiameter diesperwafer = 17 diearea 2 diearea

YieldExample

Example

wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2, = 3 (measure of manufacturing process complexity) 252 dies/wafer (remember, wafers round & dies square) die yield of 16% 252 x 16% = only 40 dies/wafer die yield !

Die cost is strong function of die area

proportional to the third or fourth power of the die area

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SystemSpecification
Functional Simulation Specifications

Function/Archt.design
Logic Simulation Behavioral Representation

LogicSynthesis
Circuit Analysis Structural Representation

CircuitDesign
Extractionand Verification Structural Representation

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(Continued)

Extractionand Verification

Structural Representation

PhysicalSynhtesis
Physical Representation

Fabrication

Packaging

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